Lab Manual 8085 Microprocessor

PH 311 Laboratory Manual
Contents
Instructions to students
01
Expt. #1:
Universality of NOR gate & De Morgans laws
02
Expt. #2:
Half Adder, Half Subtractor, Full Adder, Multiplexer and Demultiplexer
04
Expt. #3:
NAND latch, J-K Flip-flop, shift register and ripple counter
07
Expt. #4.
Comparator, encoder and decoder circuits
11
Expt. #5.
4-bit adder/subtractor and Static RAM
15
Expt. #6.
Programming exercises using 8085A P trainer kit
18
Expt. #7.
Simple interfacing exercises using 8085A P trainer kit
20
Expt. #8.
Interfacing of 8-bit A/D and D/A cards with 8085A P kit
25
Expt. #9.
Interfacing and control of a stepper motor with 8085A P kit
29
Appendix
31
Department of Physics
Indian Institute of Technology Guwahati
JulyNovember, 2015
Instructions to students
This manual contains instructions for performing nine sets of experiments in digital electronics.
Two three-hour slots have been allotted every week to perform each of these nine experiments.
All experiments have to be performed independently by each student. Each experiment has two
sections. In the first part, circuits and procedures are provided for the students to achieve the
aims specified. This compulsory part is to be performed as instructed. At the end of this
section, some exercises are given, which are within the scope of the knowledge of the students
of this course. The students have to make their own circuits (for which any standard text book
can be referred) and perform these exercises within the allotted time.
The students are expected to come prepared to the lab with the relevant background
reading required for the experiment. Devote a file folder for the lab reports. Your preparation
for the experiment (prior to entering the lab) includes a write-up containing the title,
objective(s), circuit diagram(s), truth table(s), Boolean expression(s) related to the entire
experiment including the exercises. Once inside the lab, you are expected to wire up the
circuits, generate the relevant truth table(s) and get them endorsed by the instructor. You
should then proceed to experiment with the exercises provided (for which you should have
come prepared with circuit diagrams) and demonstrate those experiments to the instructor. The
lab report of each experiment (including the exercises) is to be completed and submitted by the
end of each lab session.
During the 8th week of this course, each student has to propose a mini project based on
the knowledge and experience acquired during the earlier laboratory classes. The proposal
consisting of the basic idea behind the circuit, its use along with the relevant circuit diagram(s)
and component list has to be submitted latest by the 8th week of the semester.
Components/instruments available with the department would be provided for this work, if
specified in the proposal. Ensure availability of the components before submitting the proposal.
The students should complete and demonstrate their mini project during the last lab session.
This would be followed by an end-semester (lab) exam.
Assessment of PH 311 is based on your (i) preparation for the lab classes and
performance in the lab including the exercises, (ii) mini project work, and (iii) performance in
the end-semester practical examination. Contact any of the instructors if you have any doubts
about this course. Hope you enjoy the course.
Course Instructors PH 311 (July-November 2015).
Electronics Lab II (PH311), 2015
B. Tech. Eng. Physics
Page 1
EXPERIMENT #1
AIM :
a)
b)
To verify the universality of NOR gate.

To verify De Morgans Laws.
APPARATUS /COMPONENTS REQUIRED:

Power Supply (1 No.), Multimeter (1 No.), IC 7404 (NOT), IC 7432 (OR), IC 7402 (NOR)
IC 7408 (AND) and IC 7400 (NAND) one each.
PROCEDURE:
Wire up the circuits given below (for pin diagram of the ICs, refer the Appendix-B of
this manual).
Apply inputs A and B.
Generate the truth table for each of the circuits (0 Volts 0, 5 Volts 1).
(1) CIRCUIT DIAGRAM:

7402
7402
7402
7402
A
B
NOT Gate
OR Gate
7402
7402
B
7402
AND Gate
7402
A
7402
7402
Y
7402
B
XOR Gate
Fig. 1.1: NOT, OR, AND & XOR GATE
Page 2
(2) CIRCUIT DIAGRAM:

7404
De Morgans laws:
A
(i) A . B = A + B
(ii) A + B = A . B
7432
7400
A
B
Y = A+ B
Y = A.B
7404
B
A
7402
A
B
7404
Y = A+ B
7408
Y = A.B
7404
B
Fig. 1.2: Verification of De Morgans Laws
TYPICAL TRUTH TABLE 1:
INPUT
A
B
0
0
0
1
1
0
1
1
OUTPUT (Y)
VOLT LOGIC
EXERCISE:
1. Verify that NAND gate is a universal gate.
2. Design and verify a 5-bit odd parity checker.
*****
Page 3
EXPERIMENT #2
AIM :
Design and test half adder, half subtractor, full adder, 2-to-1 multiplexer and
1-to-2 demultiplexer circuits.
Power Supply (1 No.), Multimeter (1 No.), IC 7404 (NOT), IC 7486 (XOR), IC 7408 (AND),
IC 7432 (OR) (two each), IC 7402 (NOR) (one) and LEDs.
PROCEDURE:
Wire up the circuits (for pin diagram of the ICs, refer the Appendix-B of this manual).
Apply inputs A and B.
Generate the truth table for each of the circuits [0 Volts 0 , 5 Volts 1].
(1) CIRCUIT DIAGRAM: HALF ADDER
Fig. 2.1: Half Adder
TRUTH TABLE 2.1:
INPUT
A
B
0
0
1
1
OUTPUT (Y)
CARRY
SUM
LOGIC
VOLT LOGIC VOLT
0
1
0
1
Page 4
(2) CIRCUIT DIAGRAM: HALF SUBTRACTOR
Fig. 2.2: HALF SUBTRACTOR

TRUTH TABLE 2.2:
INPUT
A
B
0
0
1
1
OUTPUT (Y)
BORROW
DIFFERENCE
VOLT LOGIC VOLT LOGIC
0
1
0
1
(3) CIRCUIT DIAGRAM: FULL ADDER
Fig. 2.3: FULL ADDER
TRUTH TABLE 2.3:

INPUT
A
B
C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
OUTPUT (Y)
CARRY
SUM
VOLT LOGIC VOLT LOGIC
0
1
0
1
0
1
0
1
Page 5
(4) CIRCUIT DIAGRAM: 2 TO 1 MULTIPLEXER
Fig. 2.4: MULTIPLEXER
(5) CIRCUIT DIAGRAM: 1 TO 2 DEMULTIPLEXER
Fig. 2.5: DEMULTIPLEXER
EXERCISE:
1. Design and verify an adder cum substractor circuit.
2. Design and verify a nibble multiplexer.
*****
Page 6
EXPERIMENT #3
AIM :
Design and test a NAND latch and JK flip-flop and use the latter to construct
a 4-segment shift register and ripple counter.

Power Supply (1 No.), Multimeter (1 No.), NAND (IC 7400), JK Flip Flop (IC 7476), NOT
(IC 7404), LED (4 No.), 1 K Resistance (4 No.), Digital Storage Oscilloscope (DSO), switches
PART A.: BASIC LATCH CIRCUIT USING NAND GATE.
PROCEDURE :
Analyze the circuit and make the truth table.

Wire up the circuits as shown in Fig 3.1.
Test the out put (LED) by using all possible combinations of inputs for P and R.
Replace the power supply with a function generator (and a NOT gate if required) for
generation of all possible combinations of inputs P and R.
Remove LED and connect both the outputs on different channels of the Digital Storage
Oscilloscope (DSO).
Display both the inputs and outputs on DSO.
Record the wave shape for all the possible combinations.
7400
Fig.3.1: Basic latch using NAND gate
Page 7
PART B: J-K FLIP FLOP:

PROCEDURE:
Assemble the circuit as shown in Fig 3.2.

Initially set clock pulse at 0 level and check the out put for
i.
C at 1 and P at 0 and
ii.
C at 0 and P at 1.
Momentarily disconnect the SW2 (so as to ensure clock=0) and then release it (making
Clock=1) to enable the flip-flop.
Verify the truth table for enabled condition of the flip-flop (of step 1 and 2).
Repeat step 3 for all possible combinations of input J and K to generate the truth table.
Replace power supplies V1 and V2 with the signal from the function generator. For
clock frequency use TTL signal from the function generator. Set the frequency to ~10
KHz. Display J and K inputs and the output on the DSO. For various combinations of
inputs (all the rows of the truth table) you may be required to use a NOT gate.
Record the output for all the combinations. Trace the wave forms or record the data.
Fig 3.2: J-K flip flop
Page 8
PART C: DESIGN AN ASYNCHRONOUS COUNTER: RIPPLE DOWN COUNTER

PROCEDURE:
Assemble the circuit as shown below in Fig. 3.3.

Enable the circuit as done in the previous part.
Apply an input clock from the function generator (TTL pulse) at low frequency (1 Hz10 Hz).
Observe the ON-OFF sequence of the LEDs and verify the truth table.
Remove the LEDs and record the waveform using the DSO. Measure the delay in
subsequent signals and discuss the results.
Fig 3.3: RIPPLE DOWN COUNTER
Page 9
PART D: DESIGN A 4 BIT SERIAL IN PARALLEL OUT SHIFT REGISTER

PROCEDURE:
1. Assemble the circuit of Fig 3.4. Connect the out put of all the flip-flops to LEDs via 1
k resistances.
2. Set the Function Generator for square waveform with period of 10 (or 5) second.
Connect function generator output to clock input of the Shift Register Circuit.
3. Enable the circuit.
4. Manually apply an input of logic 1 into the first flip-flop when clock is in high state.
Circuit will take input only when High to Low transition of clock state takes place (as
in the previous experiment). This can be observed by displaying the clock pulse
simultaneously on DSO and observing the ON-OFF sequence of the first LED.
5. Once the circuit takes the input as logic 1, bring the input to logic 0. Then check
the serial shift of this bit through the shift register for each High to Low transition of
clock state by observing the LEDs and verify this circuits behavior.
6. Display the three Shift Resister output & the Clock on the DSO and repeat step 4 above
7. You may also repeat step 4 and 6 above by displaying the output of all four shift
register on the DSO.
Fig. 3.4: SERIAL IN PARALLEL OUT SHIFT REGISTER
EXERCISE:
1. Design and verify decade (MOD-10) counter..
2. Design and verify Up-Down counter.
*****
Page 10
EXPERIMENT #4
AIM :
Design and test comparator, encoder and decoder circuits.
NOT (IC 7404-3 Nos), XOR (IC 7486-2 Nos), OR (IC 7432 -4 Nos), AND (IC 7408-2 Nos),
3-i/p NAND (IC 7410 -2 Nos), LED (10 No.), 1 K Resistance (4 No.).
PART A.: DESIGN AND TEST OF 2-BIT MAGNITUDE COMPARATOR
.PROCEDURE :
Analyze the circuit and derive the appropriate Boolean expression for each of the
outputs.
Wire up the circuit as shown in the fig 4.1 below.
Logical inputs are given in the truth table 4.1.
Test the output (using LED and multi-meter) by using all possible combinations of
inputs.
LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR
Fig. 4.1: MAGNITUDE COMPARATOR
Page 11
TRUTH TABLE 4.1:
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
INPUT
A0 B1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
A>B
VOLT LOGIC
OUTPUT
A=B
VOLT LOGIC
A<B
VOLT
LOGIC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PART B: DESIGN AND IMPLEMENTATION OF ENCODER

PROCEDURE :
Analyze and wire up the circuits as shown in the circuit diagram (Fig. 4.2).
Test the output (using LED and multi-meter) by using all the possible combinations of
inputs by connecting a 5 V power supply with the help of switches.
Page 12
LOGIC DIAGRAM: ENCODER
Fig. 4.2: ENCODER
TRUTH TABLE 4.2:

INPUT
OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7
VOLT LOGIC VOLT LOGIC VOLT LOGIC

1
Page 13
PART B: DESIGN AND IMPLEMENTATION OF DECODER

PROCEDURE :
Analyze and wire up the circuits as shown in the figure below.
Test the output (using LED and multi-meter) by using all the possible combinations of
inputs.
LOGIC DIAGRAM: DECODER
Fig. 4.3 DECODER
TRUTH TABLE 4.3:

INPUT
E
OUTPUT
B
D0
VOLT
D1
LOGIC
VOLT
D2
LOGIC
VOLT
LOGIC
D3
VOLT
LOGIC
EXERCISE:
1. Demonstrate a BCD validation unit (Output is 1 if inputs are from 1010 to 1111).
2. Demonstrate a 2/4 active-high line decoder (Only 1 of 4 outputs is 1 for any input S1S0)
*****
Page 14
EXPERIMENT #5
AIM :
Perform addition / subtraction, using a 4-bit adder chip, store the result in a
static RAM IC and retrieve the stored result from the RAM IC.
APPARATUS/COMPONENTS REQUIRED:
Power Supply (1 No.), Multimeter (1 No.), 4-bit parallel adder (IC 7483), IC7486, 4-bit static
4K RAM (IC 2114 1 Nos), LED (5 Nos).
PROCEDURE:
Adding and subtracting 4-bit no.
For functional description of 4-bit static 4K RAM (IC2214) and 4-bit parallel adder (IC
7483), refer to the data sheets.
Give the two 4-bit inputs (A3A2A1A0 & B3B2B1B0) to the adder chip through XOR
gates.
For addition operation, connect CIN to ground (GND or logic 0) and for subtraction
operation, connect CIN to +5V (logic 1).
The LEDs connected to the S3S2S1S0 provide the result of the addition/subtraction
result.
Fig. 5.1: 4-bit Addition and subtraction

Page 15
TO STORE A RESULT IN STATIC RAM:
Wire up the circuit to store output of IC 7483 in IC 2114 (Static RAM).

For functional description of 4-bit static 4K RAM (IC2114) and 4-bit parallel adder (IC
7483), refer to the data sheets.
Give the two 4-bit inputs ((A3A2A1A0 & B3B2B1B0)) to the adder circuit and store the
result in static RAM.
For writing data, make both WE and CS input low in IC2114.
Select any address input from A9 to A0, (say, A3A2A1A0) keeping the others in 0 state
and connect the data inputs to I/O4 I/O3 I/O2 I/O1.
By performing the last two steps, data can be stored in the memory location specified
by you.
CIRCUIT DIAGRAMS:
VCC
WE
VCC
VCC
14
B0
B1
B2
B3
12
13
11
9
10
4
5
1
2
7
4
8
3
11
7
GND
CS
12
9
6
2
15
14
S0
I/O 1
S1
I/O 2
S2
I/O 3
S3
I/O 4
14
13
12
11
18
2
1
1
4
R
A
M
5
6
7
4
3
2
1
17
16
15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
COUT
9
GND
16
7486
A0
10
A1
8
A2
3
A3
1
10
13
CIN
1
+5 V
Fig. 5.2: Storing in static RAM

TO RETREIVE DATA FROM THE STATIC RAM:
Disconnect the data inputs I/O4 I/O3 I/O2 I/O1 from input lines and connect them to
output lines to read the data. You can also wire up four LEDs to I/O4 I/O3 I/O2 I/O1 for
reading the stored data.
For reading data, make WE pin high and CS input low.
Give address inputs of the data you have stored and observe the outputs I/O4 - I/O1.
Page 16
1. Store any 10 consecutive addition/subtraction results in 10 consecutive locations in static

RAM. Then retrieve the data by reading the 10 locations.
2. Modify the adder circuit to a subtractor circuit using IC 7483 adder. Repeat the process for
storing and retrieving the addition/subtraction results.
PIN & LOGIC DIAGRAMS:
EXERCISE:
Make necessary changes in the circuit to store the carry of the addition of the two 4-bit
numbers.
*****
Page 17
EXPERIMENT #6
AIM :
Programming exercises using INTEL 8085A microprocessor trainer kit.
Dyna85 Trainer kit (P8085), Power Supply (SMPS)
BACKGROUND:
A microprocessor (P) trainer kit consists of basic units required for a simple computer,
namely, a microprocessor chip (CPU), memory (EPROM, and RAM), input device (Hex keypad and cassette tape) and output device(seven segment display unit- four address fields
followed by two data fields). Programmable peripheral chips such as 8155 and 8255 provide
the necessary interface between the P and the external circuitry. These physical units
constitute the basic hardware of the system. Software in the form of a set of instructions written
using the 8085 instruction set makes the P perform a set of desired operations. It has to keep
in mind that the instructions should be converted into the hexadecimal form before entry in this
kit. A system program (commonly called the operating system) resides in the EPROM and gets
loaded whenever the kit is switched ON. The MICROFRIEND DYNA-85 kit given in the
laboratory is based on the INTEL 8085 chip. The CPU operates at 3 MHz (system clock). The
RAM locations (C000)16 to (FFFF)16 are available for the user to enter any desired
program. The following single-key system commands are provided in the trainer kit for
facilitating easy operation of the kits.
<RES> Does hardware reset. The word FriEnd appears in the display when pressed
<DCR> Decrements memory address presently displayed
<INR> Increments memory address presently displayed
<EXEC> Starts execution of <GO> command
<SET> Used for modifying contents of RAM locations reserved for the user
<GO> Used for loading the memory address of the beginning of the program
<STEP> For executing program in single step or break-point mode
<REG> Keys let you examine or modify the CPU registers
To use these commands press <REG> and press one A, B, C, D, E, F, 8 or 9 for choosing the
registers A, B, C, D, E, Flag H or L respectively. The flag register bits are
S Z X
AC X P X C
where S is the sign flag, Z is the zero flag, AC is the auxiliary carry flag, P is the plus flag and
C is the carry flag (X means dont care).
Page 18
To enter a program, follow the following sequence:

<RES>
<SET> C000
XX
! first hex instruction is entered in the place of XX
<INR>
! this command increments address to C001
.
! enter the entire program by keying one 8 bit no. in hex
.
in each location and moving to next by pressing <INR>
<INR> 76
! last instruction in the program
To execute the entered program, use the following commands:
<RES>
<GO> C000
! load program which starts at address C000
<EXEC>
! execute the loaded program
It is usually desired that the result of a computation is readily available after the execution of
the program. The subroutine called MODIDT which resides in the EPROM at the address
(036E)16 can be used to display the contents of register A (Accumulator) to the data fields of
the display units. In order to use this to display the result of any computation use following
sequence instructions:
<move result to register A>
<move zero into register B>
CALL MODIDT
! Key in the address 03 6E in the place of MODIDT
It should be remembered that the CALL MODIDT commands changes the state of all CPU
registers and all flags and hence be careful & use this only towards the end of the program.
PROGRAMS TO BE ENTERED AND TESTED:
1.
2.
3.
4.
Multiplication of two 8-bit numbers by successive addition method.

Multiplication of two 8- bit numbers by shift left & add method.
Divide the given numbers and display quotient in display fields.
Divide the indivisible numbers and display the quotient in display field and store reminder
in location some memory location.
5. Load ten 8-bit numbers in ten memory locations and sort them in ascending order.
EXERCISE:
1. Program to implement BCD to BINARY conversion.
2. Program to simulate THROW OF A DICE (one dice with six faces)..
*****
Page 19
EXPERIMENT #7
AIM :
Simple interfacing exercises using INTEL 8085A microprocessor trainer kit.
Multimeter 1 Nos , Dyna85 Trainer kit (P8085- 1 Nos), Power Supply (SMPS 1 Nos),
Flat Ribbon Cable (FRC) 1 Nos, 7-Segment LED (MAN-74A- 2 Nos) , BCD-to-SevenSegment Decoder (74LS48P 1 Nos), LEDs -10 Nos
PREREQUISITE:
Knowledge of interfacing peripherals 8155A and 8255A (Ref: Appendix C & E) which are
parts of the 8085 Microprocessor kit.
PART A: To generate binary equivalent of sequence of hexadecimal numbers from 00H to
0FH and display the binary numbers by activating 8 LEDs using 8155A interfacing
peripherals.
DIAGRAM:
Fig.7.1
CONNECTION TABLE 7.1:
Pin Number
1
2
3
4
6
7
8
9
26
Signal Name
PA3
PA2
PA1
PA0
PA7
PA6
PA5
PA4
GND
Bit position represented by LED

2-5th bit
2-6th bit
2-7th bit
LSB (2-8th bit)
MSB (2-1th bit)
2-2th bit
2-3th bit
2-4th bit
Short cathode of all the LEDs
together and connect them to GND
Page 20
FOR 8155A
ADDRESS OF PORT A=09H, ADDRESS OF PORT B=0AH,
ADDRESS OF PORT C=0BH, ADDRESS OF CONTROL REGISTER=08H,
PORT A SPECIFICATION = OUTPORT, MODE 0, PORT B SPECIFICATION= OUTPORT , MODE 0
MEMORY MACHINE MNEMONICS
COMMENTS
ADDRESS
CODE
C000
3E, 03
MVI A, 03H
C002
D3, 08
OUT 08H
C004
3E, 06
MVI A, 06H
C006
C008
D3, 09
76
OUT 09H
HLT
Control word to initialize I/O PORTs of 8155: Ports

A and B are configured as output and Port C as
input port.
Writing Control Word to control register of 8155,
whose address is 08 in Dyana85 P kit.
Get 06 into accumulator as we want to display
binary equivalent of 06.
Send 06 to Port A whose address is 09H
Stop
PROCEDURE:
1. For learning about interfacing peripherals 8255 & 8155, refer the Appendix-C.
2. Understand the given program and load it in the specified memory locations. Here the
control word of 8155A is set in such a way that PORT-A is configured as OUTPUT
port (in memory location C000 to C003).
3. Connect the 26-Pin FRC to J2 connector of the P kit and the 8 LEDs as specified in
the table 7.1 and in Fig. 7.1.
4. Run the program and observe the LED status.
5. Change the program to display various sequences of number from 00H-0FH (in C005
memory location) and observe the output.
PART B: To activate a 7-Segment LED and display any decimal number from 0 to 8 using
8155A.
BACKGROUND:
7-Segment LED:
The 7segment LED display is a multiple segment LED display module. It can display all
decimal digits and some letters by activate appropriate LED segments. Each of the 7 LED
segments can be controlled separately. To display a digit or letter, the desired segments are
made ON as described in the figure below. Two types of 7segment LEDs available in the
market are called common cathode and common anode 7-segment LEDs.
Common Cathode: In this type, all the 7 cathodes of LEDs are tied together to the ground.
When a +5V signal is applied to any segment, corresponding diode emits light. Thus, applying
logic 1 i.e, positive logic, to desired segments, the desired letter or decimal number can be
displayed.
Common Anode: In this type, all the 7 anodes of LEDs are tied together and connected to a
+5 V supply. A particular segment will emit light when 0 logic is applied to it.
Page 21
PIN DIAGRAM:
Fig.7.2a
Fig.7.2b
To display digit 1 using this common cathode seven segment LED, the segment b and c
should be turned on. Corresponding binary code should be:
Data Lines :
Bits
Segment
PA7
X
NC
PA6
0
g
PA5
0
f
PA4
0
e
PA3
0
d
PA2
1
c
PA1
1
b
PA0
0
a
=06H
Similarly, by changing the content of the data lines we can display different digits.
Page 22
FOR 8155A
ADDRESS OF PORT A=09H, ADDRESS OF PORT B=0AH,
ADDRESS OF PORT C=0BH, ADDRESS OF CONTROL REGISTER=08H,
PORT A SPECIFICATION = OUTPORT, MODE 0, PORT B SPECIFICATION= OUTPORT , MODE 0
COMMENTS
ADDRESS
CODE
C000
3E 03
MVI A, 03H
C002
D3 08
OUT 08H
C004
C006
C008
3E 06
D3 09
76
MVI A, 06H
OUT 09H
HLT
Control word to initialize I/O PORTs of 8155: Ports

A and Port B are configured as output and Port C as
input modes.
Writing Control Word to control resister of 8155,
whose address is 08 in Dyna85 P kit
Get 06 in accumulator as we want to display 06.
Send 06 to Port A whose address is 09H
Stop
PROCEDURE:
1. Understand the given program and load it in the specified memory locations (say from
C000). Here the control word of 8155A is set in such a way that PORT-A is configured
as OUTPUT port (in memory location C000 to C003).
2. Connect the 26-Pin FRC to J2 connector of the P kit and the 8 LEDs as specified in
the table 7.2 and in Fig 7.2.
3. Run the program and observe the LED status.
4. Change the program to display various sequences of number from 0H-FH (in C005
memory location) and observe the output.
PART C: To activate a 7-Segment LED to display any decimal number from 0 to 8 using
BCD-to-Seven-Segment Decoder (74LS48P) and 8255A.
BACKGROUND: BCD-to-Seven-Segment Decoder (74LS48P) aspects a 4 digit BCD input
and decodes it to a 7 digits output, which is usually used for 7-Segment LED display.
Fig.7.3 BCD-to-Seven-Segment Decoder

Page 23

Pin Number
74LS48P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Connected to Signal
Remark
PB1 Signal from 8255A

NC
NC
NC
GND Signal from 8255A
Pin 1 of Seven Segment LED
+5V D.C
Pin No 19 of FRC Cable


e
d
c
b
a
g
f
FOR 8255A
ADDRESS OF PORT A=10H, ADDRESS OF PORT B=11H,
ADDRESS OF PORT C=12H, ADDRESS OF CONTROL REGISTER=13H,
PORT A SPECIFICATION = INPORT, MODE 0, PORT B SPECIFICATION= OUTPORT , MODE 0
COMMENTS
ADDRESS
CODE
C000
3E 98
MVI A, 98H
C002
D3 13
OUT 13H
C004
C006
C008
3E 05
D3 11
76
MVI A, 05H
OUT 11H
HLT
Control word to initialize I/O PORTs of 8255 : PORT A as an

Input PORT & Mode 0, PORT B as an Output PORT & Mode
0 PORT Cupper as an input PORT and PORT Clower as an
output PORT
Writing Control Word to control resister of 8255, whose
address is 13 in Dyana85 Microprocessor Kit
Get 05 in accumulator as we want to display 5.
Send 05 to Port B whose address is 11H
Stop
PROCEDURE:
1. Connect the 26-Pin FRC to J3 connector of the P kit, decoder (74LS48P) and the
seven segments LED as specified in the table 7.3 and in Fig 7.3 by using a bread board
2. Understand the given program and load the same in the specified memory locations.
3. Run the program and observe the 7 Segment LED display status.
4. Change the program to display various number from 0- 8 and observe the output.
EXERCISE:
1. Fabricate a display panel with two 7-segment display units (each capable of displaying
hexadecimal numbers.
2. Build a display panel which display decimals 00 to 99 using two seven-segment display
units
*****
Page 24
EXPERIMENT #8
AIM :
Interfacing of 8-bit Analog to Digital and Digital to Analog cards with INTEL
8085A microprocessor kit.
Dyna85 Trainer kit (P8085 1 No), ADC Card (Dynalog ADC-08 1 No), DAC Card
(Dynalog DAC-01 1 No), Flat Ribbon Cable (FRC) 2 Nos, Power Supply (SMPS 2 Nos),
LEDs 10 Nos
PART A:
To convert an analog signal to digital signal by interfacing ADC card with the 8085
microprocessor kit, store the data in accumulator and then reproduce the same analog signal by
using DAC card.
Fig. 8.1: Interfacing of 8-bit A to D and D to A cards with 8085A P- kit.

BACKGROUND:
In this experiment, you will learn to connect ADC & DAC cards to 8085 P through PPI
devices 8255 and 8155. The input analog signal will be applied to Channel 0 of ADC card and
the necessary control signal will be supplied by the P. The digital output will be temporarily
stored in the Accumulator and then will be applied to the digital Inputs of DAC card. Finally,
the analog output will be displayed in the DSO and compared with the original input.
The ADC 08 card plugs into the 8255 IC via 26 Pin FRC Connector. Informations on 8255 IC
interface is given in the Appendix. Ports B and Cupper are defined as input and Ports A and
Page 25
Clower in the output ports. Port As PA0, PA1, PA2 are used to multiplex channel select. PB0
PB7 are used for 8-bit digital output from ADC card. PC1, PC2 and PC3 are used as Start of
Conversion (SOC), Enable (ALE) & Output enable (OE) signals. PC4 is used end of
conversion signal (EOC).
The DAC card is plugs into the 8155 IC via 26 Pin FRC Connector. Ports A and Port B are
configured as output port and Ports C as input port. Port Bs PB0 signal gives the allow data
flow signal to the DAC. Port As PA0 PA7 are used for 8-bit digital input to the DAC card.
ADDRESS of PORTS in DYNA85 Microprocessor Kit
8255 IC
8155 IC
Control Register 13H
Control Register
08H
Port A
10H
Port A
09H
Port B
11H
Port B
0AH
Port C
12H
Port C
0BH
PROCEDURE:
1. For details of ADC card, 26 pin Flat Ribbon Cable (FRC) Pin details, interfacing 8255
& 8155 etc., refer the Appendix C , -D & -E of this manual.
2. Before switching on the power supply, check the direction of 26 pin flat cable
connector at both ends. All supply connections +5V, +12V and -12V must be applied
simultaneously to the ADC & DAC cards.
3. Load the program in the P in the specified memory locations.
4. The value in the DE register pair (in location C02D and C02E in the program) will
define the sampling rate by producing a delay. This register pair can be 0000HFFFFH.
5. Input a sinusoidal signal with peak to peak voltage less then 5V and frequency less then
30 Hz from function generator. Sample it with various sampling frequency (as
described in the previous point). [A table containing information of various values of
DE resister pair and corresponding sampling frequency is provided in Appendix-G].
6. Trace both the original input analog signal and the re-constructed signal from DAC
output in the two channel of DSO.
7. Use a signal of a particular frequency (<30Hz) and re-construct it for three set of
different sampling frequencies.
8. Compare the fast Fourier transform (FFT) of the input signal and the reconstructed
signal for different sampling frequency. Analyse the effect of sampling frequency.
Page 26
PROGRAM TO DRIVE ADC AND DAC CARDS

ADDRESS
DATA
MNEMONIC
COMMENT
C000
3E 8A
MVI A, 8AH
C002
D3 13
OUT 13H
C004
3E 03
MVI A 03H
Control word to initialize I/O PORTs of 8255: Ports B

and Cupper are defined as input mode and Ports A and
Clower in the output mode
Writing Control Word to control register of 8255,
whose address is 13 in Dyana85 Microprocessor Kit
Control word to initialize I/O PORTs of 8155: Ports A
and Port B are configured as output mode and Ports C in
input mode.
C006
D3 08
OUT 08H
C008
C00A
3E 01
D3 0A
MVI A 01H
OUT 0AH
3E 00
MVI A 00H
D3 10
OUT 10H
C010
C012
3E 06
D3 12
MVI A, 06H
OUT 12H
C014
3E 04
MVI A, 04H
C016
D3 12
OUT 12H
DB 12
E6 10
FE 10
C2 18 C0
IN 12H
ANI 10H
CPI 10H
JNZ LOOP
C021
C023
C025
3E 0B
D3 12
DB 11
MVI A, 08H
OUT 12H
IN 11H
C027
D3 09
OUT 09
C00C
C00D
C00E
C00F
C018
C01A
C01C
C01E
LEBEL
LOOP1
LOOP
Writing Control Word to control resister of 8155, whose

address is 08 in Dyana85 Microprocessor Kit
PB0 high signal gives the allow data flow signal to the
D/A Converter
Loading first Accumulator with '00' and then PORT A
whose address is 10. This instruction sets Pins 23, 24,
25 of 0809 to Low state hereby selecting CH0. (By
setting these three pins low or high or combination of low and high
state, one can select different multiplexed channels (Ch- 0 to Ch-7)
of the ADC. By setting all three pins to low Ch-0 is selected (as in
this case).
Loading Accumulator with '06' and then sending it to

PORT C. These instructions direct 0809 to start
conversion by making SOC and ALE PINs of 0809 to
High state
Loading Accumulator with '04' and then sending it to
PORT C. These instructions direct 0809 to start
conversion by making SOC and ALE PINs of 0809 to
Low state.
Check for End-of-Conversion Pin status. If Conversion
is over then status of SOC Pin of 0809 will be High.IN
instruction make the Bit 4 of accumulator to 1. ANI
instruction will do logical AND operation with 10H
and content of accumulator, the result will be compared
with 01H by CPI instruction. If conversion is over then
ZERO flag should be SET to high. If ZERO flag is not
set then JNZ instruction takes program control to
previous IN instruction i.e. to C018 for further
checking and it continues until the EOC pin is high. If
conversion is over i.e. EOC pin is high, then program
proceeds ahead.
Enable output
This instruction scans for the contents of PORT B and
loads it in Accumulator.
This instruction sends the contents of Accumulator to
Port A of 8155.
Page 27
C029
CD 6E 03
CALL
MODIDT
Calling the Monitor Program stored at location 036E .

This instruction will display the contents of
Accumulator in systems LED monitor.
Load FFFFH in DE register pair. The content of DE
register pair decides the scanning rate.
Calling the delay sub-routine in location 05F1.
C02C
11 FF FF
LXID FFFFH
C02F
CD F1 05
C032
C3 0C C0
CALL
DELAY
JMP LOOP1
Jump to C00C
C035
76
HLT
Stop
PART B:
To generate a square wave signal of any frequency between 1 Hz to 10 Hz using DAC Card.
PROCEDURE:
1. With the experience of driving the DAC card in the previous experiment, write a program
to generate square wave of any frequency between 1Hz to 10 Hz using a DAC card.
2. Before switching on the power supply, check the direction of 26 pin flat cable connector at
both ends. All voltages (+5, +12 and -12 V) must be applied simultaneously to the DAC.
3. Load the program in Microprocessor in the specified memory locations.
4. Connect the output of DAC card to Digital Storage Oscilloscope (DSO).
5. Trace the signal from the DSO.
EXERCISE:
1
2
Write a program to generate triangular waves of any frequency between 1 Hz to 10 Hz

using DAC card.
Write a general program to convert any input signal (say, square or triangular) with
frequency in the range of 1 Hz to 10 Hz into digital signal.
******
Page 28
EXPERIMENT #9
AIM :
Interfacing a stepper motor with 8085A microprocessor kit and its control.
Dyna85 trainer kit (8085 P - 1 No), stepper motor controller card (STP-PIO 1 No) , stepper
motor ( 1 No) , power supply (SMPS - 1 Nos)
PROCEDURE:
1. To understand the working of the stepper motor controller card / 26 pin FRC pin details /
interfacing details of 8255 or 8155 to the P etc., refer Appendix-C, -D, -E & -F.
2. Feed and run the given program using the 8085 P kit. You can write your own program
to run the stepper motor in free running and step wise mode. Try to run the stepper motor
in continuous mode / step mode with different speed (rpm).
3. Perform the following operations: Activate the motor at desired rpm value, make it rotate
in both directions (clock-wise and anti clock-wise), interrupt it while in motion and
restart, set it for desired no. of revolutions, etc.
4. Excitation sequence of the stepper motor: Following hexadecimal numbers
(excitation Sequence) are to be entered in the specified memory locations
Memory Location
Excitation code
C0E0 to C0E4
06 0A 09 05 00
C1E0 to C1E4
05 09 0A 06 00
A)
Direction of rotation
For clock-wise movement
For anti clock-wise movement
Free running (continuous) mode: The motor will rotate continuously until the RST
button is pressed. Speed control can be implemented by calling a delay sub-routine after
each step of the rotation)
Program:
ADDRESS
D000
D002
D004
OPCODE
3E 80
D3 13
06 04
D006
21 E0 C1
D009
D00A
D00C
7E
D3 10
11 05 05
D00F
CD F1 05
LABEL
START
MNEMONICS
MVI A 80
OUT 13
MVI B, 04
LXI H, C1E0
BACK:
MOV A, M
OUT 10
LXI D, 0505
CALL 05F1
COMMENTS
: Configuring Control register
: Counts excitation sequence
: Initialize memory pointer
C1E0 for clock-wise, and
C0E0 for anti clock-wise
: Get the Excite code
: Send Excite code
:Calling system defined delay
routine to control speed (by
varying the lower order operand
between 00 and FF.
Page 29
D012
D013
D014
D017
D019
23
05
C2 09 D0
C3 04 D0
FF
INX H
DCR B
JNZ BACK
JMP START
RST 7
: Increment pointer
: Repeat 4 times
Load the program in the above mentioned memory locations and execute the program.
Change the direction of movement by changing the program at location D006.
Change the rotation speed by changing the lower order operands from 00 FF of the
LXI D instruction.
B) Step-wise operation mode: In this mode, the motor will make a defined number of steps
which can be implemented by adding an additional step variable (which defines number
of steps) and a decrement command followed by a jump on non-zero command in
program given above.
Load the program in the mentioned memory locations and execute the program.
To change the number of steps, change the operands of the MVI C instruction.
Change the direction of movement by changing the program at location D008.
Change the speed of rotation by changing the lower order operands from 00 FF of
the LXI D instruction.
Program:
ADDRESS
D000
D002
D004
D006
OPCODE
3E 80
D3 13
0E 0A
06 04
LABEL
D008
21 E0 C1
D00B
D00C
D00E
7E
D3 10
11 05 05
D011
CD F1 05
CALL 05F1
D014
D015
D016
D019
D01A
D01D
D020
23
0D
CA 20 D0
05
C2 0B D0
C3 06 D0
FF
INX H
DCR C
JZ END
DCR B
JNZ BACK
JMP START
RST 7
START
MNEMONICS
MVI A 80
OUT 13
MVI C 0A
MVI B, 04
LXI H, C1E0
BACK
END
MOV A, M
OUT 10
LXI D, 0505
COMMENTS
:Configuring control register
: Counts number of steps
:Counts excitation seq.
: Initialize memory pointer
C1E0 for clock-wise and
C0E0 for anti clock-wise
: Get the Excite code
: Send Excite code
:Calling system defined delay
routine to control the speed
(by varying the lower order
operand from 00 FF
: Increment pointer
: Check no of steps over? If
yes, then jump to END.
: Repeat 4 times
EXERCISE:
1. Write and test a program to simulate a car wiper using a stepper motor.
2. Design of a digital clock (seconds hand only) using 8085 P kit and the stepper motor.
******
Page 30
A P P E N D I X A : BREAD BOARD
The breadboard consists of two terminal strips and two bus strips (often broken in the centre).
Each bus strip has two rows of contacts. Each of the two rows of contacts is a node. That is,
each contact along a row on a bus strip is connected together (inside the breadboard). Bus
strips are used primarily for power supply connections, but are also used for any node requiring
a large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on
each side of the centre gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit components
into the contact receptacles and making connections with 22-26 gauge wire. There are wire
cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power
supply connections to separate bus strips.
Fig. A-1 : Schematic diagram of a breadboard. The lines indicate connected holes.
Page 31
APPENDIX B : COMPONENT LAYOUT IN ICs
Page 32
Page 33
Page 34
A P P E N D I X C : PROGRAMMABLE PERIPHERAL INTERFACE

ADDRESS of PORTS in DYNA85 Microprocessor Kit
8255 IC
8155 IC
Control Register 13H
Control Register
08H
Port A
10H
Port A
09H
Port B
11H
Port B
0AH
Port C
12H
Port C
0BH
8255 Programmable Peripheral Interface
Intel 8255 is a programmable peripheral interface (PPI). It has three 8-bit ports namely Port A,
Port B and Port C. The Port C further divided into two 4-bit ports, namely, Port C upper
(Cupper) and Port C lower (Clower). Thus a total 4 ports are available, two 8-bit ports and two 4bit ports. Each port can be programmed either as an input port or output port sending control
word signal from microprocessor. In our experiment we will configure the ports of 8255 as per
following status:
Port A as an input port and Mode of the Port A Mode 0
Port B as an output port and Mode of the Port B Mode 0
Port Cupper as an input port
Port Clower as an output port
The control word bits for the above definition of the ports are shown in the following figure:
Fig : Control word bits for 8255 in our experiment
Page 35
8155 Programmable Peripheral Interface:

Intel 8155 is a programmable peripheral interface (PPI). It has two 8-bit ports namely Port A,
Port B and one 6-bit port namely Port C upper (Cupper). Each port can be programmed either as
an input port or output port sending control word signal from microprocessor.
The control word =98 H

Bit No. 0 is set to 0, as the Port Clower is an output port
Bit No. 1 is set to 0, as the Port B is an output port
Bit No 2 is set to 0 , as the Port B has to operate in Mode 0.
Bit No 3 is set to 1 , as the Port Cupper is an input port
Bit No. 4 is set to 1, as the Port A is an input port
Bit No. 5 and 6 are set to 00, as the Port A has to operate in Mode 0.
Bit No.7 is set to 1, as the Ports A , B and C are used as simple input/output port
Binary control word: 1001 (decimal eqv=9) 1000(decimal eqv= 8)
Thus the control word is 98H.
Page 36
A P P E N D I X D : ADC0809 & DAC0800
ADC 0809 :
The ADC 0808 (or 0809) is an 8-bit A/D converter (ADC) with 8-channel multiplexer. It is
a monolithic CMOS chip manufactured by National Semiconductors. The ADC uses
successive approximation as the conversion technique. It does not require external zero
and full scale adjustments. There is no terminal available for sample and hold between the
multiplexer and comparator stages. Figures displayed below show the schematic diagram
and the timing diagram of ADC 0808/0809. The device operates with a single 5 V d.c.
supply. The conversion time is 100 ns at clock frequency 640 KHz. The resolution is 8
bits. Error 1 LSB.
Fig: Schematic diagram of ADC0809
Fig: Timing Diagram of ADC0809
Page 37
Some important characteristics of ADC 0809 are as follows:

Electrical CharacteristicsMinimum Start Pulse Width
100 ns
Minimum ALE Pulse Width
100 ns
Clock Frequency
10 to 1280 KHz
Conversion Time
100 nS at 640 KHz
Resolution
8 bits
Error
1 LSB
Ref. (+) should not be more positive than supply. Ref. (-) should not be more
negative than ground.
Supply
5 V d.c.
Logical "I" Input Voltage
Min Vcc-1.5
Logical "0" Input Voltage
Max. 1.5 V
Logical "I" Output Voltage
Min. : Vcc-O.4
Logical "0" Output Voltage
Max. : 0.45 V
DAC 0800 :
The DAC 0800 is a simple monolithic 8-bit D/A converter (DAC). Pin diagram and interfacing
connections of the DAC are shown below. It has fast settling time (~100 ns). It can be directly
interfaced to TTL, CMOS, PMOS and others. It operates at 4.5 V to +18 V supply. The supply
V+ may be either +5 V or +12 V. V- is kept at -12 V, being easily available on standard power
supply units.
Page 38
A P P E N D I X E : P i n - o u t c o n f i g u r a t i o n o f J 2 / J 3 Connector of Dyna85 P Kit
CONNECTOR J2 : 8155 CONNECTOR

Pin No
Signal Name
1
PA3
2
PA2
3
PA1
4
PA0
5
VCC
6
PA7
7
PA6
8
PA5
9
PA4
10
TIM OUT
11
TIM IN
12
PC5
13
PC4
14
PC0
15
PC1
16
PC2
17
PC3
18
PB0
19
PB1
20
PB2
21
PB3
22
PB4
23
PB5
24
PB6
25
PB7
26
GND
CONNECTOR J3 : 8255 CONNECTOR

Pin No
Signal Name
1
PA3
2
PA2
3
PA1
4
PA0
5
VCC
6
PA7
7
PA6
8
PA5
9
PA4
10
PC7
11
PC6
12
PC5
13
PC4
14
PC0
15
PC1
16
PC2
17
PC3
18
PB0
19
PB1
20
PB2
21
PB3
22
PB4
23
PB5
24
PB6
25
PB7
26
GND
A P P E N D I X F : STEPPER MOTOR CONTROLLER CARD

Stepper motors have immense applications in printing, industrial robotics, precision tool
motions in drilling, cutting and shaping machines, lathe etc. The aim of experiment #9 is to
demonstrate interfacing of stepper motor to 8085 microprocessor and to run it in continuous or
stepped motion in forward or reverse direction in a programmable manner using 8085
microprocessor.
Page 39
The hardware setup consists of a microprocessor trainer kit and stepper motor interface board.
The stepper motor interface consists of driver transistors (current amplifiers) for energizing
stepper motor windings and address decoding circuit. The microprocessor outputs the binary
sequence (programmed) through the data bus, which is converted in to current pulses by the
driver transistors and used for driving the stepper motor.
Fig. F-1
The STP-PIO card interfaces with the microprocessor kit and has the capability to drive 12 V
d.c., 5 A/phase stepper motor and has the choice of two rotating directions. The card can be
used for varying the rotation speeds in terms of 00H to FFH steps, which can be programmed.
The dynamic torque is mainly controlled by the drive circuit and the output transistors can give
up to 3 A current. The maximum working temperature of the stepper motor is 30 to 40 C
above the ambient. The schematic diagram of the stepper motor is shown as in Fig.F-2.
Page 40
Fig.F-2: The schematic diagram of the stepper motor
Switching Logic 4
Input Sequence Step
Input Sequence
Step
SW1
SW2
Ph-1
Ph-2
Hex Value
A1
B1
A2
B2
05
09
0A
06
05
The control s/w is in 8085 assembly language. The control word is written to the 8255 IC to
select speed, direction and motor ON/OFF states. The numbers of rotation steps can also be
programmed. After program execution, the motor starts and rotates in the selected direction
with the chosen speed. It stops after the specified number of steps. Stepper motors (four phase)
available in the lab require 12V DC and 5 A/phase. The step angle of the stepper motor is -1.8
with an error of up to 5% and their holding torque is 2 kg cm.
Page 41
A P P E N D I X G : CONTENT OF DE-RESISTER PAIR FOR VARIOUS SAMPLING

FREQUENCY
TABLE G
Frequency(Hz)
250
225
200
175
150
125
100
75
50
25
20
15
10
5
Time
period(ms)
4.0000
4.4444
5.0000
5.7143
6.6667
8.0000
10.0000
13.3333
20.0000
40.0000
50.0000
66.6667
100.0000
200.0000
Value in Location
C02D
C02E
01
3C
82
DC
5E
05
05
A5
F9
F0
F0
F5
A2
F0
00
00
00
00
01
02
03
04
07
11
16
18
30
60
The Value in
DE-resister
pair
0001
003C
0082
00DC
01FE
0205
0305
04A5
07F9
11F0
16F0
18F5
30A2
60F0
*****
Page 42

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PH 311 Laboratory Manual

Universality of NOR gate & De Morgans laws

Half Adder, Half Subtractor, Full Adder, Multiplexer and Demultiplexer

NAND latch, J-K Flip-flop, shift register and ripple counter

Comparator, encoder and decoder circuits

4-bit adder/subtractor and Static RAM

Programming exercises using 8085A P trainer kit

Simple interfacing exercises using 8085A P trainer kit

Interfacing of 8-bit A/D and D/A cards with 8085A P kit

Interfacing and control of a stepper motor with 8085A P kit

B. Tech. Eng. Physics

To verify the universality of NOR gate.

APPARATUS /COMPONENTS REQUIRED:

(1) CIRCUIT DIAGRAM:

Fig. 1.1: NOT, OR, AND & XOR GATE

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

(2) CIRCUIT DIAGRAM:

TYPICAL TRUTH TABLE 1:

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

(1) CIRCUIT DIAGRAM: HALF ADDER

Fig. 2.1: Half Adder

TRUTH TABLE 2.1:

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

(2) CIRCUIT DIAGRAM: HALF SUBTRACTOR

Fig. 2.2: HALF SUBTRACTOR

(3) CIRCUIT DIAGRAM: FULL ADDER

Fig. 2.3: FULL ADDER

TRUTH TABLE 2.3:

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

(4) CIRCUIT DIAGRAM: 2 TO 1 MULTIPLEXER

Fig. 2.4: MULTIPLEXER

(5) CIRCUIT DIAGRAM: 1 TO 2 DEMULTIPLEXER

Fig. 2.5: DEMULTIPLEXER

B. Tech. Eng. Physics

APPARATUS /COMPONENTS REQUIRED:

Analyze the circuit and make the truth table.

Fig.3.1: Basic latch using NAND gate

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

PART B: J-K FLIP FLOP:

Assemble the circuit as shown in Fig 3.2.

Fig 3.2: J-K flip flop

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

PART C: DESIGN AN ASYNCHRONOUS COUNTER: RIPPLE DOWN COUNTER

Assemble the circuit as shown below in Fig. 3.3.

Fig 3.3: RIPPLE DOWN COUNTER

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

PART D: DESIGN A 4 BIT SERIAL IN PARALLEL OUT SHIFT REGISTER

Fig. 3.4: SERIAL IN PARALLEL OUT SHIFT REGISTER

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

Fig. 4.1: MAGNITUDE COMPARATOR

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics

TRUTH TABLE 4.1:

PART B: DESIGN AND IMPLEMENTATION OF ENCODER

Electronics Lab II (PH311), 2015

B. Tech. Eng. Physics