SoCLab
Lab 3 : Building a VGA display controller
Purpose
In the previous labs, we familiarized ourselves with the Xilinx ISE environment. The Project
Navigator has been used as the overall interface to Xilinx Design tools. To familiarize the
usage, simple combinatorial and sequential circuits have been designed.
In this lab, already more complex systems are addressed. A VGA display controller will be
designed and experimented.
Requirements
To complete this Lab, the following software is required:
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Windows PC
Digilent Pegasus-2
VGA display
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Computer Displays
For the preparation of this laboratory, you should consult the section on the introduction of
VGA signals in the Digilent reference manuals.
Computer displays have traditionally been realized by Cathode Ray Tubes (CRTs). CRTs (see
fig. 3.1.) have been used for years in television sets. An electron beam is emitted from the
electron guns. In color displays there are three independent guns; one for each of the three
primary colors: red, green and blue. The electron beam is deflected by the variable
magnetic fields of the deflection coils. These coils generate a sawtooth shaped waveform.
The horizontal coil generates the writing of lines from the left to the right. The vertical coil
generates the deflection of line per line from the top of the screen to the bottom, to form
frames.
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front
porch
movement
of a
number
of lines
to form
a
vertical
fram
visible
part
of a
frame
back
porch
front
porch
back
porch
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Ts
Tdisp
Tbp Tpw
Tfp
"back
porch"
Time reference
"front
porch"
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Fig. 3.4. relationship of display of a horizontal line and the horizontal synchronization signal.
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Symbol
Name
Time duration
Number of
50Mhz Clock
periods
50MHz Clock
periods from
Time reference
Tdisp
Display Time
16s
800
799
Tfp
Front Porch
320ns
16
815
Tpw
Pulse Width
2.4s
120
935
Tbp
Back Porch
2.08s
104
1039
Ts
20.8s
1040
1039
Table 3.1. Horizontal synchronization signal characteristics for 800 x 600 video generation,
using a 50MHz clock.
The timing characteristics for the 800 x 600 vsync signal are given in table 3.2. The 800 x 600
video signal uses a frame time Ts of 13.853ms. This corresponds to a frame rate of 72Hz.
Number of lines
Symbol
Name
Time duration
Tdisp
Display Time
12.48ms
600
599
Tfp
Front Porch
740s
37
636
Tpw
Pulse Width
120s
642
Tbp
Back Porch
460s
23
665
Ts
13.853ms
666
665
Table 3.2. Vertical synchronization signal characteristics for 800 x 600 video generation, using
a 50MHz clock.
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Description
Pegasus2
D2SB-DIO4
(in C1-C2)
D2FT-DIO5
(in C1-C2)
Spartan-3
red
vga red
P33
P201
A3
R12
green
vga green
P31
P202
C2
T12
blue
vga blue
P30
P203
B3
R11
hsync
hsync
P29
P199
A4
R9
vsync
vsync
P27
P200
C4
T10
The basic connection on the Digilent boards allow for 1 bit per primary color (red, green and
blue). This leads to 23 =8 combinations. In the assumption that all resistors are installed on the
NCTUIO1 boards, 8 bits can be used per primary color. This corresponds to 23 *8 = 16,777,216
different colors.
The Interface to the VGA screen is done via a 15-SubD connector as shown in figure 3.4.a.
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A word of caution!
Use of an intelligent computer switch cable
To do these experiments we will need to connect a VGA screen to the VGA 9-SubD
connector on our experimentation boards. During the debugging phase of the VGA
controller it is often desired to be able to connect a VGA screen to the FPGA board. As the
VGA display for the computer is normally used for this, this would mean a frequent plugging
and unplugging of the VGA cable in and out of the computer.
We will use a computer KVM1-switch cable supplied in the Lab. This is an intelligent cable
allowing to hook up two computers to a single display, keyboard and mouse. We will
connect our computer and our Digilent boards in this way. Assume that the computer is
connected to one port and the FPGA board to the other port. By typing <ScrLk><ScrLk>
one can switch from the computer to the FPGA board and backwards.
Be careful when experimenting with VGA signals on CRTs!
The VGA signals have originally been designed to be used with Cathode Ray Tubes (CRTs)
such as used in traditional television sets. The signals are directly used to deflect the electron
beam on the screen. When the synchronization signals that are generated are too high for
the underlying electronics, they can damage (older) CRTs, as too high voltages are
generated in the deflection coils with inappropriate high frequencies.
Such a warning holds when you are experimenting with FPGAs connected to old CRTs. It
also holds when you are developing new graphics software drivers for specific
programmable graphics display cards (e.g. for Linux), or when you are using wrong
configurations with too high frequencies in MS-Windows.
Modern LCD computer displays, still use the VGA signals that have originally been designed
for CRTs. As there are no deflection coils in LCD screens, the same problems of possible
damage do not occur here.
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Design a 800 x 600 vga_controller using the on-board 50MHz clock to generate the
horizontal- and vertical control signals: hsync and vsync respectively. In a 72Hz frame rate
800 x 600 display the pixel clock frequency is 50MHz. This is the same as the frequency of the
clock generator on the main FPGA board. In this controller also generate two counters
indicating the pixel_row and pixel_col. These counter values can afterwards be used for
generating specific on-screen information such as text and graphics. This coincidence is
because of the careful choice of the reference time with respect to the horizontal and
vertical synchronization signals. The reference times are chosen such that the counters start
at 0 with the 0-th pixel in a row or a column.
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hsync, vsync);
input clock;
input reset;
// reset signal
endmodule
From the timing signals of table 3.3. and table 3.4. the timing diagram for the hsync signal is
given in fig. 3.5.
Ts
Horizontal
Clock Period Count
Tdisp
Tbp Tpw
Tfp
800
16 120
104
0
Reference Time
7
9
9
8
1
5
9
3
5
1
0
3
9
Fig. 3.5. Timing diagram for the hsync signal for a 800 x 600 display.
In the vga_controller module, the hsync signal can be generated based on the
pixel_col counter that increments with every clock period. When pixel_col reaches
the end of the horizontal synchronization signal clock cycle (at count 1039) reset the counter
back to 0 for the next clock cycle. In this way, we can generate the 1040 clock cycles for
one hsync signal period. As can be seen from fig. 3.5. the hsync signal can be generated
based on the pixel_col counter values by some combinatorial logic.
At every hsync pulse also generate a single clock cycle pulse called line_start_pulse
that can be used to increment the pixel_row counter that is needed for the generation of
the vertical synchronization signal. Take care that for the whole hsync period (consisting of
1040 clock cycles) you only generate a line_start_pulse that is only valid during ONE
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Ts
Tdisp
Tbp Tpw
600
0
Vertical
Line Count
Reference Time
37
5
9
9
23
6
6
3
6
Tfp
6
4
2
6
6
5
Fig. 3.6. Timing diagram for the vsync signal for a 800 x 600 display.
The vertical synchronization signal vsync can be generated in a similar way as the horizontal
synchronization signal hsync. Use the line_start_pulse to have the row_counter being
incremented. At row_counter equal to 665 reset the row_counter to 0. Derive the vsync
signal in the same way as done before for the hsync.
= switch[1];
green = switch[2];
blue
= switch[3];
= 0;
green = 0;
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blue
= 0;
end
With this code, several color combinations can be tested by means of the 8 combinations of
three switches.
The .ucf Design Configuration files can be downloaded from the website (both for D2SB and
D2FT).
red
= pixel_row[6];
green = pixel_row[7];
blue
= pixel_row[8];
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(2)
(3)
(1)
VGA screen
Fig. 3.7. Bouncing Ball experiment.
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A character generator.
In many applications, characters are displayed on a screen. Characters can be represented
as a two dimensional array of pixels. Fig. 3.8 illustrates how the @ character can be
composed in a 16 x 16 character matrix.
Several characters of a specific character set can be represented in an array. The SoCLab
predesigned fontrom module consists of a 128 character array. For the characters from 32
till 126, the ASCII encoding is being used. For the remaining encodings other characters have
been selected. An overview of the 128 characters represented in the SoCLab fontrom
module is given in Appendix 3.b.
The fontrom Read Only Memory (ROM) makes use a Block RAM modules as available in the
Xilinx FPGAs.
Fig. 3.8 16 x 16 bit Character bitmap for the @ sign. (ASCII code 32)
The fontrom is a Xilinx ROM module with a 15 bits address addr[14:0] and a 1 bit output
dout . The 15 address bits is composed of the following parts:
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addr[14:8]
addr[7:4]
addr[3:0]
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endmodule
When this font_rom instantiation is added to a Verilog description, the Project navigator will
indicate that the module is unknown. This is illustrated in fig. 3. 10.
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Fig 3.10. Module font_rom is instantiated in vgasystem_0.v but not yet defined.
The fontrom character ROM is an application of a predefined module that can be used as a
building block in other designs. In actual SoC designs predefined building blocks are often
used and re-used, as this allows to shorten the design cycle. Several companies are currently
commercializing a number of such reusable building blocks. In this case they are also
referred to as: IP blocks (Intellectual Property blocks).
Xilinx includes several libraries of predefined blocks as well. In later labs, the use of Xilinx IP
blocks as available in the Core Generator module will be introduced.
In this experiment, the font_rom ROM module is used. The files describing the font_rom
module, as available in the compressed fontrom.zip file located in the lab3 directory need
to be copied to the project directory at hand.
The fontrom module can than be added to the design files by right clicking on the Verilog
file name using the fontrom module in the Sources for Project window pane of the Project
Navigator. Hereafter select Add Source . In the following file selection box select the
font_rom.xco Xilinx core definition file. (This file is part of the contents of the fontrom.zip file.
Hereafter the icon near font_rom in the Sources for Project window pane of the Project
Navigator changes to the icon for Core Generator.
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characters
addressed by
pixel_row[9:4]
VGA Screen
Fig 3.12 Addressing of characters on the VGA screen by using the pixel_row and
pixel_col counters.
A completed design using the character generator can be found in the vgasystem1.zip
archive of the associated lab files area for Lab3. In that setup all characters are
generated on the screen. The color the characters is defined by switch[1:3] and the
background color is defined by switch[4:6].
The overall vgasystem1.v Verilog description is given below:
module vgasystem_1(red,green,blue,hsync,vsync,clock,reset,switch);
output red;
output green;
output blue;
output hsync;
output vsync;
input clock;
input reset;
input switch;
wire [6:1] switch;
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= switch[1];
green = switch[2];
blue
= switch[3];
end
else begin
red
= 0;
green = 0;
blue
= 0;
end
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endmodule
Experiment with the switches to set the foreground and background colors.
Further applications.
Based on the vga_controller module several graphics applications can be built. Examples
are:
-
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The current applications directly generate the characters from the position counters:
pixel_row and pixel_col. In an actual application a video buffer memory will be used
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Make a graphics computer game. An example could be the famous pong first
computer game.
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Symbol
Name
Time duration
Number of
50Mhz Clock
periods
Tdisp
Display Time
25.6s
1280
1279
Tfp
Front Porch
640ns
32
1311
Tpw
Pulse Width
3.84s
192
1503
Tbp
Back Porch
1.92s
96
1599
Ts
32s
1600
1599
50MHz Clock
periods from
Time reference
Table 1. Horizontal synchronization signal characteristics for 640 x 480 video generation, using
a 50MHz clock.
The timing characteristics for the 640 x 480 vsync signal are given in table 3.2. The 640 x 480
video signal uses a 60 Hz frame rate. This means that every 1/60 sec = 16.666ms a new frame
is being displayed.
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Number of lines
Symbol
Name
Time duration
Tdisp
Display Time
15.36ms
480
479
Tfp
Front Porch
320s
10
489
Tpw
Pulse Width
64s
491
Tbp
Back Porch
928s
29
520
Ts
16.66ms
521
520
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&
<
>
LSB
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