Vol. 35, No.

10

Journal of Semiconductors

October 2014

A 2.52-mW continuous-time modulator with 72 dB dynamic range for FM radio

Chen Mingyi() , Zhou Liguo(), Bian Chenghao(), Yan Jun(),
and Shi Yin()
Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

Abstract: A continuous-time modulator with a third-order loop filter and a 3-bit quantizer is realized. The
modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integrator,
an op-amp with novel GBW extension structure, improving the linearity of the loop filter, is adopted. The prototype
chip is designed in a 130 nm CMOS technology, targeting FM radio applications. The experimental results show
that the prototype modulator achieves a 72 dB dynamic range and a 70.7 dB signal to noise and distortion ratio over
a 500 kHz bandwidth with a 26 MHz clock, consuming 2.52 mW power from a 1.2 V supply.
Key words: continuous-time sigmadelta modulator; FM radio; oversampling A/D converters
DOI: 10.1088/1674-4926/35/10/105004
EEACC: 2220

1. Introduction
It may be surprising that today an almost ancient standard
such as FM is still featured in one of the most used consumer
products, the in-car radio, which is driving research on innovative and state-of-the-art A/D converters1 4 . Without a doubt,
in-car FM radio can be considered a true high-end system due
to the vast dynamic range differences between FM channels.
The full antenna input dynamic range (for FM) is in the order
of 140 dB, exceeding the requirements of, for example, super
audio CD. However, there is no receiver on the market today
that handles that dynamic range without desensitization or using external high-Q filters. Hence, any increase in the dynamic
range of the A/D converter results in a higher quality radio with
better sensitivity and a lower cost system, which is the aim of
every car radio set maker.
Figure 1 presents the conventional direct conversion radio architecture in a modern FM radio receiver. An RF LNA,
which is controlled by an automatic gain control loop (AGC),
processes the received FM signal band (76108 MHz). Then,
a quadrature mixer down-converts the RF signal to baseband.
The mixer pair is controlled by quadrature local oscillator (LO)
signals that have 90 degrees phase difference. After the downconversion, the base band signal is adjusted by a programmable
gain amplifier (PGA) and it is then digitized by a modulator. The modulator is followed by digital comb filters, which
perform most of the required channel filtering prior to the DSP.
The anti-alias filtering and A/D conversion functions can be
combined by using a continuous-time (CT) modulator.
This is helpful to reduce the system cost. In our system, each
modulator has an input sample rate of 26 MHz, which is
the clock rate of the whole system, and should achieve at least
65 dB of dynamic range over the FM bandwidth of 200 kHz.
In the future, this modulator will be shared by a Bluetooth receiver with a similar architecture, thus the bandwidth should
be extended to 500 kHz to accommodate Bluetooth signals.
As mentioned above, a modulator is one of the core
blocks in the tuner and it will have an important impact on the

performance of the whole system. Nowadays, over-sampling

modulators are widely used in application-specific ICs
due to their high dynamic range and low power consumption.
Thanks to the advance of CMOS processes and the CT analog filter technique, the popularity of CT modulator has
recently been growing. Due to the inherent anti-alias function
and non-sampling loop filter, it is feasible at the same time to
achieve a resolution larger than 12 bits with a signal bandwidth
of up to MHz, leading to more power and area-efficient ADCs.
Many discussions about the possibility of building a high speed
and high resolution CT modulator for those applications
are presented in Refs. [59].
This paper firstly describes the system architecture, it then
gives the circuit design and implementation. Our experiment
results are presented in Section 4. Finally, our conclusions are
drawn in Section 5.

2. System architecture
2.1. CT modulator architecture
The loop filter design of a CT A/D modulator is nontrivial in that it has a strong dependence on the pulse of the feedback DAC. Because discrete time (DT) modulator loop filters
can be easily designed, the most common method to design a
CT modulator loop filter is to first find the equivalent DT modulator loop filter and then transform it to continuous-time using

Corresponding author. Email: tjucmy@126.com

Received 10 February 2014, revised manuscript received 8 May 2014

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Fig. 1. Traditional direct conversion receiver architecture.

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Fig. 2. CT modulator architecture.

Table 1. Coefficient value of the modulator.

Parameter
Value
K1
1.74
K2
0.35
K3
1
Kff
0.82
Kfb
0.025
K1fb
1
K2fb
3

impulse invariant transformation8 .

The dynamic range (DR) of an oversampling A/D
modulator is a function of the oversampling ratio (OSR), loop
order (L), and the number of quantizer bits (N ), as expressed
by:


ps 3 2L C 1
DR D
.2N 1/2 OSR2LC1 :
(1)
pN 2
 2L
Although Equation (1) is valid only if the noise transfer
function is .1 z 1 /L , which is not true for most wideband,
high resolution A/D modulators, it does give qualitative guidance on selecting OSR, L, and N in the system level design.
Based on extensive simulation in MATLAB, a third-order, 3 bit
(with 8 output levels) topology is chosen with 26  OSR. By
taking only the quantization noise into account, the ideal peak
dynamic range is about 96 dB.
The proposed CT modulator architecture is shown in
Fig. 2. The modulator comprises a 3-bit internal quantizer, operating at 26 MHz with an oversampling ratio of 26, a thirdorder loop filter, and two feedback DACs. Dynamic element
matching (DEM) is used to suppress the DAC mismatch to
the required level. In order to save power and maintain a good
alias filter characteristic, a combination of feed-forward and
feedback stabilized loop filters are implemented. The feedback
path Kfb shifts two zeros (with conjugate frequencies in the s
plane) out of DC in the noise transfer function (NTF) to lower
the overall quantization noise within the signal bandwidth, and
hence improves the signal to noise ratio (SNR)9 . The transfer
function of the system can be expressed by Eq. (2):

Fig. 3. Noise transfer function (NTF) and signal transfer function

(STF) plot.


H.s/ D Kfb2 Ks .sT /2 C Kfb1 K1 Ks Kff sT


C Kfb1 K1 K2 Ks .sT /2 C Kfb K2 Ks sT

: (2)

The coefficient of the CT loop filter can be derived by

MATLAB deltasigma toolbox. First, the optimized NTF can
be obtained by inputting the system order, over-sampling ratio, and maximum out-of-band gain. Then, the discrete-time
transfer function, as shown by Eq. (3), can be obtained from
NTF. Next, the CT transfer function can be derived using the
d2cm (discrete-to-continuous) function, as shown by Eq. (4).
Finally, by comparing Eq. (2) and Eq. (4), the coefficient can
be obtained by solving the following equations:
2:355z 2 2:689z C 0:9436
;
z 3 2:991z 2 C 2:991z 1

(3)

1:5497.sT /2 C 1:4121sT C 0:61

:
.sT /3 C 0:0088
sT

(4)

H.Z/ D

H.S / D

The coefficient value of the modulator is given in Table 1.

The NTF and STF of the modulator are shown in Fig. 3. A
maximum NTF gain of 12 dB is chosen. The top level of the
implementation is shown in Fig. 4.

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Fig. 4. The modulators top Level of the implementation.

Fig. 5. SNDR for 6 dBFS input versus normalized time constant.

2.2. Loop filter coefficient variations

Large time constant variations are one of the major disadvantages of CT modulators compared to DT modulators and,
thus, a careful system level examination is needed. The result
of the signal to noise and distortion ratio (SNDR) calculation
is shown in Fig. 5, assuming that the time constants in the
three integrators vary by the same percentage. This is actually
a worst case assumption because if each time constant varies
independently, then the effects are averaged out, which reduces
the overall degradation.
As shown in Fig. 5, when the time constants, that is, the
products of resistors and capacitors are as small as 85% of their
nominal values, the SNDR decreases and the modulator becomes unstable due to excessive loop gain. On the other hand,
if the time constants are larger than 115% of their nominal values, the SNDR reaches its peak and varies a little. Further increasing of the time constant beyond that value will have little
impact on the SNDR and will only increase the chip area. Thus,
if the time constants are centered at 115% of the nominal value,
then the SNDR can always be larger than 70 dB with 10%
time constant variation. Since it is not uncommon for the RC
time constants to vary by 20%, an on-chip tuning method is
still needed (see Section 3.5).

Fig. 6. Simulation results of SNDR versus clock jitter and quantizer

delay. (a) SNDR for 6 dBFS input versus clock jitter. (b) SNDR for
6 dBFS input versus quantizer delay.

2.3. Clock jitter and excess loop delay

There are two main problems of the CT modulator,
the first is clock jitter and the second is excess loop delay,
which is caused by the quantizer delay. Both of these problems can cause SNDR degradation and even cause instability
of the modulator. In the architecture design stage, these effects
should be found and evaluated.
Figure 6 shows the simulation results of the modulators
SNDR versus the clock jitter (Fig. 6(a)) and the quantizer delay (Fig. 6(b)) with 6 dBFS input. The plot is given by MATLABs sigmadelta toolbox. In the toolbox, the SNDR can be
calculated while sweeping the clock jitter and the quantizer delay. As can be seen from the figure, in order to achieve SNDR

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over 70 dB, the clock jitter should be kept below 15 ps. The
typical jitter performance of the 26 MHz crystal oscillator is
less than 10 ps. This leaves enough margin for the SNDR to
be larger than 70 dB. In addition, the quantizer delay should
be lower than 10.6 ns for stable operation of the modulator.
The typical delay of the quantizer that is comprised of a preamplifier and a high speed latch is only 1 ns (see Section 3.2).
This also confirms the SNDR to be larger than 70 dB.
2.4. Noise consideration
The device noise at the modulator front-end is not attenuated and, thus, it is a limiting factor in the total input referred
noise of the modulator. There are three sources for the noise of
the front-end:
(1) Noise of the two input resistors;
(2) Noise of the op-amp;
(3) Noise of the current steering DAC1 feedback to the
virtual grounds of the op-amp.
The following integrator contributes little noise due to the
high gain of the preceding stage. In our design, the dominant
noise source is the noise from two input resistors. The choice
of the input resistor value is a trade off process between chip
area and noise. For a given time constant, a larger resistor has
a smaller capacitor area but larger noise. The resistor value
should be fixed during the architecture design stage. The total in-band noise power of the two input resistor is expressed
by:
VR2in D 8kTRin f;
(5)
where k represents the Boltzmann constant, T represents absolute temperature, and f is the signal bandwidth, which equals
500 kHz. In our design, the value of the input resistor is chosen
to be 6 k, generating a thermal noise power that is 98.6 dB
lower than the full scale input signal. The input resistor of the
following integration stage could be scaled up to minimize the
capacitor area. The simulation shows that the resistors of the
following stage can be scaled up to less than 3 compared to
the former stage in order to make little in-band noise contribution. Thus, in our design, the R2 and R3 are chosen to be 16 k
and 36 k, respectively.

3. Circuit design and implementation

3.1. Operational amplifier
Figure 7(a) shows the schematic of the op-amps used in the
proposed modulator10 , which is a two-stage op-amp. The 1st
stage is a PMOS input differential pair with cascade NMOS
load, and the 2nd stage is an NMOS common source stage.
The common-mode (CM) control section is composed of the
common-mode interference rejection (CMIR), common-mode
feed-forward (CMFF) and common-mode feedback (CMFB)
circuits.
A novel gain-bandwidth (GBW) extension structure is
adopted, which splits the Miller compensation capacitor CC
into CC1 , CC2 in series, each with two times the CC value. RZ
is added to cancel out the right half plane (RHP) zero and R1
acts as an anti-pole splitting resistor at low frequencies. R2
operates on common-mode signals to cancel out the anti-pole
splitting effect for the common-mode signal.

The op-amps differential mode small signal equivalent

circuit is shown in Fig. 7(b). The gmb generator and gatedrain capacitance Cgd are neglected for simplicity. The output impedance of the 1st and 2nd stage are supposed to be
Ro1 and Ro2 , respectively. At low frequencies, R1 has a lower
impedance than CC1 , so the feedback current signal flows
through CC2 , R1 to ac ground and the feedback path is now cut
off, presenting the effect of anti-pole splitting. In this case,
the op-amp behaves like an uncompensated two stage amplifier. At high frequencies, CC1 has a lower impedance than R1
and steers the feedback current as in the Miller compensated
counterpart, making its magnitude response coincide with the
Miller compensation response. As shown in Fig. 8, the two frequency response curves of a conventional Miller op-amp and
the op-amp with extended GBW intersect at the unit gain bandwidth (UGB), which is 286.9 MHz in this design. The proposed
GBW extension scheme can increase the op-amp gain by 3 dB
at the integrators corner frequency (26 MHz) and by 6 dB at
half of the corner frequency (13 MHz). Thanks to this open
loop gain improvement, both in-band and out-of-band linearity of the loop filter can be enhanced. By using the GBW extension technique, the op-amp phase margin decreases by 9 degrees compared to its Miller compensated counterpart, with the
simulation results larger than 70 degrees over the process, voltage and temperature (PVT) variations.
By adding an auxiliary input CM transconductor that is
made up of MP9a, MP9b and current mirror Mn3, Mn4, Opamp CMRR is improved by 16 dB. High CM rejection not
only helps to improve the filters CMRR performance, but also
makes the CM loops more stable. Moreover, to reject the large
signal CM interference, two PMOS transistors MP8a, MP8b
are added to the op-amps input stage. MP8a and MP8b are
turned off when there is no CM interference applied to the input terminals. When the op-amp inputs catch a large CM step,
MP8a and MP8b function as switches. Without these two devices, the large CM step would drastically pull the op-amp output CM voltage away from its nominal CM value to the power
rail, which may continue to saturate the following op-amps and
finally put the filter into latch or CM oscillation status. When
MP8a and MP8b are added, the large CM step would turn on
MP8a and MP8b, conduct I2 to the output to balance the upper and lower bias current, and maintain the output CM voltage
around its nominal CM value.
In conclusion, consuming only 350 A current, the opamp achieves UGB of 286.9 MHz with a dc gain of 50 dB and
phase margin of 70 degree, which suffices for the requirements
of this modulator.
3.2. Three-bit flash ADC
The quantizer in the modulator (Fig. 9) consists of a reference ladder and a 3-bit flash ADC with a thermometer-coded
output. The differential reference voltages for the comparator
inputs are generated by copying an internally available reference voltage onto a unit resistor string. The eight comparators of the internal flash ADC consist of a double differential input stage as pre-amp and a regenerative latch at the output, as shown in Fig. 10. In the operation mode, the current
from the input pairs generates a voltage difference at the output of the pre-amp. Immediately afterwards, the output latch

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Fig. 7. (a) Op-amp schematic and (b) its differential mode small signal equivalent circuit.

Fig. 8. Frequency response of two op-amps.

is started. This latch has a very small regenerative time constant and amplifies the voltage difference to full logic levels.
Simulation shows that the quantizer delay is only 1ns, which is
much smaller than the upper limit of the value that will cause
instability of the modulator (see Section 2.3).
3.3. Feedback DACs
Since the loop filter implements one feed-forward path,

only two DACs would be necessary to realize the differentiated return-zero (RZ) feedback. DAC1 realizes an input to the
loop filter and, hence, has the highest requirements on linearity and noise performance, which requires a large device size
to get the necessary matching and flicker noise performance.
DAC2 realizes the second feedback. As any non-idealities of
DAC2 are suppressed by the gain of the first two integrators,
the requirements on noise and linearity can be relaxed. For both

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saturation region, which further increases the output resistance,
and reduces both glitch energy and clock feedthrough. This is
achieved by driving them with a reduced voltage swing, which
comes from low swing buffers. The edges of the driving dual
rail signals have a high crossover point to ensure that one of the
switches is always on, which avoids charging and discharging
of the tail node. The biasing circuit uses a resistor that matches
to the modulator input resistors to derive the DAC current from
a reference voltage. Thereby, a fixed input to output gain is ensured. The schematics of the DAC and low swing buffer are
shown in Fig. 11. The DAC1s current value will have impact
on the input noise and the signal-to-noise ratio (SNR) of the
modulator. The input noise power is proportional of Idac , while
2
the full scale signal power is proportional of Idac
. Thus, a larger
DAC current increases the SNR. In this design, we chose a 60
A current for the DAC1 while the SNR due to the DAC noise
is calculated to be 86.1 dB, leaving enough margin for the design. The transient simulation results of flash ADC and feedback DAC are shown in Fig. 12.

Fig. 9. Quantizer in the modulator.

3.4. Dynamic element matching

Figure 13 takes data-weighted-averaging (DWA), a widely
used first order DEM algorithm, and a 3-bit DAC, as an example to illustrate the principle of the DEM. The selection of the
DAC elements is based on the input data and currently used
elements. We assume that the input sequence is 2, 5, 4, 7, 5, 2,



in Fig. 12, the gray grids represent the currently used DAC
elements while the white grids indicate those that are not used.
The elements are selected in a circular way, such that every
element has the same probability of use. Hence, the mismatch
error can be quickly averaged out and the DAC mismatch error is effectively first-order shaped. Figure 14 gives a block
diagram of the DWA block. The adder adds the kth and the
(kC1)th binary code from the ADC. If the result is larger than
8, then the MOD8 operation is implemented. The result is decoded to one hot key by the decoder, which then transfers to
the barrel shifter. The barrel shifter outputs the final code to the
DAC. In this manner, DWA is realized.
3.5. Time constant tuning

Fig. 10. Schematic of (a) the pre-amp and (b) the latch in the comparator.

DACs, the gate overdrive voltage is chosen to be relatively high

to get good device matching and thermal noise performance.
Both DACs use source degeneration resistors to increase their
output resistance. The switch transistors always operate in the

In this design, integration capacitors in all integrators are

realized by an adjustable capacitor array, as shown in Fig. 15.
The capacitors in the arrays are binary-sized, except for the
always-in-use capacitors. This sizing method provides constant tuning steps with the least number of capacitors. The 3 bit
digital control codes are fed externally so that we can choose
which capacitors to use.
The value of and are chosen such that they equal the nominal value of the integration capacitor. The ratio between C
and C0 is chosen to be 0.1; thus, the tuning range and tuning
accuracy are 1.7 and 7.7%, respectively, which suffices for the
requirements for this modulator according to the simulation results shown in Fig. 5.

4. Experimental results
The proposed modulator is fabricated in a TSMC 130 nm
CMOS process and it occupies an area of 0.66 mm2 . Figure 16
gives a die photograph of this modulator.

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Fig. 11. Schematic of (a) the DAC and (b) the low swing buffer.

Fig. 12. Transient simulation results of flash ADC and feedback DAC.

dB. The Harmonic distortion test result is shown in Fig. 19.

The 2nd and 3rd harmonic distortion value is 85 dB and
72 dB, respectively. Higher order harmonic distortion is below the noise floor. The two-tone intermodulation test result is
shown in Fig. 20, with two 6 dB input signals at 310 kHz and
330 kHz, respectively. The 3rd-order intermodulation distortion (IM3) is 64 dB lower than the input signals.

5. Conclusion
Fig. 13. Illustration of DWA.

An external transformer converts the single-ended analog

signal to a balanced differential signal input. The output of the
modulator is windowed by a Hanning window and the Fourier
transformation is applied with 65536 data points. The measured output spectra for the 75.8 kHz, 4 dBFS input signal are
shown in Fig. 17. The measured spurious-free dynamic range
(SFDR) is 75 dB and the peak SNR is 72.3 dB, while consuming 2.1 mA current from a 1.2-V supply.
Figure 18 shows the SNDR as a function of the input signal magnitude. The peak SNDR is 70.7 dB and the DR is 72

In this paper, a continuous-time modulator that is fabricated in a 130 nm CMOS technology is proposed for the application FM/Bluetooth tuner. The proposed modulator consumes 2.1 mA current from a 1.2 V supply and occupies an
area of 0.66 mm2 . Table 2 gives performance summary of this
work and a comparison with other related works11 14 .

Acknowledgments
The author would like to thank Yang Zhengxiu, Liu Cong,
Yin Jinlin and Li Canyang for their help in layout and testing.

References
[1] Breems L J, van der Zwan E J, Dijkmans E C, et al. A 1.8 mW

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Parameter
Supply voltage (V)
Technology
Fs (MHz)
BW (MHz)
SNDR (dB)
DR (dB)
Power (mW)
Chip area (mm2 /
FoM* (pJ/conv.)

Chen Mingyi et al.

Table 2. Performance comparison with other related works.
Ref. [11]
Ref. [12]
Ref. [13]
Ref. [14]
1.2
1
1.5
2.7
130 nm CMOS 130 nm CMOS 250 nm CMOS 350 nm BiCMOS
480
5.12
150
32
20
0.02
2
0.5
64.1
81.4
63.4
77
66
85
68
80
18
0.06
2.7
11.9
0.76
0.12
0.42
1.0
0.33
0.11
0.56
2.06

*FoM(Figure of Merit) D Power/(2  BW  2.SNDR

**It includes two channels (I/Q path).

1:73/=6:02 /.

This work
1.2
130 nm CMOS
26
0.5
70.7
72
2.52
0.66
0.89

Smaller FoM is better.

Fig. 14. Block diagram of DWA.

Fig. 17. Measured output spectrum of the modulator with 75.8 kHz
and 4 dBFS input signal.

Fig. 15. Tunable capacitor array.

Fig. 18. Measured SNDR versus input signal magnitude.

Fig. 16. Die photograph of the modulator.

CMOS sigma delta modulator with integrated mixer for A/D conversion of IF signals. IEEE J Solid-State Circuits, 2000, 35(4):
468
[2] Van der Zwan E J, Philips K, Bastiaansen C A A. A 10.7-MHz
IF-to-baseband sigma delta A/D conversion system for AM/FM
radio receivers. IEEE J Solid-State Circuits, 2000, 35(12): 1810

[3] Silva P, Breems L J, Makinwa K, et al. A 118 dB DR CT IFto-baseband modulator for AM/FM/IBOC radio receivers.
IEEE ISSCC Dig Tech Papers, 2006: 66
[4] Breems L J, Rutten R, van Veldhoven R, et al. A 56 mW CT
quadrature cascaded sigma delta modulator with 77 dB DR in a
near zero-IF 20 MHz band. IEEE ISSCC Dig Tech Papers, 2007:
238

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4 dBFS input

Fig. 20. Two-tone intermodulation test (input frequencies: 310 kHz

and 330 kHz).

[5] Paton S, Giandomenico A D, Hernandez L, et al. A 70-mW 300MHz CMOS continuous-time sigma delta ADC with 15-MHz
bandwidth and 11 bits of resolution. IEEE J Solid-State Circuits,
2004, 39(7): 1056
[6] Mitteregger G, Ebner C, Mechnig S, et al. A 20-mW 640-MHz
CMOS continuous-time sigmadelta ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE
J Solid-State Circuits, 2006, 41(12): 2641
[7] Schoofs R, Steyaert M S J, Sanse W M C. A design-optimized
continuous-time deltasigma ADC for WLAN applications.
IEEE Trans Circuits Syst I, 2007, 54(1): 209
[8] Li Z M, Fiez T S. A 14 bit continuous-time deltasigma A/D
modulator with 2.5 MHz signal bandwidth. IEEE J Solid-State
Circuits, 2007, 42(9): 1873
[9] Yan S L, Sanchez-Sinencio E. A continuous-time modulator
with 88-dB dynamic range and 1.1-MHz signal bandwidth. IEEE

J Solid-State Circuits, 2004, 39(1): 75

[10] Gong Zhen, Chen Bei, Hu Xueqing, et al. A low power 8th order
elliptic low-pass filter for a CMMB tuner. Journal of Semiconductors, 2011, 32(9): 095002
[11] Li Ran, Li Jing, Yi Ting, et al. A 18-mW, 20-MHz bandwidth, 12bit continuous-time modulator using a power-efficient multistage amplifier. Journal of Semiconductors, 2012, 33(1): 015007
[12] Li Yuanwen, Qi Da, Dong Yifeng, et al. A 1-V 60-W 85-dB dynamic range continuous-time third-order sigmadelta modulator.
Journal of Semiconductors, 2009, 30(12): 125011
[13] Song T Y, Cao Z H, L Yan S. A 2.7-mW 2-MHz continuous-time
modulator with a hybrid activepassive loop filter. IEEE J
Solid-State Circuits, 2008, 43(2): 330
[14] Grilo J, Galton I, Wang K, et al. A 12-mW ADC deltasigma
modulator with 80 dB of dynamic range integrated in a singlechip Bluetooth transceiver. IEEE J Solid-State Circuits, 2002,
37(3): 271

Fig. 19. Harmonic distortion test with 75.8 kHz and

signal.

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