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1.

Which of the following logic families has the highest maximum clock frequency?
A.

S-TTL

B.

AS-TTL

C.

HS-TTL

D.

HCMOS

Answer: Option B
2.
Why is the fan-out of CMOS gates frequency dependent?

A.

Each CMOS input gate has a specific propagation time and this limits the number of different
gates that can be connected to the output of a CMOS gate.

B.

When the frequency reaches the critical value, the gate will only be capable of delivering
70% of the normal output voltage and consequently the output power will be one-half of
normal; this defines the upper operating frequency.

C.

The higher the number of gates attached to the output, the more frequently they will have to
be serviced, thus reducing the frequency at which each will be serviced with an input signal.

D.

The input gates of the FETs are predominantly capacitive, and as the signal frequency
increases the capacitive loading also increases, thereby limiting the number of loads that may
be attached to the output of the driving gate.

Answer: Option D
3.
Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have:
A.

a greater current/voltage capability than an ordinary logic circuit.

B.

greater input current/voltage capability than an ordinary logic circuit.

C.

a smaller output current/voltage capability than an ordinary logic.

D.

greater input and output current/voltage capability than an ordinary logic circuit.

Answer: Option A
4.
Which of the following will not normally be found on a data sheet?

A.

Minimum HIGH level output voltage

B.

Maximum LOW level output voltage

C.

Minimum LOW level output voltage

D.

Maximum HIGH level input current

Answer: Option C
5.
Which of the following logic families has the shortest propagation delay?
A.

S-TTL

B.

AS-TTL

C.

HS-TTL

D.

HCMOS

Answer: Option B
6.
Which of the following summarizes the important features of ECL?

A.

Low noise margin, low output voltage swing, negative voltage operation, fast, and high
power consumption

B.

Good noise immunity, negative logic, high frequency capability, low power dissipation, and
short propagation time

C.

Slow propagation time, high frequency response, low power consumption, and high output
voltage swings

D.

Poor noise immunity, positive supply voltage operation, good low frequency operation, and
low power

Answer: Option A
7.
What must be done to interface TTL to CMOS?
A.

A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.

B.

As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of
the TTL is limited to five CMOS gates.

C.

A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them
from the higher output voltages of the CMOS gates.

D.

A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value
of RP will depend on the number of CMOS gates connected to the node.

Answer: Option D
8.
What causes low-power Schottky TTL to use less power than the 74XX series TTL?
A.

The Schottky-clamped transistor

B.

Nothing. The 74XX series uses less power.

C.

A larger value resistor

D.

Using NAND gates

Answer: Option C
9.
What are the major differences between the 5400 and 7400 series of ICs?
A.

The 5400 series are military grade and require tighter supply voltages and temperatures.

B.

The 5400 series are military grade and allow for a wider range of supply voltages and
temperatures.

C.

The 7400 series are an improvement over the original 5400s.

D.

The 7400 series was originally developed by Texas Instruments. The 5400 series was brought
out by National Semiconductors after TI's patents expired, as a second supply source.

Answer: Option B
10.
Which of the following statements apply to CMOS devices?
A.

The devices should not be inserted into circuits with the power on.

B.

All tools, test equipment, and metal workbenches should be tied to earth ground.

C.

The devices should be stored and shipped in antistatic tubes or conductive foam.

D.

All of the above.

Answer: Option D
11.
What must be done to interface CMOS to TTL?
A.

A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.

B.

As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of
the CMOS is limited to two TTL gates.

C.

A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them
from the higher output voltages of the CMOS gates.

D.

The two series cannot be interfaced without the use of special interface buffers designed for
that purpose, such as the open-collector buffers.

Answer: Option B
12.
What is the static charge that can be stored by your body as you walk across a carpet?
A.

300 volts

B.

3,000 volts

C.

30,000 volts

D.

Over 30,000 volts

Answer: Option D
13.
What type of circuit is shown below, and how is the output ordinarily connected?

A.

It is an open-collector gate and is used to drive loads that cannot be connected directly
to Vcc due to high noise levels.

B.

It represents an active-LOW inverter and is used in negative logic systems.

C.

It is an open-collector gate. An external load must be connected between the output terminal
and an appropriate supply voltage.

D.

Any of the above could be correct, depending on the specific application involved.

Answer: Option C
14.
What type of circuit is represented in the given figure, and which statement best describes its
operation?

A.

It is a tristate inverter. When the ENABLE input is HIGH, the output is effectively an open
circuitit is neither LOW nor HIGH.

B.

It is a programmable inverter. It can be programmed to function as either an active LOW or


an active HIGH inverter.

C.

It is an active LOW buffer, which can be turned on and off by the ENABLE input.

D.

None of the above.

Answer: Option A
15.
Which of the following logic families has the highest noise margin?
A.

TTL

B.

LS TTL

C.

CMOS

D.

HCMOS

Answer: Option D
16.
A "floating" TTL input may be defined as:
A.

unused input that is tied to Vcc through a 1 k

B.

unused input that is tied to used inputs.

C.

unused input that is tied to the ground.

D.

unused input that is not connected.

resistor.

Answer: Option D
17.
Which of the logic families listed below allows the highest operating frequency?
A.

74AS

B.

ECL

C.

HCMOS

D.

54S

Answer: Option B
18.
Refer to the given figure. What type of output arrangement is being used for the output?

A.

Complementary-symmetry

B.

Push-pull

C.

Quasi push-pull

D.

Totem-pole

Answer: Option D
19.
Refer the given figure. Which of the following describes the operation of the circuit?

A.

A LOW input turns Q1 and Q3 on; Q2 and Q4 are off.

B.

A LOW input turns Q1 and Q4 off; Q2 and Q3 are on.

C.

A HIGH input turns Q1, Q2, and Q3 off, and Q4 is on.

D.

A HIGH input turns Q1, Q2, and Q4 on; Q3 is off.

Answer: Option C
20.
What type of logic circuit is shown below and what logic function is being performed?

A.

It is an NMOS AND gate.

B.

It is a CMOS AND gate.

C.

It is a CMOS NOR gate.

D.

It is a PMOS NAND gate.

Answer: Option C
21.
Whenever a totem-pole TTL output goes from LOW to HIGH, a high-amplitude current spike is
drawn from the Vcc supply. How is this effect corrected to a digital circuit?
A.

By connecting a radio-frequency capacitor from Vcc to ground.

B.

By using a switching power supply

C.

By connecting a capacitor from Vout to ground

D.

By connecting a large resistor from Vcc to Vout

Answer: Option A
22.
What type of circuit is shown below and which statement best describes its operation?

A.

It is a two-input CMOS AND gate with open drain.

B.

It is a two-input CMOS buffer with tristate output.

C.

It is a CMOS inverter with tristate output.

D.

It is a hybrid TTL-CMOS inverter with FET totem-pole output.

Answer: Option C
23.
What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed
CMOS)?
A.

B.

10

C.

50

D.

100

Answer: Option B
24.
A logic signal experiences a delay in going through a circuit. The two propagation delay times are
defined as:
A.

tPLH and tPHL.

B.

tDLH and tDHL.

C.

tHPL and tlph.

D.

tLDH and tHDL.

Answer: Option A
25.
What does ECL stand for?

A.

It stands for electron-coupled logic; all of the devices used within the gates are N-type
transistors.

B.

It stands for emitter-coupled logic; all of the inputs are coupled into the device through
the emitters of the input transistors.

C.

It stands for emitter-coupled logic; all of the emitters of the input transistors are
connected together and each transistor functions as an emitter follower.

D.

It stands for energy-coupled logic; the input energy is amplified by the input transistors
and allows the device to deliver higher output currents.

Answer: Option C
26.
What is unique about TTL devices such as the 74S00?

A.

The gate transistors are silicon (S), and the gates therefore have lower values of leakage
current.

B.

The S denotes the fact that a single gate is present in the IC rather than the usual package
of 26 gates.

C.

The S denotes a slow version of the device, which is a consequence of its higher power
rating.

D.

The devices use Schottky transistors and diodes to prevent them from going into
saturation; this results in faster turn on and turn off times, which translates into higher
frequency operation.

Answer: Option D
27.
Refer to the figure given below. What type of device is shown and what input levels are required to
turn the LED off?

A.

The device is an open-collector AND gate and requires both inputs to be HIGH in order to
turn the LED off.

B.

The device is a Schottky AND gate and requires only one low input to turn the LED off.

C.

The device is an open-collector AND gate and requires only one low input to turn the LED
off.

D.

The device is a Schottky open-collector AND gate and requires a low on both inputs to turn
the LED off.

Answer: Option A
28.
Generally, the voltage measured at an unused TTL input would typically be measured between:
A.

1.4 to 1.8 V.

B.

0 to 5 V.

C.

0 to 1.8 V.

D.

0.8 to 5 V.

Answer: Option A
29.
The IEEE/ANSI notation of an internal underlined diamond denotes:
A.

totem-pole outputs.

B.

open-collector outputs.

C.

quadrature amplifiers.

D.

tristate buffers.

Answer: Option B
30.
The bipolar TTL logic family that was developed to increase switching speed by preventing transistor
saturation is:
A.

emitter-coupled logic (ECL).

B.

current-mode logic (CML).

C.

transistor-transistor logic (TTL).

D.

emitter-coupled logic (ECL) and transistor-transistor logic (TTL).

Answer: Option D