Anda di halaman 1dari 582

Ngspice Users Manual

Version 25plus
(Describes actual ngspice source code at git)
Paolo Nenzi, Holger Vogt
October 20, 2013

Locations
The project and download pages of ngspice may be found at
Ngspice home page http://ngspice.sourceforge.net/
Project page at sourceforge http://sourceforge.net/projects/ngspice/
Download page at sourceforge http://sourceforge.net/projects/ngspice/files/
Git source download http://sourceforge.net/scm/?type=cvs&group_id=38962

Status
This manual is a work in progress. Some to-dos are listed in the following. More is surely
needed. You are invited to report bugs, missing items, wrongly described items, bad English
style etc.

To Do
1. Review of chapt. 1.3
2. hfet1,2 model descriptions

How to use this manual


The manual is a work in progress. It may accompany a specific ngspice release, e.g. ngspice24 as manual version 24. If its name contains Version xxplus, it describes the actual code
status, found at the date of issue in the Git Source Code Management (SCM) tool. The manual is
intended to provide a complete description of the ngspice functionality, its features, commands,
or procedures. It is not a book about learning spice usage, but the novice user may find some
hints how to start using ngspice. Chapter 21.1 gives a short introduction how to set up and
simulate a small circuit. Chapter 32 is about compiling and installing ngspice from a tarball or
the actual Git source code, which you may find on the ngspice web pages. If you are running a
specific LINUX distribution, you may check if it provides ngspice as part of the package. Some
are listed here.

Part I
Ngspice User Manual

Contents
I

Ngspice User Manual

Introduction

33

1.1

Simulation Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

1.1.1

Analog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

1.1.2

Digital Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

1.1.3

Mixed-Mode Simulation . . . . . . . . . . . . . . . . . . . . . . . . .

35

1.1.4

Mixed-Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . .

36

Supported Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37

1.2.1

DC Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37

1.2.2

AC Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . .

38

1.2.3

Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38

1.2.4

Pole-Zero Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38

1.2.5

Small-Signal Distortion Analysis . . . . . . . . . . . . . . . . . . . .

39

1.2.6

Sensitivity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

1.2.7

Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40

1.2.8

Periodic Steady State Analysis

. . . . . . . . . . . . . . . . . . . . .

40

1.3

Analysis at Different Temperatures . . . . . . . . . . . . . . . . . . . . . . . .

40

1.4

Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42

1.4.1

Voltage convergence criterion . . . . . . . . . . . . . . . . . . . . . .

42

1.4.2

Current convergence criterion . . . . . . . . . . . . . . . . . . . . . .

43

1.4.3

Convergence failure . . . . . . . . . . . . . . . . . . . . . . . . . . .

43

1.2

Circuit Description

45

2.1

General Structure and Conventions . . . . . . . . . . . . . . . . . . . . . . . .

45

2.1.1

Input file structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45

2.1.2

Circuit elements (device instances)

. . . . . . . . . . . . . . . . . . .

45

2.1.3

Some naming conventions . . . . . . . . . . . . . . . . . . . . . . . .

46

CONTENTS
2.2

Basic lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

2.2.1

.TITLE line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

2.2.2

.END Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

2.2.3

Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

2.2.4

End-of-line comments . . . . . . . . . . . . . . . . . . . . . . . . . .

49

2.3

.MODEL Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

2.4

.SUBCKT Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50

2.4.1

.SUBCKT Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

51

2.4.2

.ENDS Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

52

2.4.3

Subcircuit Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

52

2.5

.GLOBAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

52

2.6

.INCLUDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

52

2.7

.LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

2.8

.PARAM Parametric netlists . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

2.8.1

.param line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

2.8.2

Brace expressions in circuit elements: . . . . . . . . . . . . . . . . . .

54

2.8.3

Subcircuit parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .

54

2.8.4

Symbol scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55

2.8.5

Syntax of expressions . . . . . . . . . . . . . . . . . . . . . . . . . .

55

2.8.6

Reserved words

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58

2.8.7

Alternative syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58

.FUNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58

2.10 .CSPARAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

59

2.11 .TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

59

2.12 .IF Condition-Controlled Netlist . . . . . . . . . . . . . . . . . . . . . . . . .

60

2.13 Parameters, functions, expressions, and command scripts . . . . . . . . . . . .

61

2.13.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61

2.13.2 Nonlinear sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61

2.13.3 Control commands, Command scripts . . . . . . . . . . . . . . . . . .

61

2.9

Circuit Elements and Models

63

3.1

General options and information . . . . . . . . . . . . . . . . . . . . . . . . .

63

3.1.1

Simulating more devices in parallel . . . . . . . . . . . . . . . . . . .

63

3.1.2

Technology scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .

64

3.1.3

Model binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

64

CONTENTS
3.1.4
3.2

7
Multiplier m, initial conditions . . . . . . . . . . . . . . . . . . . . . .

64

Elementary Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65

3.2.1

Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65

3.2.2

Semiconductor Resistors . . . . . . . . . . . . . . . . . . . . . . . . .

66

3.2.3

Semiconductor Resistor Model (R) . . . . . . . . . . . . . . . . . . .

66

3.2.4

Resistors, dependent on expressions (behavioral resistor) . . . . . . . .

68

3.2.5

Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

68

3.2.6

Semiconductor Capacitors . . . . . . . . . . . . . . . . . . . . . . . .

69

3.2.7

Semiconductor Capacitor Model (C) . . . . . . . . . . . . . . . . . . .

69

3.2.8

Capacitors, dependent on expressions (behavioral capacitor) . . . . . .

71

3.2.9

Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72

3.2.10 Inductor model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72

3.2.11 Coupled (Mutual) Inductors . . . . . . . . . . . . . . . . . . . . . . .

73

3.2.12 Inductors, dependent on expressions (behavioral inductor) . . . . . . .

74

3.2.13 Capacitor or inductor with initial conditions

. . . . . . . . . . . . . .

75

3.2.14 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

76

3.2.15 Switch Model (SW/CSW) . . . . . . . . . . . . . . . . . . . . . . . .

77

Voltage and Current Sources

79

4.1

Independent Sources for Voltage or Current . . . . . . . . . . . . . . . . . . .

79

4.1.1

Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

4.1.2

Sinusoidal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

81

4.1.3

Exponential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

81

4.1.4

Piece-Wise Linear . . . . . . . . . . . . . . . . . . . . . . . . . . . .

82

4.1.5

Single-Frequency FM . . . . . . . . . . . . . . . . . . . . . . . . . .

82

4.1.6

Amplitude modulated source (AM) . . . . . . . . . . . . . . . . . . .

83

4.1.7

Transient noise source . . . . . . . . . . . . . . . . . . . . . . . . . .

83

4.1.8

Random voltage source . . . . . . . . . . . . . . . . . . . . . . . . . .

84

4.1.9

External voltage or current input . . . . . . . . . . . . . . . . . . . . .

84

4.1.10 Arbitrary Phase Sources . . . . . . . . . . . . . . . . . . . . . . . . .

85

Linear Dependent Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . .

85

4.2.1

Gxxxx: Linear Voltage-Controlled Current Sources (VCCS) . . . . . .

85

4.2.2

Exxxx: Linear Voltage-Controlled Voltage Sources (VCVS) . . . . . .

86

4.2.3

Fxxxx: Linear Current-Controlled Current Sources (CCCS) . . . . . .

86

4.2.4

Hxxxx: Linear Current-Controlled Voltage Sources (CCVS) . . . . . .

86

4.2.5

Polynomial Source Compatibility . . . . . . . . . . . . . . . . . . . .

87

4.2

8
5

CONTENTS
Non-linear Dependent Sources (Behavioral Sources)

89

5.1

Bxxxx: Nonlinear dependent source (ASRC) . . . . . . . . . . . . . . . . . .

89

5.1.1

Syntax and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

89

5.1.2

Special B-Source Variables time, temper, hertz . . . . . . . . . . . . .

92

5.1.3

par(expression) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92

5.1.4

Piecewise Linear Function: pwl . . . . . . . . . . . . . . . . . . . . .

92

Exxxx: non-linear voltage source* . . . . . . . . . . . . . . . . . . . . . . . .

95

5.2.1

VOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

5.2.2

VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

5.2.3

TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

5.2.4

POLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

5.2.5

LAPLACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

96

Gxxxx: non-linear current source* . . . . . . . . . . . . . . . . . . . . . . . .

97

5.3.1

CUR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97

5.3.2

VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97

5.3.3

TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97

5.3.4

POLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

98

5.3.5

LAPLACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

98

5.3.6

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

98

Debugging a behavioral source . . . . . . . . . . . . . . . . . . . . . . . . . .

99

5.2

5.3

5.4
6

Transmission Lines
6.1

Lossless Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.2

Lossy Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102


6.2.1

6.3

6.4

Lossy Transmission Line Model (LTRA) . . . . . . . . . . . . . . . . 102

Uniform Distributed RC Lines . . . . . . . . . . . . . . . . . . . . . . . . . . 104


6.3.1

101

Uniform Distributed RC Model (URC) . . . . . . . . . . . . . . . . . 104

KSPICE Lossy Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . 105


6.4.1

Single Lossy Transmission Line (TXL) . . . . . . . . . . . . . . . . . 105

6.4.2

Coupled Multiconductor Line (CPL) . . . . . . . . . . . . . . . . . . . 106

Diodes

107

7.1

Junction Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.2

Diode Model (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.3

Diode Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

CONTENTS
8

BJTs

9
115

8.1

Bipolar Junction Transistors (BJTs) . . . . . . . . . . . . . . . . . . . . . . . 115

8.2

BJT Models (NPN/PNP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

JFETs

121

9.1

Junction Field-Effect Transistors (JFETs) . . . . . . . . . . . . . . . . . . . . 121

9.2

JFET Models (NJF/PJF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121


9.2.1

JFET level 1 model with Parker Skellern modification . . . . . . . . . 121

9.2.2

JFET level 2 Parker Skellern model . . . . . . . . . . . . . . . . . . . 123

10 MESFETs

125

10.1 MESFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125


10.2 MESFET Models (NMF/PMF) . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.2.1 Model by Statz e.a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.2.2 Model by Ytterdal e.a. . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.2.3 hfet1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.2.4 hfet2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11 MOSFETs

127

11.1 MOSFET devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127


11.2 MOSFET models (NMOS/PMOS) . . . . . . . . . . . . . . . . . . . . . . . . 128
11.2.1 MOS Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.2.2 MOS Level 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.2.3 MOS Level 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.2.4 MOS Level 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.2.5 Notes on Level 1-6 models . . . . . . . . . . . . . . . . . . . . . . . . 130
11.2.6 BSIM Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.2.7 BSIM1 model (level 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.2.8 BSIM2 model (level 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.2.9 BSIM3 model (levels 8, 49) . . . . . . . . . . . . . . . . . . . . . . . 136
11.2.10 BSIM4 model (levels 14, 54) . . . . . . . . . . . . . . . . . . . . . . . 137
11.2.11 EKV model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.2.12 BSIMSOI models (levels 10, 58, 55, 56, 57) . . . . . . . . . . . . . . . 138
11.2.13 SOI3 model (level 60) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.2.14 HiSIM models of the University of Hiroshima . . . . . . . . . . . . . . 138

10

CONTENTS

12 Mixed-Mode and Behavioral Modeling with XSPICE


12.1 Code Model Element & .MODEL Cards

139

. . . . . . . . . . . . . . . . . . . . 139

12.2 Analog Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143


12.2.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.2 Summer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.2.3 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.2.4 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.2.5 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.2.6 Controlled Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.2.7 PWL Controlled Source . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.2.8 Filesource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.2.9 multi_input_pwl block . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.2.10 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.2.11 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.2.12 Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.2.13 Hysteresis Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.2.14 Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.2.15 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.2.16 S-Domain Transfer Function . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.17 Slew Rate Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.2.18 Inductive Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.2.19 Magnetic Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.2.20 Controlled Sine Wave Oscillator . . . . . . . . . . . . . . . . . . . . . 174
12.2.21 Controlled Triangle Wave Oscillator . . . . . . . . . . . . . . . . . . . 175
12.2.22 Controlled Square Wave Oscillator . . . . . . . . . . . . . . . . . . . . 176
12.2.23 Controlled One-Shot . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.2.24 Capacitance Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.2.25 Inductance Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
12.2.26 Memristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
12.3 Hybrid Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.3.1 Digital-to-Analog Node Bridge . . . . . . . . . . . . . . . . . . . . . 183
12.3.2 Analog-to-Digital Node Bridge . . . . . . . . . . . . . . . . . . . . . 184
12.3.3 Controlled Digital Oscillator . . . . . . . . . . . . . . . . . . . . . . . 186
12.3.4 Node bridge from digital to real with enable . . . . . . . . . . . . . . . 187
12.3.5 A Z**-1 block working on real data . . . . . . . . . . . . . . . . . . . 187

CONTENTS

11

12.3.6 A gain block for event-driven real data . . . . . . . . . . . . . . . . . . 188


12.3.7 Node bridge from real to analog voltage . . . . . . . . . . . . . . . . . 189
12.4 Digital Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
12.4.1 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
12.4.2 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.4.3 And . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.4.4 Nand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.4.5 Or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.4.6 Nor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.4.7 Xor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.4.8 Xnor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.4.9 Tristate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
12.4.10 Pullup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
12.4.11 Pulldown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
12.4.12 D Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
12.4.13 JK Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.4.14 Toggle Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.4.15 Set-Reset Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12.4.16 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.4.17 Set-Reset Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.4.18 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
12.4.19 Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
12.4.20 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
12.4.21 Digital Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
12.5 Predefined Node Types for event driven simulation . . . . . . . . . . . . . . . 222
12.5.1 Digital Node Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.5.2 Real Node Type

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

12.5.3 Int Node Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222


12.5.4 (Digital) Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13 Verilog A Device models

223

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223


13.2 adms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
13.3 How to integrate a Verilog-A model into ngspice . . . . . . . . . . . . . . . . 223
13.3.1 How to setup a *.va model for ngspice . . . . . . . . . . . . . . . . . . 223
13.3.2 Adding admsXml to your build environment . . . . . . . . . . . . . . 223

12

CONTENTS

14 Mixed-Level Simulation (ngspice with TCAD)

225

14.1 Cider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225


14.2 GSS, Genius . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
15 Analyses and Output Control (batch mode)

227

15.1 Simulator Variables (.options) . . . . . . . . . . . . . . . . . . . . . . . . . . 227


15.1.1 General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.1.2 DC Solution Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
15.1.3 AC Solution Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
15.1.4 Transient Analysis Options . . . . . . . . . . . . . . . . . . . . . . . . 230
15.1.5 MOSFET Specific options . . . . . . . . . . . . . . . . . . . . . . . . 231
15.1.6 Transmission Lines Specific Options . . . . . . . . . . . . . . . . . . . 231
15.1.7 Precedence of option and .options commands . . . . . . . . . . . . . . 231
15.2 Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
15.2.1 .NODESET: Specify Initial Node Voltage Guesses . . . . . . . . . . . 232
15.2.2 .IC: Set Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . 232
15.3 Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
15.3.1 .AC: Small-Signal AC Analysis . . . . . . . . . . . . . . . . . . . . . 233
15.3.2 .DC: DC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . 234
15.3.3 .DISTO: Distortion Analysis . . . . . . . . . . . . . . . . . . . . . . . 234
15.3.4 .NOISE: Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.3.5 .OP: Operating Point Analysis . . . . . . . . . . . . . . . . . . . . . . 236
15.3.6 .PZ: Pole-Zero Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3.7 .SENS: DC or Small-Signal AC Sensitivity Analysis . . . . . . . . . . 237
15.3.8 .TF: Transfer Function Analysis . . . . . . . . . . . . . . . . . . . . . 238
15.3.9 .TRAN: Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . 238
15.3.10 Transient noise analysis (at low frequency) . . . . . . . . . . . . . . . 239
15.3.11 .PSS: Periodic Steady State Analysis . . . . . . . . . . . . . . . . . . 242
15.4 Measurements after Op, Ac, and Transient Analysis . . . . . . . . . . . . . . . 242
15.4.1 .meas(ure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.4.2 batch versus interactive mode . . . . . . . . . . . . . . . . . . . . . . 243
15.4.3 General remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15.4.4 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
15.4.5 Trig Targ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
15.4.6 Find ... When . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

CONTENTS

13

15.4.7 AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT . . . . . . . . . . . . . . 247


15.4.8 Integ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.4.9 param . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.4.10 par(expression) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.4.11 Deriv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.4.12 More examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
15.5 Batch Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15.5.1 .SAVE: Name vector(s) to be saved in raw file . . . . . . . . . . . . . . 249
15.5.2 .PRINT Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
15.5.3 .PLOT Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
15.5.4 .FOUR: Fourier Analysis of Transient Analysis Output . . . . . . . . . 251
15.5.5 .PROBE: Name vector(s) to be saved in raw file . . . . . . . . . . . . . 252
15.5.6 par(expression): Algebraic expressions for output . . . . . . . . . . . 252
15.5.7 .width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
16 Starting ngspice

255

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255


16.2 Where to obtain ngspice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
16.3 Command line options for starting ngspice and ngnutmeg . . . . . . . . . . . . 256
16.4 Starting options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
16.4.1 Batch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
16.4.2 Interactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
16.4.3 Control mode (Interactive mode with control file or control section) . . 258
16.5 Standard configuration file spinit . . . . . . . . . . . . . . . . . . . . . . . . . 260
16.6 User defined configuration file .spiceinit . . . . . . . . . . . . . . . . . . . . . 261
16.7 Environmental variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.7.1 Ngspice specific variables . . . . . . . . . . . . . . . . . . . . . . . . 261
16.7.2 Common environment variables . . . . . . . . . . . . . . . . . . . . . 262
16.8 Memory usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
16.9 Simulation time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
16.10Ngspice on multi-core processors using OpenMP . . . . . . . . . . . . . . . . 263
16.10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.10.2 Some results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.10.3 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
16.10.4 Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

14

CONTENTS
16.11Server mode option -s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
16.12Ngspice control via input, output fifos . . . . . . . . . . . . . . . . . . . . . . 266
16.13Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.13.1 Compatibility mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.13.2 Missing functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.13.3 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
16.13.4 Controls and commands . . . . . . . . . . . . . . . . . . . . . . . . . 269
16.14Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.15Reporting bugs and errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

17 Interactive Interpreter

273

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273


17.2 Expressions, Functions, and Constants . . . . . . . . . . . . . . . . . . . . . . 273
17.3 Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
17.4 Command Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17.4.1 On the console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17.4.2 Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17.4.3 Add-on to circuit file . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
17.5.1 Ac*: Perform an AC, small-signal frequency response analysis . . . . . 280
17.5.2 Alias: Create an alias for a command . . . . . . . . . . . . . . . . . . 281
17.5.3 Alter*: Change a device or model parameter . . . . . . . . . . . . . . 281
17.5.4 Altermod*: Change model parameter(s)

. . . . . . . . . . . . . . . . 282

17.5.5 Asciiplot: Plot values using old-style character plots . . . . . . . . . . 283


17.5.6 Aspice*: Asynchronous ngspice run . . . . . . . . . . . . . . . . . . . 284
17.5.7 Bug: Mail a bug report . . . . . . . . . . . . . . . . . . . . . . . . . . 284
17.5.8 Cd: Change directory . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
17.5.9 Cdump: Dump the control flow to the screen . . . . . . . . . . . . . . 284
17.5.10 Circbyline*: Enter a circuit line by line . . . . . . . . . . . . . . . . . 285
17.5.11 Codemodel*: Load an XSPICE code model library . . . . . . . . . . . 285
17.5.12 Compose: Compose a vector . . . . . . . . . . . . . . . . . . . . . . . 286
17.5.13 Dc*: Perform a DC-sweep analysis . . . . . . . . . . . . . . . . . . . 286
17.5.14 Define: Define a function . . . . . . . . . . . . . . . . . . . . . . . . . 286
17.5.15 Deftype: Define a new type for a vector or plot . . . . . . . . . . . . . 286
17.5.16 Delete*: Remove a trace or breakpoint . . . . . . . . . . . . . . . . . . 287

CONTENTS

15

17.5.17 Destroy: Delete an output data set . . . . . . . . . . . . . . . . . . . . 287


17.5.18 Devhelp: information on available devices . . . . . . . . . . . . . . . . 287
17.5.19 Diff: Compare vectors . . . . . . . . . . . . . . . . . . . . . . . . . . 288
17.5.20 Display: List known vectors and types . . . . . . . . . . . . . . . . . . 288
17.5.21 Echo: Print text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
17.5.22 Edit*: Edit the current circuit . . . . . . . . . . . . . . . . . . . . . . 288
17.5.23 Eprint*: Print an event driven node (only used with XSPICE option) . . 289
17.5.24 FFT: fast Fourier transform of vectors . . . . . . . . . . . . . . . . . . 289
17.5.25 Fourier: Perform a Fourier transform . . . . . . . . . . . . . . . . . . 291
17.5.26 Gnuplot: Graphics output via Gnuplot . . . . . . . . . . . . . . . . . . 292
17.5.27 Hardcopy: Save a plot to a file for printing . . . . . . . . . . . . . . . 292
17.5.28 Help: Print summaries of Ngspice commands

. . . . . . . . . . . . . 292

17.5.29 History: Review previous commands . . . . . . . . . . . . . . . . . . 292


17.5.30 Inventory: Print circuit inventory . . . . . . . . . . . . . . . . . . . . . 292
17.5.31 Iplot*: Incremental plot . . . . . . . . . . . . . . . . . . . . . . . . . 293
17.5.32 Jobs*: List active asynchronous ngspice runs . . . . . . . . . . . . . . 293
17.5.33 Let: Assign a value to a vector . . . . . . . . . . . . . . . . . . . . . . 293
17.5.34 Linearize*: Interpolate to a linear scale . . . . . . . . . . . . . . . . . 293
17.5.35 Listing*: Print a listing of the current circuit . . . . . . . . . . . . . . 294
17.5.36 Load: Load rawfile data . . . . . . . . . . . . . . . . . . . . . . . . . 294
17.5.37 Meas*: Measurements on simulation data . . . . . . . . . . . . . . . . 294
17.5.38 Mdump*: Dump the matrix values to a file (or to console) . . . . . . . 295
17.5.39 Mrdump*: Dump the matrix right hand side values to a file (or to console)295
17.5.40 Noise*: Noise analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 296
17.5.41 Op*: Perform an operating point analysis . . . . . . . . . . . . . . . . 296
17.5.42 Option*: Set a ngspice option . . . . . . . . . . . . . . . . . . . . . . 296
17.5.43 Plot: Plot values on the display . . . . . . . . . . . . . . . . . . . . . . 297
17.5.44 Pre_<command>: execute commands prior to parsing the circuit . . . . 298
17.5.45 Print: Print values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
17.5.46 Quit: Leave Ngspice or Nutmeg . . . . . . . . . . . . . . . . . . . . . 299
17.5.47 Rehash: Reset internal hash tables . . . . . . . . . . . . . . . . . . . . 299
17.5.48 Remcirc*: Remove the current circuit . . . . . . . . . . . . . . . . . . 299
17.5.49 Reset*: Reset an analysis . . . . . . . . . . . . . . . . . . . . . . . . . 300
17.5.50 Reshape: Alter the dimensionality or dimensions of a vector . . . . . . 300
17.5.51 Resume*: Continue a simulation after a stop . . . . . . . . . . . . . . 300

16

CONTENTS
17.5.52 Rspice*: Remote ngspice submission . . . . . . . . . . . . . . . . . . 301
17.5.53 Run*: Run analysis from the input file . . . . . . . . . . . . . . . . . . 301
17.5.54 Rusage: Resource usage . . . . . . . . . . . . . . . . . . . . . . . . . 301
17.5.55 Save*: Save a set of outputs . . . . . . . . . . . . . . . . . . . . . . . 302
17.5.56 Sens*: Run a sensitivity analysis . . . . . . . . . . . . . . . . . . . . . 303
17.5.57 Set: Set the value of a variable . . . . . . . . . . . . . . . . . . . . . . 304
17.5.58 Setcirc*: Change the current circuit . . . . . . . . . . . . . . . . . . . 304
17.5.59 Setplot: Switch the current set of vectors . . . . . . . . . . . . . . . . 304
17.5.60 Setscale: Set the scale vector for the current plot . . . . . . . . . . . . 304
17.5.61 Settype: Set the type of a vector . . . . . . . . . . . . . . . . . . . . . 305
17.5.62 Shell: Call the command interpreter . . . . . . . . . . . . . . . . . . . 305
17.5.63 Shift: Alter a list variable . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.5.64 Show*: List device state . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.5.65 Showmod*: List model parameter values . . . . . . . . . . . . . . . . 306
17.5.66 Snload*: Load the snapshot file . . . . . . . . . . . . . . . . . . . . . 306
17.5.67 Snsave*: Save a snapshot file . . . . . . . . . . . . . . . . . . . . . . 307
17.5.68 Source: Read a ngspice input file . . . . . . . . . . . . . . . . . . . . 307
17.5.69 Spec: Create a frequency domain plot . . . . . . . . . . . . . . . . . . 308
17.5.70 Status*: Display breakpoint information . . . . . . . . . . . . . . . . . 308
17.5.71 Step*: Run a fixed number of time-points . . . . . . . . . . . . . . . . 308
17.5.72 Stop*: Set a breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . 309
17.5.73 Strcmp: Compare two strings . . . . . . . . . . . . . . . . . . . . . . 309
17.5.74 Sysinfo*: Print system information . . . . . . . . . . . . . . . . . . . 310
17.5.75 Tf*: Run a Transfer Function analysis . . . . . . . . . . . . . . . . . . 310
17.5.76 Trace*: Trace nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
17.5.77 Tran*: Perform a transient analysis . . . . . . . . . . . . . . . . . . . 311
17.5.78 Transpose: Swap the elements in a multi-dimensional data set . . . . . 311
17.5.79 Unalias: Retract an alias . . . . . . . . . . . . . . . . . . . . . . . . . 312
17.5.80 Undefine: Retract a definition . . . . . . . . . . . . . . . . . . . . . . 312
17.5.81 Unlet: Delete the specified vector(s) . . . . . . . . . . . . . . . . . . . 312
17.5.82 Unset: Clear a variable . . . . . . . . . . . . . . . . . . . . . . . . . . 312
17.5.83 Version: Print the version of ngspice . . . . . . . . . . . . . . . . . . . 313
17.5.84 Where*: Identify troublesome node or device . . . . . . . . . . . . . . 314
17.5.85 Wrdata: Write data to a file (simple table) . . . . . . . . . . . . . . . . 314
17.5.86 Write: Write data to a file (Spice3f5 format) . . . . . . . . . . . . . . . 314

CONTENTS

17

17.5.87 Wrs2p: Write scattering parameters to file (Touchstone format) . . . 315


17.5.88 Xgraph: use the xgraph(1) program for plotting. . . . . . . . . . . . . 315
17.6 Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
17.6.1 While - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
17.6.2 Repeat - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
17.6.3 Dowhile - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
17.6.4 Foreach - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
17.6.5 If - Then - Else . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
17.6.6 Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
17.6.7 Goto

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

17.6.8 Continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317


17.6.9 Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
17.7 Internally predefined variables . . . . . . . . . . . . . . . . . . . . . . . . . . 318
17.8 Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
17.8.1 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
17.8.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
17.8.3 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
17.8.4 control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
17.8.5 Example script spectrum . . . . . . . . . . . . . . . . . . . . . . . . 327
17.8.6 Example script for random numbers . . . . . . . . . . . . . . . . . . . 329
17.8.7 Parameter sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
17.8.8 Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
17.9 Scattering parameters (s-parameters) . . . . . . . . . . . . . . . . . . . . . . . 331
17.9.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
17.9.2 S-parameter measurement basics . . . . . . . . . . . . . . . . . . . . . 332
17.9.3 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
17.10MISCELLANEOUS (old stuff, has to be checked for relevance) . . . . . . . . 334
17.11Bugs (old stuff, has to be checked for relevance) . . . . . . . . . . . . . . . . . 334
18 Ngspice User Interfaces

335

18.1 MS Windows Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . 335


18.2 MS Windows Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
18.3 LINUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
18.4 CygWin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
18.5 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

18

CONTENTS
18.6 Postscript printing options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
18.7 Gnuplot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
18.8 Integration with CAD software and third party GUIs . . . . . . . . . . . . . 340
18.8.1 KJWaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
18.8.2 GNU Spice GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
18.8.3 XCircuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

18.8.4 GEDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341


18.8.5 CppSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
18.8.6 NGSPICE Online . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
18.8.7 Spicy Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
18.8.8 MSEspice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
18.8.9 PartSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
19 ngspice as shared library or dynamic link library

343

19.1 Compile options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343


19.1.1 How to get the sources . . . . . . . . . . . . . . . . . . . . . . . . . . 343
19.1.2 LINUX, MINGW, CYGWIN . . . . . . . . . . . . . . . . . . . . . . . 343
19.1.3 MS Visual Studio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
19.2 Linking shared ngspice to a calling application . . . . . . . . . . . . . . . . . 344
19.2.1 Linking during creating the caller . . . . . . . . . . . . . . . . . . . . 344
19.2.2 Loading at runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
19.3 Shared ngspice API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
19.3.1 structs and types defined for transporting data . . . . . . . . . . . . . . 344
19.3.2 Exported functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
19.3.3 Callback functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
19.4 General remarks on using the API . . . . . . . . . . . . . . . . . . . . . . . . 350
19.4.1 Loading a netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
19.4.2 Running the simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 351
19.4.3 Accessing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
19.4.4 Altering model or device parameters . . . . . . . . . . . . . . . . . . . 352
19.4.5 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
19.4.6 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
19.5 Example applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
19.6 ngspice parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
19.6.1 Go parallel! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
19.6.2 Additional exported functions . . . . . . . . . . . . . . . . . . . . . . 355
19.6.3 Additional callback functions . . . . . . . . . . . . . . . . . . . . . . 356
19.6.4 Parallel ngspice example . . . . . . . . . . . . . . . . . . . . . . . . . 357

CONTENTS

19

20 TCLspice

359

20.1 tclspice framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359


20.2 tclspice documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
20.3 spicetoblt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
20.4 Running TCLspice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
20.5 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
20.5.1 Active capacitor measurement . . . . . . . . . . . . . . . . . . . . . . 360
20.5.2 Optimization of a linearization circuit for a Thermistor . . . . . . . . . 363
20.5.3 Progressive display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
20.6 Compiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
20.6.1 LINUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
20.6.2 MS Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
20.7 MS Windows 32 Bit binaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
21 Example Circuits

371

21.1 AC coupled transistor amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 371


21.2 Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
21.3 MOSFET Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
21.4 RTL Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
21.5 Four-Bit Binary Adder (Bipolar) . . . . . . . . . . . . . . . . . . . . . . . . . 378
21.6 Four-Bit Binary Adder (MOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 380
21.7 Transmission-Line Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
22 Statistical circuit analysis

383

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383


22.2 Using random param(eters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
22.3 Behavioral sources (B, E, G, R, L, C) with random control . . . . . . . . . . . 385
22.4 ngspice scripting language . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
22.5 Monte-Carlo Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
22.5.1 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
22.5.2 Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
22.6 Data evaluation with Gnuplot . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

20

CONTENTS

23 Circuit optimization with ngspice

391

23.1 Optimization of a circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391


23.2 ngspice optimizer using ngspice scripts . . . . . . . . . . . . . . . . . . . . . 392
23.3 ngspice optimizer using tclspice . . . . . . . . . . . . . . . . . . . . . . . . . 392
23.4 ngspice optimizer using a Python script . . . . . . . . . . . . . . . . . . . . . 392
23.5 ngspice optimizer using ASCO . . . . . . . . . . . . . . . . . . . . . . . . . . 392
23.5.1 Three stage operational amplifier . . . . . . . . . . . . . . . . . . . . . 393
23.5.2 Digital inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
23.5.3 Bandpass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
23.5.4 Class-E power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 396
24 Notes

397

24.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397


24.2 Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

II

XSPICE Software Users Manual

25 XSPICE Basics

401
403

25.1 ngspice with the XSPICE option . . . . . . . . . . . . . . . . . . . . . . . . . 403


25.2 The XSPICE Code Model Subsystem . . . . . . . . . . . . . . . . . . . . . . 403
25.3 XSPICE Top-Level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
26 Execution Procedures

405

26.1 Simulation and Modeling Overview . . . . . . . . . . . . . . . . . . . . . . . 405


26.1.1 Describing the Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 405
26.2 Circuit Description Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
26.2.1 XSPICE Syntax Extensions . . . . . . . . . . . . . . . . . . . . . . . 411
26.3 How to create code models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
27 Example circuits

417

27.1 Amplifier with XSPICE model gain . . . . . . . . . . . . . . . . . . . . . . 417


27.2 XSPICE advanced usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
27.2.1 Circuit example C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
27.2.2 Running example C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

CONTENTS

21

28 Code Models and User-Defined Nodes

427

28.1 Code Model Data Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . 428


28.2 Creating Code Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
28.3 Creating User-Defined Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
28.4 Adding a new code model library . . . . . . . . . . . . . . . . . . . . . . . . . 430
28.5 Compiling and loading the new code model (library) . . . . . . . . . . . . . . 430
28.6 Interface Specification File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
28.6.1 The Name Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
28.6.2 The Port Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
28.6.3 The Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
28.6.4 Static Variable Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
28.7 Model Definition File

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

28.7.1 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438


28.7.2 Function Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
28.8 User-Defined Node Definition File . . . . . . . . . . . . . . . . . . . . . . . . 454
28.8.1 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
28.8.2 Function Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
28.8.3 Example UDN Definition File . . . . . . . . . . . . . . . . . . . . . . 457
29 Error Messages

461

29.1 Preprocessor Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 461


29.2 Simulator Error Messages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

29.3 Code Model Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 467


29.3.1 Code Model aswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
29.3.2 Code Model climit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
29.3.3 Code Model core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
29.3.4 Code Model d_osc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
29.3.5 Code Model d_source . . . . . . . . . . . . . . . . . . . . . . . . . . 469
29.3.6 Code Model d_state . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
29.3.7 Code Model oneshot . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
29.3.8 Code Model pwl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
29.3.9 Code Model s_xfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
29.3.10 Code Model sine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
29.3.11 Code Model square

. . . . . . . . . . . . . . . . . . . . . . . . . . . 471

29.3.12 Code Model triangle . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

22

III

CONTENTS

CIDER

473

30 CIDER Users Manual

475

30.1 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475


30.1.1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
30.2 BOUNDARY, INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
30.2.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

30.2.2 PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478


30.2.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
30.3 COMMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
30.3.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

30.3.2 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479


30.4 CONTACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
30.4.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

30.4.2 PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479


30.4.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
30.4.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
30.5 DOMAIN, REGION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
30.5.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

30.5.2 PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480


30.5.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
30.5.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
30.6 DOPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
30.6.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

30.6.2 PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484


30.6.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
30.6.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
30.7 ELECTRODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
30.7.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

30.7.2 PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486


30.7.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
30.7.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
30.8 END

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

30.8.1 DESCRIPTION
30.9 MATERIAL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

CONTENTS

23

30.9.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

30.9.2 PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488


30.9.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
30.9.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
30.10METHOD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

30.10.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

30.10.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489


30.10.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
30.11Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
30.11.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
30.11.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
30.11.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
30.11.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
30.11.5 BUGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

30.12MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
30.12.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

30.12.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492


30.12.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
30.12.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
30.12.5 Bugs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
30.13OPTIONS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

30.13.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

30.13.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494


30.13.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
30.13.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
30.14OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
30.14.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

30.14.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496


30.14.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
30.14.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
30.15TITLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
30.15.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

30.15.2 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497


30.15.3 BUGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

30.16X.MESH, Y.MESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

24

CONTENTS
30.16.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

30.16.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499


30.16.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
30.16.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
30.17NUMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
30.17.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

30.17.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501


30.17.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
30.17.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
30.17.5 BUGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

30.18NBJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
30.18.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

30.18.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503


30.18.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
30.18.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
30.18.5 BUGS
30.19NUMOS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

30.19.1 DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

30.19.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505


30.19.3 EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
30.19.4 SEE ALSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
30.20Cider examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

IV

Appendices

31 Model and Device Parameters

507
509

31.1 Accessing internal device parameters . . . . . . . . . . . . . . . . . . . . . . . 509


31.2 Elementary Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
31.2.1 Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
31.2.2 Capacitor - Fixed capacitor . . . . . . . . . . . . . . . . . . . . . . . . 513
31.2.3 Inductor - Fixed inductor . . . . . . . . . . . . . . . . . . . . . . . . . 514
31.2.4 Mutual - Mutual Inductor . . . . . . . . . . . . . . . . . . . . . . . . . 515
31.3 Voltage and current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
31.3.1 ASRC - Arbitrary source . . . . . . . . . . . . . . . . . . . . . . . . . 516
31.3.2 Isource - Independent current source . . . . . . . . . . . . . . . . . . . 517

CONTENTS

25

31.3.3 Vsource - Independent voltage source . . . . . . . . . . . . . . . . . . 518


31.3.4 CCCS - Current controlled current source . . . . . . . . . . . . . . . . 519
31.3.5 CCVS - Current controlled voltage source . . . . . . . . . . . . . . . . 519
31.3.6 VCCS - Voltage controlled current source . . . . . . . . . . . . . . . . 520
31.3.7 VCVS - Voltage controlled voltage source . . . . . . . . . . . . . . . . 520
31.4 Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
31.4.1 CplLines - Simple Coupled Multiconductor Lines . . . . . . . . . . . . 521
31.4.2 LTRA - Lossy transmission line . . . . . . . . . . . . . . . . . . . . . 522
31.4.3 Tranline - Lossless transmission line . . . . . . . . . . . . . . . . . . . 523
31.4.4 TransLine - Simple Lossy Transmission Line . . . . . . . . . . . . . . 524
31.4.5 URC - Uniform R. C. line . . . . . . . . . . . . . . . . . . . . . . . . 525
31.5 BJTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
31.5.1 BJT - Bipolar Junction Transistor . . . . . . . . . . . . . . . . . . . . 526
31.5.2 BJT - Bipolar Junction Transistor Level 2 . . . . . . . . . . . . . . . . 529
31.5.3 VBIC - Vertical Bipolar Inter-Company Model . . . . . . . . . . . . . 532
31.6 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
31.6.1 MOS1 - Level 1 MOSFET model with Meyer capacitance model . . . . 536
31.6.2 MOS2 - Level 2 MOSFET model with Meyer capacitance model . . . . 539
31.6.3 MOS3 - Level 3 MOSFET model with Meyer capacitance model

. . . 543

31.6.4 MOS6 - Level 6 MOSFET model with Meyer capacitance model

. . . 547

31.6.5 MOS9 - Modified Level 3 MOSFET model . . . . . . . . . . . . . . . 550


31.6.6 BSIM1 - Berkeley Short Channel IGFET Model . . . . . . . . . . . . 554
31.6.7 BSIM2 - Berkeley Short Channel IGFET Model . . . . . . . . . . . . 557
31.6.8 BSIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
31.6.9 BSIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
32 Compilation notes

565

32.1 Ngspice Installation under LINUX (and other UNIXes) . . . . . . . . . . . . 565


32.1.1 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
32.1.2 Install from Git . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
32.1.3 Install from a tarball, e.g. ngspice-rework-25.tgz . . . . . . . . . . . . 567
32.1.4 Compilation using an user defined directory tree for object files . . . . 567
32.1.5 Advanced Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
32.1.6 Compilers and Options . . . . . . . . . . . . . . . . . . . . . . . . . . 569
32.1.7 Compiling For Multiple Architectures . . . . . . . . . . . . . . . . . . 570

26

CONTENTS
32.1.8 Installation Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
32.1.9 Optional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
32.1.10 Specifying the System Type . . . . . . . . . . . . . . . . . . . . . . . 571
32.1.11 Sharing Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
32.1.12 Operation Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
32.2 Ngspice Compilation under WINDOWS OS

. . . . . . . . . . . . . . . . . . 571

32.2.1 How to make ngspice with MINGW and MSYS

. . . . . . . . . . . . 571

32.2.2 64 Bit executables with MINGW-w64 . . . . . . . . . . . . . . . . . . 573


32.2.3 make ngspice with MS Visual Studio 2008 or 2010 . . . . . . . . . . . 574
32.2.4 make ngspice with pure CYGWIN . . . . . . . . . . . . . . . . . . . . 576
32.2.5 ngspice mingw or cygwin console executable . . . . . . . . . . . . . . 576
32.2.6 make ngspice with CYGWIN and external MINGW32 . . . . . . . . . 576
32.2.7 make ngspice with CYGWIN and internal MINGW32 (use config.h
made above) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
32.3 Reporting errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
33 Copyrights and licenses

579

33.1 Documentation license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579


33.1.1 Spice documentation copyright . . . . . . . . . . . . . . . . . . . . . . 579
33.1.2 XSPICE SOFTWARE (documentation) copyright . . . . . . . . . . . . 579
33.1.3 CIDER RESEARCH SOFTWARE AGREEMENT (superseded by 33.2.1)580
33.2 ngspice license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
33.2.1 Modified BSD license . . . . . . . . . . . . . . . . . . . . . . . . . 581
33.2.2 XSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
33.2.3 tclspice, numparam . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
33.2.4 Linking to GPLd libraries (e.g. readline): . . . . . . . . . . . . . . . . 582

Prefaces
Preface to the first edition
This manual has been assembled from different sources:
1. The spice3f5 manual,
2. the XSPICE users manual,
3. the CIDER users manual
and some original material needed to describe the new features and the newly implemented
models. This cut and paste approach, while not being orthodox, allowed ngspice to have a full
manual in a fraction of the time that writing a completely new text would have required. The use
of LaTex and Lyx instead of TeXinfo, which was the original encoding for the manual, further
helped to reduce the writing effort and improved the quality of the result, at the expense of an
on-line version of the manual but, due to the complexity of the software I hardly think that users
will ever want to read an on-line text version.
In writing this text I followed the cut of spice3f5 manual, both in the chapter sequence and
presentation of material, mostly because that was already the user manual of spice.
Ngspice is an open source software, users can download the source code, compile, and run it.
This manual has an entire chapter describing program compilation and available options to help
users in building ngspice (see chapt. 32). The source package already comes with all safe
options enabled by default, and activating the others can produce unpredictable results and thus
is recommended to expert users only. This is the first ngspice manual and I have removed all
the historical material that described the differences between ngspice and spice3, since it was
of no use for the user and not so useful for the developer who can look for it in the Changelogs
of in the revision control system.
I want to acknowledge the work dome Emmanuel Rouat and Arno W. Peters for converting to
TEXinfo the original spice3f documentation, their effort gave ngspice users the only available
documentation that described the changes for many years. A good source of ideas for this
manual comes from the on-line spice3f manual written by Charles D.H. Williams (Spice3f5
User Guide), constantly updated and useful for some insight that he gives in it.
As always, errors, omissions and unreadable phrases are only my fault.
Paolo Nenzi
Roma, March 24th 2001

27

28

CONTENTS
Indeed. At the end of the day, this is engineering, and one learns to live
within the limitations of the tools.

Kevin Aylward , Warden of the Kings Ale

Preface to the actual edition (as of January 2013)


Due to the wealth of new material and options in ngspice the actual order of chapters has been
revised. Several new chapters have been added. The LYX text processor has allowed adding
internal cross references. The PDF format has become the standard format for distribution of
the manual. Within each new ngspice distribution (starting with ngspice-21) a manual edition
is provided reflecting the ngspice status at the time of distribution. At the same time, located
at ngspice manuals, the manual is constantly updated. Every new ngspice feature should enter
this manual as soon as it has been made available in the Git source code.
Holger Vogt
Mlheim, 2013

Acknowledgments
ngspice contributors
Spice was originally written at The University of California at Berkeley (USA).
Since then, there have been many people working on the software, most of them releasing
patches to the original code through the Internet.
The following people have contributed in some way:
Vera Albrecht,
Cecil Aswell,
Giles C. Billingsley,
Phil Barker,
Steven Borley,
Stuart Brorson,
Mansun Chan,
Wayne A. Christopher,
Al Davis,
Glao S. Dezai,
Jon Engelbert,
Daniele Foci,
Noah Friedman,
David A. Gates,
Alan Gillespie,
John Heidemann,
Jeffrey M. Hsu,
JianHui Huang,
S. Hwang,
Chris Inbody,
Gordon M. Jacobs,
Min-Chie Jeng,

29

30
Beorn Johnson,
Stefan Jones,
Kenneth H. Keller,
Francesco Lannutti,
Robert Larice,
Mathew Lew,
Robert Lindsell,
Weidong Liu,
Kartikeya Mayaram,
Richard D. McRoberts,
Manfred Metzger,
Wolfgang Muees,
Paolo Nenzi,
Gary W. Ng,
Hong June Park,
Stefano Perticaroli,
Arno Peters,
Serban-Mihai Popescu,
Georg Post,
Thomas L. Quarles,
Emmanuel Rouat,
Jean-Marc Routure,
Jaijeet S. Roychowdhury,
Lionel Sainte Cluque,
Takayasu Sakurai,
Amakawa Shuhei,
Kanwar Jit Singh,
Bill Swartz,
Hitoshi Tanaka,
Steve Tell,
Andrew Tuckey,
Andreas Unger,
Holger Vogt,
Dietmar Warning,
Michael Widlok,

CONTENTS

CONTENTS

31

Charles D.H. Williams,


Antony Wilson,
and many others...
If someone helped in the development and has not been inserted in this list then this omission was unintentional. If you feel you should be on this list then please write to <ngspicedevel@lists.sourceforge.net>. Do not be shy, we would like to make a list as complete as
possible.

XSPICE
The XSPICE simulator is based on the SPICE3 program developed by the Electronics Research
Laboratory, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley. The authors of XSPICE gratefully acknowledge UC Berkeleys development
and distribution of this software, and their licensing policies which promote further improvements to simulation technology.
We also gratefully acknowledge the participation and support of our U.S. Air Force sponsors, the Aeronautical Systems Center and the Warner Robins Air Logistics Command, without
which the development of XSPICE would not have been possible.

32

CONTENTS

Chapter 1
Introduction
Ngspice is a general-purpose circuit simulation program for nonlinear and linear analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent or dependent
voltage and current sources, loss-less and lossy transmission lines, switches, uniform distributed
RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs,
and MOSFETs.
Some introductory remarks on how to use ngspice may be found in chapter 21.
Ngspice is an update of Spice3f5, the last Berkeleys release of Spice3 simulator family. Ngspice
is being developed to include new features to existing Spice3f5 and to fix its bugs. Improving
a complex software like a circuit simulator is a very hard task and, while some improvements
have been made, most of the work has been done on bug fixing and code refactoring.
Ngspice has built-in models for the semiconductor devices, and the user need specify only the
pertinent model parameter values. There are three models for bipolar junction transistors, all
based on the integral-charge model of Gummel and Poon; however, if the Gummel-Poon parameters are not specified, the basic model (BJT) reduces to the simpler Ebers-Moll model. In either
case and in either models, charge storage effects, ohmic resistances, and a current-dependent
output conductance may be included. The second bipolar model BJT2 adds dc current computation in the substrate diode. The third model (VBIC) contains further enhancements for
advanced bipolar devices.
The semiconductor diode model can be used for either junction diodes or Schottky barrier
diodes. There are two models for JFET: the first (JFET) is based on the model of Shichman
and Hodges, the second (JFET2) is based on the Parker-Skellern model. All the original six
MOSFET models are implemented: MOS1 is described by a square-law I-V characteristic,
MOS2 [1] is an analytical model, while MOS3 [1] is a semi-empirical model; MOS6 [2] is a
simple analytic model accurate in the short channel region; MOS9, is a slightly modified Level
3 MOSFET model - not to confuse with Philips level 9; BSIM 1 [3, 4]; BSIM2 [5] are the
old BSIM (Berkeley Short-channel IGFET Model) models. MOS2, MOS3, and BSIM include
second-order effects such as channel-length modulation, subthreshold conduction, scatteringlimited velocity saturation, small-size effects, and charge controlled capacitances. The recent
MOS models for submicron devices are the BSIM3 (Berkeley BSIM3 web page) and BSIM4
(Berkeley BSIM4 web page) models. Silicon-on-insulator MOS transistors are described by the
SOI models from the BSIMSOI family (Berkeley BSIMSOI web page) and the STAG [18] one.
There is partial support for a couple of HFET models and one model for MESA devices.

33

34

CHAPTER 1. INTRODUCTION

Ngspice supports mixed-level simulation and provides a direct link between technology parameters and circuit performance. A mixed-level circuit and device simulator can provide greater
simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the
critical devices in a circuit. Compact models can be used for noncritical devices. The mixedlevel extensions to ngspice are two:
CIDER: a mixed-level circuit and device simulator integrated into ngspice code. CIDER
was originally the name of the mixed-level extension made to spice3f5.
GSS: GSS (now called GENIUS) TCAD is a 2D simulator developed independently from
ngspice. The device simulator itself is free and not included into ngspice, but a socket
interface is provided.
Ngspice supports mixed-signal simulation through the integration of XSPICE code into it.
XSPICE software, developed as an extension to Spice3C1 from GeorgiaTech, has been ported
to ngspice to provide board level and mixed-signal simulation.
New devices can be added to ngspice by two means: the XSPICE code-model interface and the
ADMS interface based on Verilog-A and XML.
Finally, numerous small bugs have been discovered and fixed, and the program has been ported
to a wider variety of computing platforms.

1.1

Simulation Algorithms

Computer-based circuit simulation is often used as a tool by designers, test engineers, and
others who want to analyze the operation of a design without examining the physical circuit.
Simulation allows you to change quickly the parameters of many of the circuit elements to
determine how they affect the circuit response. Often it is difficult or impossible to change
these parameters in a physical circuit.
However, to be practical, a simulator must execute in a reasonable amount of time. The key to
efficient execution is choosing the proper level of modeling abstraction for a given problem. To
support a given modeling abstraction, the simulator must provide appropriate algorithms.
Historically, circuit simulators have supported either an analog simulation algorithm or a digital
simulation algorithm. Ngspice inherits the XSPICE framework and supports both analog and
digital algorithms and is a mixed-mode simulator.

1.1.1

Analog Simulation

Analog simulation focuses on the linear and non-linear behavior of a circuit over a continuous
time or frequency interval. The circuit response is obtained by iteratively solving Kirchhoffs
Laws for the circuit at time steps selected to ensure the solution has converged to a stable value
and that numerical approximations of integrations are sufficiently accurate. Since Kirchhoffs
laws form a set of simultaneous equations, the simulator operates by solving a matrix of equations at each time point. This matrix processing generally results in slower simulation times
when compared to digital circuit simulators.

1.1. SIMULATION ALGORITHMS

35

The response of a circuit is a function of the applied sources. Ngspice offers a variety of
source types including DC, sine-wave, and pulse. In addition to specifying sources, the user
must define the type of simulation to be run. This is termed the mode of analysis. Analysis
modes include DC analysis, AC analysis, and transient analysis. For DC analysis, the timevarying behavior of reactive elements is neglected and the simulator calculates the DC solution
of the circuit. Swept DC analysis may also be accomplished with ngspice. This is simply the
repeated application of DC analysis over a range of DC levels for the input sources. For AC
analysis, the simulator determines the response of the circuit, including reactive elements to
small-signal sinusoidal inputs over a range of frequencies. The simulator output in this case
includes amplitudes and phases as a function of frequency. For transient analysis, the circuit
response, including reactive elements, is analyzed to calculate the behavior of the circuit as a
function of time.

1.1.2

Digital Simulation

Digital circuit simulation differs from analog circuit simulation in several respects. A primary
difference is that a solution of Kirchhoffs laws is not required. Instead, the simulator must only
determine whether a change in the logic state of a node has occurred and propagate this change
to connected elements. Such a change is called an event.
When an event occurs, the simulator examines only those circuit elements that are affected by
the event. As a result, matrix analysis is not required in digital simulators. By comparison,
analog simulators must iteratively solve for the behavior of the entire circuit because of the
forward and reverse transmission properties of analog components. This difference results in
a considerable computational advantage for digital circuit simulators, which is reflected in the
significantly greater speed of digital simulations.

1.1.3

Mixed-Mode Simulation

Modern circuits often contain a mix of analog and digital circuits. To simulate such circuits
efficiently and accurately a mix of analog and digital simulation techniques is required. When
analog simulation algorithms are combined with digital simulation algorithms, the result is
termed mixed-mode simulation.
Two basic methods of implementing mixed-mode simulation used in practice are the native
mode and glued mode approaches. Native mode simulators implement both an analog algorithm and a digital algorithm in the same executable. Glued mode simulators actually use two
simulators, one of which is analog and the other digital. This type of simulator must define an
input/output protocol so that the two executables can communicate with each other effectively.
The communication constraints tend to reduce the speed, and sometimes the accuracy, of the
complete simulator. On the other hand, the use of a glued mode simulator allows the component
models developed for the separate executables to be used without modification.
Ngspice is a native mode simulator providing both analog and event-based simulation in the
same executable. The underlying algorithms of ngspice (coming from XSPICE and its Code
Model Subsystem) allow use of all the standard SPICE models, provide a pre-defined collection
of the most common analog and digital functions, and provide an extensible base on which to
build additional models.

36
1.1.3.1

CHAPTER 1. INTRODUCTION
User-Defined Nodes

Ngspice supports creation of User-Defined Node types. User-Defined Node types allow you
to specify nodes that propagate data other than voltages, currents, and digital states. Like digital
nodes, User-Defined Nodes use event-driven simulation, but the state value may be an arbitrary
data type. A simple example application of User-Defined Nodes is the simulation of a digital
signal processing filter algorithm. In this application, each node could assume a real or integer
value. More complex applications may define types that involve complex data such as digital
data vectors or even non-electronic data.
Ngspice digital simulation is actually implemented as a special case of this User-Defined Node
capability where the digital state is defined by a data structure that holds a Boolean logic state
and a strength value.

1.1.4

Mixed-Level Simulation

Ngspice can simulate numerical device models for diodes and transistors in two different ways,
either through the integrated DSIM simulator or interfacing to GSS TCAD system. DSIM is
an internal C-based device simulator which is part of the CIDER simulator, the mixed-level
simulator based on spice3f5. CIDER within ngspice provides circuit analyses, compact models
for semiconductor devices, and one- or two-dimensional numerical device models.
1.1.4.1

CIDER (DSIM)

DSIM provides accurate, one- and two-dimensional numerical device models based on the solution of Poissons equation, and the electron and hole current-continuity equations. DSIM
incorporates many of the same basic physical models found in the Stanford two-dimensional
device simulator PISCES. Input to CIDER consists of a SPICE-like description of the circuit
and its compact models, and PISCES-like descriptions of the structures of numerically modeled
devices. As a result, CIDER should seem familiar to designers already accustomed to these
two tools. CIDER is based on the mixed-level circuit and device simulator CODECS, and is a
replacement for this program. The basic algorithms of the two programs are the same. Some of
the differences between CIDER and CODECS are described below. The CIDER input format
has greater flexibility and allows increased access to physical model parameters. New physical
models have been added to allow simulation of state-of-the-art devices. These include transverse field mobility degradation important in scaled-down MOSFETs and a polysilicon model
for poly-emitter bipolar transistors. Temperature dependence has been included over the range
from -50C to 150C. The numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and
JFETs can be modeled with or without a substrate contact. Support has been added for the
management of device internal states. Post-processing of device states can be performed using
the ngnutmeg user interface.
1.1.4.2

GSS TCAD

GSS is a TCAD software which enables two-dimensional numerical simulation of semiconductor device with well-known drift-diffusion and hydrodynamic method. GSS has Basic DDM

1.2. SUPPORTED ANALYSES

37

(drift-diffusion method) solver, Lattice Temperature Corrected DDM solver, EBM (energy balance method) solver and Quantum corrected DDM solver which based on density-gradient theory. The GSS program is directed via input statements by a user specified disk file. Supports
triangle mesh generation and adaptive mesh refinement. Employs PMI (physical model interface) to support various materials, including compound semiconductor materials such as SiGe
and AlGaAs. Supports DC sweep, transient and AC sweep calculations. The device can be
stimulated by voltage or current source(s).
GSS is no longer updated, but is still available as open source as a limited edition of the commercial GENIUS TCAD tool.

1.2

Supported Analyses

The ngspice simulator supports the following different types of analysis:


1. DC Analysis (Operating Point and DC Sweep)
2. AC Small-Signal Analysis
3. Transient Analysis
4. Pole-Zero Analysis
5. Small-Signal Distortion Analysis
6. Sensitivity Analysis
7. Noise Analysis
Applications that are exclusively analog can make use of all analysis modes with the exception
of Code Model subsystem that do not implements Pole-Zero, Distortion, Sensitivity and Noise
analyses. Event-driven applications that include digital and User-Defined Node types may make
use of DC (operating point and DC sweep) and Transient only.
In order to understand the relationship between the different analyses and the two underlying
simulation algorithms of ngspice, it is important to understand what is meant by each analysis
type. This is detailed below.

1.2.1

DC Analyses

The dc analysis portion of ngspice determines the dc operating point of the circuit with inductors
shorted and capacitors opened. The dc analysis options are specified on the .DC, .TF, and .OP
control lines.
There is assumed to be no time dependence on any of the sources within the system description.
The simulator algorithm subdivides the circuit into those portions which require the analog
simulator algorithm and those which require the event-driven algorithm. Each subsystem block
is then iterated to solution, with the interfaces between analog nodes and event-driven nodes
iterated for consistency across the entire system.

38

CHAPTER 1. INTRODUCTION

Once stable values are obtained for all nodes in the system, the analysis halts and the results
may be displayed or printed out as you request them.
A dc analysis is automatically performed prior to a transient analysis to determine the transient
initial conditions, and prior to an ac small-signal analysis to determine the linearized, smallsignal models for nonlinear devices. If requested, the dc small-signal value of a transfer function
(ratio of output variable to input source), input resistance, and output resistance is also computed
as a part of the dc solution. The dc analysis can also be used to generate dc transfer curves: a
specified independent voltage, current source, resistor or temperature1 is stepped over a userspecified range and the dc output variables are stored for each sequential source value.

1.2.2

AC Small-Signal Analysis

AC analysis is limited to analog nodes and represents the small signal, sinusoidal solution of the
analog system described at a particular frequency or set of frequencies. This analysis is similar
to the DC analysis in that it represents the steady-state behavior of the described system with a
single input node at a given set of stimulus frequencies.
The program first computes the dc operating point of the circuit and determines linearized,
small-signal models for all of the nonlinear devices in the circuit. The resultant linear circuit
is then analyzed over a user-specified range of frequencies. The desired output of an ac smallsignal analysis is usually a transfer function (voltage gain, transimpedance, etc). If the circuit
has only one ac input, it is convenient to set that input to unity and zero phase, so that output
variables have the same value as the transfer function of the output variable with respect to the
input.

1.2.3

Transient Analysis

Transient analysis is an extension of DC analysis to the time domain. A transient analysis begins by obtaining a DC solution to provide a point of departure for simulating time-varying
behavior. Once the DC solution is obtained, the time-dependent aspects of the system are reintroduced, and the two simulator algorithms incrementally solve for the time varying behavior of
the entire system. Inconsistencies in node values are resolved by the two simulation algorithms
such that the time-dependent waveforms created by the analysis are consistent across the entire
simulated time interval. Resulting time-varying descriptions of node behavior for the specified
time interval are accessible to you.
All sources which are not time dependent (for example, power supplies) are set to their dc value.
The transient time interval is specified on a .TRAN control line.

1.2.4

Pole-Zero Analysis

The pole-zero analysis portion of Ngspice computes the poles and/or zeros in the small-signal
ac transfer function. The program first computes the dc operating point and then determines
the linearized, small-signal models for all the nonlinear devices in the circuit. This circuit is
1 Temperature

(TEMP) and resistance sweeps have been introduced in Ngspice, they were not available in the
original code of Spice3f5.

1.2. SUPPORTED ANALYSES

39

then used to find the poles and zeros of the transfer function. Two types of transfer functions
are allowed: one of the form (output voltage)/(input voltage) and the other of the form (output
voltage)/(input current). These two types of transfer functions cover all the cases and one can
find the poles/zeros of functions like input/output impedance and voltage gain. The input and
output ports are specified as two pairs of nodes. The pole-zero analysis works with resistors,
capacitors, inductors, linear-controlled sources, independent sources, BJTs, MOSFETs, JFETs
and diodes. Transmission lines are not supported. The method used in the analysis is a suboptimal numerical search. For large circuits it may take a considerable time or fail to find all
poles and zeros. For some circuits, the method becomes "lost" and finds an excessive number
of poles or zeros.

1.2.5

Small-Signal Distortion Analysis

The distortion analysis portion of Ngspice computes steady-state harmonic and intermodulation
products for small input signal magnitudes. If signals of a single frequency are specified as the
input to the circuit, the complex values of the second and third harmonics are determined at
every point in the circuit. If there are signals of two frequencies input to the circuit, the analysis
finds out the complex values of the circuit variables at the sum and difference of the input
frequencies, and at the difference of the smaller frequency from the second harmonic of the
larger frequency. Distortion analysis is supported for the following nonlinear devices:
Diodes (DIO),
BJT,
JFET (level 1),
MOSFETs (levels 1, 2, 3, 9, and BSIM1),
MESFET (level 1).
All linear devices are automatically supported by distortion analysis. If there are switches
present in the circuit, the analysis continues to be accurate provided the switches do not change
state under the small excitations used for distortion calculations.
If a device model does not support direct small signal distortion analysis, please use the Fourier
statement and evaluate the output per scripting.

1.2.6

Sensitivity Analysis

Ngspice will calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an output variable with respect to all circuit variables, including model parameters.
Ngspice calculates the difference in an output variable (either a node voltage or a branch current)
by perturbing each parameter of each device independently. Since the method is a numerical
approximation, the results may demonstrate second order affects in highly sensitive parameters,
or may fail to show very low but non-zero sensitivity. Further, since each variable is perturb
by a small fraction of its value, zero-valued parameters are not analyzed (this has the benefit of
reducing what is usually a very large amount of data).

40

1.2.7

CHAPTER 1. INTRODUCTION

Noise Analysis

The noise analysis portion of Ngspice does analysis device-generated noise for the given circuit. When provided with an input source and an output port, the analysis calculates the noise
contributions of each device (and each noise generator within the device) to the output port
voltage. It also calculates the input noise to the circuit, equivalent to the output noise referred
to the specified input source. This is done for every frequency point in a specified range - the
calculated value of the noise corresponds to the spectral density of the circuit variable viewed as
a stationary Gaussian stochastic process. After calculating the spectral densities, noise analysis
integrates these values over the specified frequency range to arrive at the total noise voltage/current (over this frequency range). This calculated value corresponds to the variance of the circuit
variable viewed as a stationary Gaussian process.

1.2.8

Periodic Steady State Analysis

(Experimental code, not yet made publicly available!)


PSS is a radio frequency periodical large-signal dedicated analysis. The implementation is
based on a time domain shooting like method which make use of Transient analysis. As it is in
early development stage, PSS performs analysis only on autonomous circuits, meaning that it is
only able to predict fundamental frequency and amplitude (and also harmonics) for oscillators,
VCOs, etc.. The algorithm is based on a minimum search of the error vector taken as the
difference of RHS vectors between two occurrences of an estimated period. The convergence
is reached when the mean of error vector decrease below a given threshold that can be set as a
analysis parameter. Results of this analysis are the basis of every periodical large-signal analysis
as PAC or PNoise.

1.3

Analysis at Different Temperatures

Temperature, in ngspice, is a property associated to the entire circuit, rather than an analysis option. Circuit temperature has a default (nominal) value of 27C (300.15 K) that can be changed
using the TEMP option in an .option control line (see 15.1.1) or by the .TEMP line (see 2.11),
which has precedence over the .option TEMP line. All analyses are, thus, performed at circuit
temperature, and if you want to simulate circuit behavior at different temperatures you should
prepare a netlist for each temperature.
All input data for ngspice is assumed to have been measured at the circuit nominal temperature. This value can further be overridden for any device which models temperature effects by
specifying the TNOM parameter on the .model itself. Individual instances may further override
the circuit temperature through the specification of TEMP and DTEMP parameters on the instance.
The two options are not independent even if you can specify both on the instance line, the TEMP
option overrides DTEMP. The algorithm to compute instance temperature is described below:

1.3. ANALYSIS AT DIFFERENT TEMPERATURES

41

Algorithm 1.1 Instance temperature computation


IF TEMP is specified THEN
instance_temperature = TEMP
ELSE IF
instance_temperature = circuit_temperature + DTEMP
END IF
Temperature dependent support is provided for all devices except voltage and current sources
(either independent and controlled) and BSIM models. BSIM MOSFETs have an alternate temperature dependency scheme which adjusts all of the model parameters before input to ngspice.
For details of the BSIM temperature adjustment, see [6] and [7]. Temperature appears explicitly
in the exponential terms of the BJT and diode model equations. In addition, saturation currents
have a built-in temperature dependence. The temperature dependence of the saturation current
in the BJT models is determined by:


T1
IS (T1 ) = IS (T0 )
T0

XT I

Eg q (T1 T0 )
exp
k (T1 T0 )


(1.1)

where k is Boltzmanns constant, q is the electronic charge, Eg is the energy gap which is a
model parameter, and XT I is the saturation current temperature exponent (also a model parameter, and usually equal to 3).
The temperature dependence of forward and reverse beta is according to the formula:


T1
B (T1 ) = B (T0 )
T0

XT B
(1.2)

where T0 and T1 are in degrees Kelvin, and XT B is a user-supplied model parameter. Temperature effects on beta are carried out by appropriate adjustment to the values of BF , ISE , BR , and
ISC (spice model parameters BF, ISE, BR, and ISC, respectively).
Temperature dependence of the saturation current in the junction diode model is determined by:


T1
IS (T1 ) = IS (T0 )
T0

 XT I
N

Eg q (T1 T0 )
exp
Nk (T1 T0 )


(1.3)

where N is the emission coefficient, which is a model parameter, and the other symbols have
the same meaning as above. Note that for Schottky barrier diodes, the value of the saturation
current temperature exponent, XT I, is usually 2. Temperature appears explicitly in the value of
junction potential, U (in Ngspice PHI), for all the device models.
The temperature dependence is determined by:
kT
U (T ) =
ln
q

Na Nd
Ni (T )2

!
(1.4)

where k is Boltzmanns constant, q is the electronic charge, Na is the acceptor impurity density, Nd is the donor impurity density, Ni is the intrinsic carrier concentration, and Eg is the

42

CHAPTER 1. INTRODUCTION

energy gap. Temperature appears explicitly in the value of surface mobility, M0 (or U0 ), for the
MOSFET model.
The temperature dependence is determined by:
M0 (T0 )
M0 (T ) =  1.5

(1.5)

T
T0

The effects of temperature on resistors, capacitor and inductors is modeled by the formula:
h
i
2
R (T ) = R (T0 ) 1 + TC1 (T T0 ) + TC2 (T T0 )

(1.6)

where T is the circuit temperature, T0 is the nominal temperature, and TC1 and TC2 are the first
and second order temperature coefficients.

1.4

Convergence

Ngspice uses the Newton-Raphson algorithm to solve nonlinear equations arising from circuit
description. The NR algorithm is interactive and terminates when both of the following conditions hold:
1. The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e12 Amp), whichever is larger.
2. The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e-6 Volt),
whichever is larger.

1.4.1

Voltage convergence criterion

The algorithm has reached convergence if the difference between the last iteration k and the
current one (k + 1):


(k+1)
(k)
vn RELTOL vnmax + VNTOL
vn

(1.7)



(k+1) (k)
vnmax = max vn
, vn

(1.8)

where

The RELTOL (RELative TOLerance) parameter, which default value is 103 , specifies how small
the solution update must be, relative to the node voltage, to consider the solution to have converged. The VNTOL (absolute convergence) parameter, which has 1V as default becomes important when node voltages have near zero values. The relative parameter alone, in such case,
would need too strict tolerances, perhaps lower than computer round-off error, and thus convergence would never be achieved. VNTOL forces the algorithm to consider as converged any node
whose solution update is lower than its value.

1.4. CONVERGENCE

1.4.2

43

Current convergence criterion

Ngspice checks the convergence on the non-linear functions that describe the non-linear branches
in circuit elements. In semiconductor devices the functions defines currents through the device
and thus the name of the criterion.
Ngspice computes the difference between the value of the nonlinear function computed for last
voltage and the linear approximation of the same current computed with the actual voltage:


\

(k+1)
(k)
i

branch ibranch RELTOL ibrmax + ABSTOL

(1.9)

where
ibrmax



\
(k+1) (k)
= max ibranch , ibranch

(1.10)

In the two expressions above, the i\


branch indicates the linear approximation of the current.

1.4.3

Convergence failure

Although the algorithm used in ngspice has been found to be very reliable, in some cases it fails
to converge to a solution. When this failure occurs, the program terminates the job. Failure
to converge in dc analysis is usually due to an error in specifying circuit connections, element
values, or model parameter values. Regenerative switching circuits or circuits with positive
feedback probably will not converge in the dc analysis unless the OFF option is used for some
of the devices in the feedback path, .nodeset control line is used to force the circuit to converge
to the desired state.

44

CHAPTER 1. INTRODUCTION

Chapter 2
Circuit Description
2.1
2.1.1

General Structure and Conventions


Input file structure

The circuit to be analyzed is described to ngspice by a set of element instance lines, which
define the circuit topology and element instance values, and a set of control lines, which define
the model parameters and the run controls. All lines are assembled in an input file to be read by
ngspice. Two lines are essential:
The first line in the input file must be the title, which is the only comment line that does
not need any special character in the first place.
The last line must be .end.
The order of the remaining lines is arbitrary (except, of course, that continuation lines must
immediately follow the line being continued). This feature in the ngspice input language dates
back to the punched card times where elements were written on separate cards (and cards frequently fell off). Leading white spaces in a line are ignored, as well as empty lines.

2.1.2

Circuit elements (device instances)

Each element in the circuit is a device instance specified by an instance line that contains:
the element instance name,
the circuit nodes to which the element is connected,
and the values of the parameters that determine the electrical characteristics of the element.
The first letter of the element instance name specifies the element type. The format for the
ngspice element types is given in the following manual chapters. In the rest of the manual, the
strings XXXXXXX, YYYYYYY, and ZZZZZZZ denote arbitrary alphanumeric strings.

45

46

CHAPTER 2. CIRCUIT DESCRIPTION

For example, a resistor instance name must begin with the letter R and can contain one or more
characters. Hence, R, R1, RSE, ROUT, and R3AC2ZY are valid resistor names. Details of each
type of device are supplied in a following section 3. Table 2.1 lists the element types which are
available in ngspice, sorted by the first letter.
First letter

Element description

XSPICE code model

B
C
D

Behavioral (arbitrary) source


Capacitor
Diode

Voltage-controlled voltage source (VCVS)

Current-controlled current source (CCCs)

Voltage-controlled current source (VCCS)

H
I
J
K
L

Current-controlled voltage source (CCVS)


Current source
Junction field effect transistor (JFET)
Coupled (Mutual) Inductors
Inductor

Metal oxide field effect transistor (MOSFET)

N
O
P
Q
R
S
T
U
V
W
X
Y
Z

Numerical device for GSS


Lossy transmission line
Coupled multiconductor line (CPL)
Bipolar junction transistor (BJT)
Resistor
Switch (voltage-controlled)
Lossless transmission line
Uniformly distributed RC line
Voltage source
Switch (current-controlled)
Subcircuit
Single lossy transmission line (TXL)
Metal semiconductor field effect transistor (MESFET)

Comments, links
12
analog (12.2)
digital (12.4)
mixed signal (12.3)
5.1
3.2.5
7
linear (4.2.2),
non-linear (5.2)
linear (4.2.3)
linear (4.2.1),
non-linear (5.3)
linear (4.2.4)
4.1
9
3.2.11
3.2.9
11
BSIM3 (11.2.9)
BSIM4 (11.2.10)
14.2
6.2
6.4.2
8
3.2.1
3.2.14
6.1
6.3
4.1
3.2.14
2.4.3
6.4.1
10

Table 2.1: ngspice element types

2.1.3

Some naming conventions

Fields on a line are separated by one or more blanks, a comma, an equal (=) sign, or a left or
right parenthesis; extra spaces are ignored. A line may be continued by entering a + (plus) in
column 1 of the following line; ngspice continues reading beginning with column 2. A name

2.1. GENERAL STRUCTURE AND CONVENTIONS

47

field must begin with a letter (A through Z) and cannot contain any delimiters. A number field
may be an integer field (12, -44), a floating point field (3.14159), either an integer or floating
point number followed by an integer exponent (1e-14, 2.65e3), or either an integer or a floating
point number followed by one of the following scale factors:

Suffix
T
G
Meg
K
mil
m
u
n
p
f

Name
Tera
Giga
Mega
Kilo
Mil
milli
micro
nano
pico
femto

Factor
1012
109
106
103
25.4 106
103
106
109
1012
1015

Table 2.2: Ngspice scale factors

Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent
the same number, and M, MA, MSec, and MMhos all represent the same scale factor. Note that
1000, 1000.0, 1000Hz, 1e3, 1.0e3, 1kHz, and 1k all represent the same number. Note that M or
m denote milli, i.e. 103 . Suffix meg has to be used for 106 .
Nodes names may be arbitrary character strings and are case insensitive. The ground node
must be named 0 (zero). For compatibility reason gnd is accepted as ground node, and
will internally be treated as a global node and be converted to 0. Each circuit has to have a
ground node (gnd or 0)! Note the difference in ngspice where the nodes are treated as character
strings and not evaluated as numbers, thus 0 and 00 are distinct nodes in ngspice but not in
SPICE2.
Ngspice requires that the following topological constraints are satisfied:

The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain
a cut-set of current sources and/or capacitors.

Each node in the circuit must have a dc path to ground.

Every node must have at least two connections except for transmission line nodes (to
permit unterminated transmission lines) and MOSFET substrate nodes (which have two
internal connections anyway).

48

CHAPTER 2. CIRCUIT DESCRIPTION

2.2

Basic lines

2.2.1

.TITLE line

Examples:
POWER AMPLIFIER CIRCUIT
* additional lines following
*...
T e s t o f CAM c e l l
* additional lines following
*...
The title line must be the first in the input file. Its contents are printed verbatim as the heading
for each section of output.
As an alternative you may place a .TITLE <any title> line anywhere in your input deck.
The first line of your input deck will be overridden by the contents of this line following the
.TITLE statement.
.TITLE line example:
******************************
* additional lines following
*...
. TITLE T e s t o f CAM c e l l
* additional lines following
*...
will internally be replaced by
Internal input deck:
T e s t o f CAM
* additional
*...
* TITLE T e s t
* additional
*...

2.2.2

cell
lines following
o f CAM c e l l
lines following

.END Line

Examples:
. end
The ".End" line must always be the last in the input file. Note that the period is an integral part
of the name.

2.3. .MODEL DEVICE MODELS

2.2.3

49

Comments

General Form:
* < any comment >
Examples:
* RF=1K Gain s h o u l d be 100
* Check openl o o p g a i n and p h a s e m a r g i n
The asterisk in the first column indicates that this line is a comment line. Comment lines may
be placed anywhere in the circuit description.

2.2.4

End-of-line comments

General Form:
< any command> ; < any comment >
< any command> $ < any comment >
Examples:
RF2=1K ; Gain s h o u l d be 100
C1=10 p $ Check openl o o p g a i n and p h a s e m a r g i n
. param n1 =1 / / new v a l u e
ngspice supports comments that begin with single characters ; or double characters $ (dollar
plus space) or //. For readability you should precede each comment character with a space.
ngspice will accept the single character $, but only outside of a .control section.

2.3

.MODEL Device Models

General form:
. model mname t y p e ( pname1= p v a l 1 pname2= p v a l 2 . . . )
Examples:
. model MOD1 npn ( b f =50 i s =1e 13 v b f = 50 )
Most simple circuit elements typically require only a few parameter values. However, some devices (semiconductor devices in particular) that are included in ngspice require many parameter
values. Often, many devices in a circuit are defined by the same set of device model parameters.
For these reasons, a set of device model parameters is defined on a separate .model line and
assigned a unique model name. The device element lines in ngspice then refer to the model
name.
For these more complex device types, each device element line contains the device name, the
nodes to which the device is connected, and the device model name. In addition, other optional
parameters may be specified for some devices: geometric factors and an initial condition (see
the following section on Transistors (8 to 11) and Diodes (7) for more details). mname in the
above is the model name, and type is one of the following fifteen types:

50

CHAPTER 2. CIRCUIT DESCRIPTION


Code
R
C
L
SW
CSW
URC
LTRA
D
NPN
PNP
NJF
PJF
NMOS
PMOS
NMF
PMF

Model Type
Semiconductor resistor model
Semiconductor capacitor model
Inductor model
Voltage controlled switch
Current controlled switch
Uniform distributed RC model
Lossy transmission line model
Diode model
NPN BJT model
PNP BJT model
N-channel JFET model
P-channel JFET model
N-channel MOSFET model
P-channel MOSFET model
N-channel MESFET model
P-channel MESFET model

Table 2.3: Ngspice model types

Parameter values are defined by appending the parameter name followed by an equal sign and
the parameter value. Model parameters that are not given a value are assigned the default values
given below for each model type. Models are listed in the section on each device along with
the description of device element lines. Model parameters and their default values are given in
chapter 31.

2.4

.SUBCKT Subcircuits

A subcircuit that consists of ngspice elements can be defined and referenced in a fashion similar
to device models. Subcircuits are the way ngspice implements hierarchical modeling, but this is
not entirely true because each subcircuit instance is flattened during parsing, and thus ngspice
is not a hierarchical simulator.
The subcircuit is defined in the input deck by a grouping of element cards delimited by the
.subckt and the .ends cards (or the keywords defined by the substart and subend options
(see 17.7)); the program then automatically inserts the defined group of elements wherever the
subcircuit is referenced. Instances of subcircuits within a larger circuit are defined through the
use of an instance card which begins with the letter X. A complete example of all three of
these cards follows:

2.4. .SUBCKT SUBCIRCUITS

51

Example:
* The following is the instance card :
*
xdiv1 10 7 0 vdivide
* The following are the subcircuit definition cards :
*
. subckt vdivide 1 2 3
r1 1 2 10 K
r2 2 3 5 K
. ends

The above specifies a subcircuit with ports numbered 1, 2 and 3:


Resistor R1 is connected from port 1 to port 2, and has value 10 kOhms.
Resistor R2 is connected from port 2 to port 3, and has value 5 kOhms.
The instance card, when placed in an ngspice deck, will cause subcircuit port 1 to be equated
to circuit node 10, while port 2 will be equated to node 7 and port 3 will equated to
node 0.
There is no limit on the size or complexity of subcircuits, and subcircuits may contain other
subcircuits. An example of subcircuit usage is given in chapter 21.6.

2.4.1

.SUBCKT Line

General form:
. SUBCKT subnam N1 <N2 N3 . . . >
Examples:
. SUBCKT OPAMP 1 2 3 4
A circuit definition is begun with a .SUBCKT line. SUBNAM is the subcircuit name, and N1, N2,
... are the external nodes, which cannot be zero. The group of element lines which immediately
follow the .SUBCKT line define the subcircuit. The last line in a subcircuit definition is the
.ENDS line (see below). Control lines may not appear within a subcircuit definition; however,
subcircuit definitions may contain anything else, including other subcircuit definitions, device
models, and subcircuit calls (see below). Note that any device models or subcircuit definitions
included as part of a subcircuit definition are strictly local (i.e., such models and definitions
are not known outside the subcircuit definition). Also, any element nodes not included on the
.SUBCKT line are strictly local, with the exception of 0 (ground) which is always global. If you
use parameters, the .SUBCKT line will be extended (see 2.8.3).

52

2.4.2

CHAPTER 2. CIRCUIT DESCRIPTION

.ENDS Line

General form:
. ENDS <SUBNAM>
Examples:
. ENDS OPAMP
The .ENDS line must be the last one for any subcircuit definition. The subcircuit name, if
included, indicates which subcircuit definition is being terminated; if omitted, all subcircuits
being defined are terminated. The name is needed only when nested subcircuit definitions are
being made.

2.4.3

Subcircuit Calls

General form:
XYYYYYYY N1 <N2 N3 . . . > SUBNAM
Examples:
X1 2 4 17 3 1 MULTI
Subcircuits are used in ngspice by specifying pseudo-elements beginning with the letter X,
followed by the circuit nodes to be used in expanding the subcircuit. If you use parameters, the
subcircuit call will be modified (see 2.8.3).

2.5

.GLOBAL

General form:
. GLOBAL nodename
Examples:
. GLOBAL gnd v c c
Nodes defined in the .GLOBAL statement are available to all circuit and subcircuit blocks independently from any circuit hierarchy. After parsing the circuit, these nodes are accessible from
top level.

2.6

.INCLUDE

General form:
. INCLUDE f i l e n a m e
Examples:
. INCLUDE / u s e r s / s p i c e / common / bsim3param . mod

2.7. .LIB

53

Frequently, portions of circuit descriptions will be reused in several input files, particularly with
common models and subcircuits. In any ngspice input file, the .INCLUDE line may be used to
copy some other file as if that second file appeared in place of the .INCLUDE line in the original
file.
There is no restriction on the file name imposed by ngspice beyond those imposed by the local
operating system.

2.7

.LIB

General form:
. LIB f i l e n a m e l i b n a m e
Examples:
. LIB / u s e r s / s p i c e / common / m o s f e t s . l i b mos1
The .LIB statement allows to include library descriptions into the input file. Inside the *.lib
file a library libname will be selected. The statements of each library inside the *.lib file are
enclosed in .LIB libname <...> .ENDL statements.
If the compatibility mode (16.13) is set to ps by set ngbehavior=ps (17.7) in spinit (16.5)
or .spiceinit (16.6), then a simplified syntax .LIB filename is available: a warning is issued
and filename is simply included as described in chapt. 2.6.

2.8

.PARAM Parametric netlists

Ngspice allows for the definition of parametric attributes in the netlists. This is an enhancement
of the ngspice front-end which adds arithmetic functionality to the circuit description language.

2.8.1

.param line

General form:
. param < i d e n t > = < e x p r >

< i d e n t > = <expr > . . . .

Examples:
. param
. param
. param
. param
. param

p i p p o =5
po =6 pp = 7 . 8 pap ={AGAUSS( p i p p o , 1 , 1 . 6 7 ) }
p i p p p ={ p i p p o + pp }
p ={ pp }
pop = pp+p

This line assigns numerical values to identifiers. More than one assignment per line is possible
using a space as separator. Parameter identifier names must begin with an alphabetic character.
The other characters must be either alphabetic, a number, or ! # $ % [ ] _ as special characters. The variables time, temper, and hertz (see 5.1.1) are no valid identifier names. Other
restrictions on naming conventions apply as well, see 2.8.6.

54

CHAPTER 2. CIRCUIT DESCRIPTION

The .param lines inside subcircuits are copied per call, like any other line. All assignments are
executed sequentially through the expanded circuit. Before its first use, a parameter name must
have been assigned a value. Expression defining a parameter have to be put into braces {p+p2},
alternatively into single quotes AGAUSS(pippo, 1, 1.67).

2.8.2

Brace expressions in circuit elements:

General form:
{ <expr > }
Examples:
These are allowed in .model lines and in device lines. A spice number is a floating point
number with an optional scaling suffix, immediately glued to the numeric tokens (see chapt.
2.8.5). Brace expressions ({..}) cannot be used to parametrize node names or parts of names.
All identifiers used within an <expr> must have known values at the time when the line is
evaluated, else an error is flagged.

2.8.3

Subcircuit parameters

General form:
. s u b c k t < i d e n t n > node node . . .

< i d e n t >=< v a l u e > < i d e n t >=< v a l u e > . . .

Examples:
. s u b c k t m y f i l t e r i n o u t r v a l =100 k c v a l =100 nF
<identn> is the name of the subcircuit given by the user. node is an integer number or an
identifier, for one of the external nodes. The first <ident>=<value> introduces an optional
section of the line. Each <ident> is a formal parameter, and each <value> is either a spice
number or a brace expression. Inside the .subckt ... .ends context, each formal parameter
may be used like any identifier that was defined on a .param control line. The <value> parts
are supposed to be default values of the parameters. However, in the current version of , they
are not used and each invocation of the subcircuit must supply the _exact_ number of actual
parameters.
The syntax of a subcircuit call (invocation) is:
General form:
X<name> node node . . . < i d e n t n > < i d e n t >=< v a l u e > < i d e n t >=< v a l u e > . . .
Examples:
X1 i n p u t o u t p u t m y f i l t e r r v a l =1k c v a l =1n
Here <name> is the symbolic name given to that instance of the subcircuit, <identn> is the
name of a subcircuit defined beforehand. node node ... is the list of actual nodes where the
subcircuit is connected. <value> is either a spice number or a brace expression { <expr> } .
The sequence of <value> items on the X line must exactly match the number and the order of
formal parameters of the subcircuit.

2.8. .PARAM PARAMETRIC NETLISTS

55

Subcircuit example with parameters:


* Parame x a m p l e
. param a m p l i t u d e = 1V
*
. s u b c k t m y f i l t e r i n o u t r v a l =100 k c v a l =100 nF
Ra i n p1
{2 * r v a l }
Rb p1 o u t {2 * r v a l }
C1 p1 0
{2 * c v a l }
Ca i n p2
{ cval }
Cb p2 o u t { c v a l }
R1 p2 0
{ rval }
. ends m y f i l t e r
*
X1 i n p u t o u t p u t m y f i l t e r r v a l =1k c v a l =1n
V1 i n p u t 0 AC { a m p l i t u d e }
. end

2.8.4

Symbol scope

All subcircuit and model names are considered global and must be unique. The .param symbols
that are defined outside of any .subckt ... .ends section are global. Inside such a section,
the pertaining params: symbols and any .param assignments are considered local: they
mask any global identical names, until the .ends line is encountered. You cannot reassign to a
global number inside a .subckt, a local copy is created instead. Scope nesting works up to a
level of 10. For example, if the main circuit calls A which has a formal parameter xx, A calls
B which has a param. xx, and B calls C which also has a formal param. xx, there will be three
versions of xx in the symbol table but only the most local one - belonging to C - is visible.
A word of caution: Ngspice allows to define circuits with nested subcircuits. Currently it is
not possible however to issue .param statements inside of a .subckt ... .ends section, when there
are additional, nested .subckt ... .ends in the same section. This is a bug, which will be removed
asap.

2.8.5

Syntax of expressions

<expr> ( optional parts within [ ...] ):


An expression may be one of:
<atom > where <atom > i s e i t h e r a s p i c e number o r an i d e n t i f i e r
< u n a r y o p e r a t o r > <atom >
< f u n c t i o n name> ( < e x p r > [ , < e x p r > . . . ] )
<atom > < b i n a r y o p e r a t o r > < e x p r >
( <expr > )
As expected, atoms, built-in function calls and stuff within parentheses are evaluated before
the other operators. The operators are evaluated following a list of precedence close to the one

56

CHAPTER 2. CIRCUIT DESCRIPTION

of the C language. For equal precedence binary ops, evaluation goes left to right. Functions
operate on real values only!

Operator
not
**
*
/
mod
div
+
==
<>
<=
>=
<
>
and
or

Alias
!
^

%
\

!=

&&
||

Precedence
1
1
2
3
3
3
3
4
4
5
5
5
5
5
5
6
7

Description
unary unary not
power, like pwr
multiply
divide
modulo
integer divide
add
subtract
equality
non-equal
less or equal
greater or equal
less than
greater than
and
or

The result of logical operators is 1 or 0 , for True or False. An example input file is shown
below:

Example input file with logical operators:


* Logical operators
. param symd = 9
v1or
1 0 {1 o r 0}
v1and 2 0 {1 and 0}
v1not 3 0 { not (1)}
v1mod 4 0 {5 mod 3}
v 1 d i v 5 0 {5 d i v 3}
v0not 6 0 { not (0)}
v d e f i n e d 7 0 { d e f i n e d ( symb ) }
v d e f i n e d 2 8 0 { d e f i n e d ( symd ) }
. control
op
print allv
. endc
. end

2.8. .PARAM PARAMETRIC NETLISTS


Built-in function
defined(symbol)
sqr(x)
sqrt(x)
sin(x), cos(x), tan(x)
sinh(x), cosh(x), tanh(x)
asin(x), acos(x), atan(x)
asinh(x), acosh(x), atanh(x)
arctan(x)
exp(x)
ln(x), log(x)
abs(x)
floor(x), int(x)
ceil(x)
pow(x,y)
pwr(x,y)
min(x, y)
max(x, y)
sgn(x)
ternary_fcn(x, y, z)
gauss(nom, rvar, sigma)

agauss(nom, avar, sigma)

unif(nom, rvar)
aunif(nom, avar)
limit(nom, avar)

57

Notes
returns 1 if symbol is defined, else 0
y=x*x
y = sqrt(x)

atan(x), kept for compatibility

Largest integer that is less than or equal to x


Smallest integer that is greater than or equal to x
x raised to the power of y (pow from C runtime library)
pow(fabs(x), y)

1.0 for x > 0, 0.0 for x == 0, -1.0 for x < 0


x?y:z
nominal value plus variation drawn from Gaussian
distribution with mean 0 and standard deviation rvar
(relative to nominal), divided by sigma
nominal value plus variation drawn from Gaussian
distribution with mean 0 and standard deviation avar
(absolute), divided by sigma
nominal value plus relative variation (to nominal)
uniformly distributed between +/-rvar
nominal value plus absolute variation uniformly distributed
between +/-avar
nominal value +/-avar, depending on random number in
[-1, 1[ being > 0 or < 0

The scaling suffixes (any decorative alphanumeric string may follow):


suffix
g
meg
k
m
u
n
p
f

value
1e9
1e6
1e3
1e-3
1e-6
1e-9
1e-12
1e-15

Note: there are intentional redundancies in expression syntax, e.g. x^y , x**y and pwr(x,y) all
have nearly the same result.

58

2.8.6

CHAPTER 2. CIRCUIT DESCRIPTION

Reserved words

In addition to the above function names and to the verbose operators ( not and or div mod ),
other words are reserved and cannot be used as parameter names: and, or, not, div, mod, defined,
sqr, sqrt, sin, cos, exp, ln, arctan, abs, pwr, time, temper, hertz.

2.8.7

Alternative syntax

The & sign is tolerated to provide some historical parameter notation: & as the first character
of a line is equivalent to: .param.
Inside a line, the notation &(....) is equivalent to {....}, and &identifier means the same
thing as {identifier} .
Comments in the style of C++ line trailers (//) are detected and erased.
Warning: this is NOT possible in embedded .control parts of a source file, these lines are outside
of this scope.
Now, there is some possible confusion in ngspice because of multiple numerical expression
features. The .param lines and the braces expressions (see next chapter 2.9) are evaluated in
the front-end, that is, just after the subcircuit expansion. (Technically, the X lines are kept as
comments in the expanded circuit so that the actual parameters can correctly be substituted).
So, after the netlist expansion and before the internal data setup, all number attributes in the
circuit are known constants. However, there are some circuit elements in Spice which accept
arithmetic expressions that are NOT evaluated at this point, but only later during circuit analysis.
These are the arbitrary current and voltage sources (B-sources, 5), as well as E- and G-sources
and R-, L-, or C-devices. The syntactic difference is that "compile-time" expressions are within
braces, but "run-time" expressions have no braces. To make things more complicated, the backend ngspice scripting language also accepts arithmetic/logic expressions that operate on its own
scalar or vector data sets (17.2). Please see also chapt. 2.13.
It would be desirable to have the same expression syntax, operator and function set, and precedence rules, for the three contexts mentioned above. In the current Numparam implementation,
that goal is not yet achieved...

2.9

.FUNC

With this line a function may be defined. The syntax of its expression is equivalent to the
expression syntax from the .param line (2.8.5).
General form:
. func < i d e n t > { <expr > }
Examples:
. f u n c i c o s ( x ) { c o s ( x ) 1}
. func f ( x , y ) {x*y}
.func will initiate a replacement operation. After reading the input files, and before parameters
are evaluated, all occurrences of the icos(x) function will be replaced by cos(x)-1. All

2.10. .CSPARAM

59

occurrences of f(x,y) will be replaced by x*y. Function statements may be nested to a depth
of t.b.d..

2.10

.CSPARAM

Create a constant vector (see 17.8.2) from a parameter in plot (17.3) const.
General form:
. csparam < i d e n t > = <expr >
Examples:
. param p i p p o =5
. param pp =6
. c s p a r a m p i p p p ={ p i p p o + pp }
. param p ={ pp }
. c s p a r a m pap = pp+p
In the example shown, vectors pippp, and pap are added to the constants, which already reside
in plot const, with length one and real values. These vectors are generated during circuit
parsing and thus cannot be changed later (same as with ordinary parameters). They may be
used in ngspice scripts and .control sections (see chapt. 17).
The use of .csparam is still experimental and has to be tested. A simple usage is shown below.

* test csparam
.param TEMPS = 27
.csparam newt = {3*TEMPS}
.csparam mytemp = 2 + TEMPS
.control
echo $&newt $&mytemp
.endc
.end

2.11

.TEMP

Sets the circuit temperature in degrees Celsius.


General form:
. temp v a l u e
Examples:
. temp 27
This card overrides the circuit temperature given in an .option line (15.1.1).

60

2.12

CHAPTER 2. CIRCUIT DESCRIPTION

.IF Condition-Controlled Netlist

A simple IF-ELSE block allows condition-controlling of the netlist. boolean expression is


any expression according to chapt. 2.8.5 which evaluates parameters and returns a boolean 1
or 0. The netlist block in between the .if ... .endif statements may contain device instances or
.model cards which are selected according to the logic condition.

General form:
. i f ( boolean expression )
...
. e l s e i f ( boolean expression )
...
. endif
Example 1:
* d e v i c e i n s t a n c e i n IFELSE b l o c k
. param ok =0 ok2 =1
v1 1 0 1
R1 1 0 2
. i f ( ok && ok2 )
R11 1 0 2
. else
R11 1 0 0 . 5
; < s e l e c t e d
. endif
Example 2:
* . model i n IFELSE b l o c k
. param m0=0 m1=1
M1 1 2 3 4 N1 W=1 L = 0 . 5
. i f ( m0==1)
. model N1 NMOS l e v e l =49 V e r s i o n = 3 . 1
. e l s e i f ( m1==1)
. model N1 NMOS l e v e l =49 V e r s i o n = 3 . 2 . 4
. else
. model N1 NMOS l e v e l =49 V e r s i o n = 3 . 3 . 0
. endif

; < s e l e c t e d

For now this is a very restricted version of an IF-ELSE block, so several netlist components are
currently not supported within the IF-ELSE block: .SUBCKT, .INC, .LIB, .PARAM. Nesting
of IF-ELSE blocks is not possible. Only one .elseif is allowed per block.

2.13. PARAMETERS, FUNCTIONS, EXPRESSIONS, AND COMMAND SCRIPTS

2.13

61

Parameters, functions, expressions, and command scripts

In ngspice there are several ways to describe functional dependencies. In fact there are three
independent function parsers, being active before, during, and after the simulation. So it might
be due to have a few words on their interdependence.

2.13.1

Parameters

Parameters (chapt. 2.8.1) and functions, either defined within the .param statement or with
the .func statement (chapt. 2.9) are evaluated before any simulation is started, that is during
the setup of the input and the circuit. Therefore these statements may not contain any simulation output (voltage or current vectors), because it is simply not yet available. The syntax is
described in chapt. 2.8.5. During the circuit setup all functions are evaluated, all parameters are
replaced by their resulting numerical values. Thus it will not be possible to get feedback from
a later stage (during or after simulation) to change any of the parameters.

2.13.2

Nonlinear sources

During the simulation, the B source (chapt. 5) and their associated E and G sources, as well
as some devices (R, C, L) may contain expressions. These expressions may contain parameters
from above (evaluated immediately upon ngspice start up), numerical data, predefined functions, but also node voltages and branch currents which are resulting from the simulation. The
source or device values are continuously updated during the simulation. Therefore the sources
are powerful tools to define non-linear behavior, you may even create new devices by yourself.
Unfortunately the expression syntax (see chapt. 5.1) and the predefined functions may deviate
from the ones for parameters listed in 2.8.1.

2.13.3

Control commands, Command scripts

Commands, as described in detail in chapt. 17.5, may be used interactively, but also as a command script enclosed in .control ... .endc lines. The scripts may contain expressions
(see chapt. 17.2). The expressions may work upon simulation output vectors (of node voltages, branch currents), as well as upon predefined or user defined vectors and variables, and are
invoked after the simulation. Parameters from 2.8.1 defined by the .param statement are not
allowed in these expressions. However you may define such parameters with .csparam (2.10).
Again the expression syntax (see chapt. 17.2) will deviate from the one for parameters or B
sources listed in 2.8.1 and 5.1.
If you want to use parameters from 2.8.1 inside your control script, you may use .csparam
(2.10) or apply a trick by defining a voltage source with the parameter as its value, and then
have it available as a vector (e.g. after a transient simulation) with a then constant output (the
parameter). A feedback from here back into parameters (2.13.1) is never possible. Also you
cannot access non-linear sources of the preceding simulation. However you may start a first
simulation inside your control script, then evaluate its output using expressions, change some
of the element or model parameters with the alter and altermod statements (see chapt. 17.5.3)
and then automatically start a new simulation.

62

CHAPTER 2. CIRCUIT DESCRIPTION

Expressions and scripting are powerful tools within ngspice, and we will enhance the examples
given in chapt. 21 continuously to describe these features.

Chapter 3
Circuit Elements and Models
Data fields that are enclosed in less-than and greater-than signs (< >) are optional. All indicated punctuation (parentheses, equal signs, etc.) is optional but indicate the presence of any
delimiter. Further, future implementations may require the punctuation as stated. A consistent style adhering to the punctuation shown here makes the input easier to understand. With
respect to branch voltages and currents, ngspice uniformly uses the associated reference convention (current flows in the direction of voltage drop).

3.1
3.1.1

General options and information


Simulating more devices in parallel

If you need to simulate more devices of the same kind in parallel, you can use the m (often
called parallel multiplier) option which is available for all instances except transmission lines
and sources (both independent and controlled). The parallel multiplier is implemented by multiplying the value of m the elements matrix stamp, thus it cannot be used to accurately simulate
larger devices in integrated circuits. The netlist below show how to correctly use the parallel
multiplier:
Multiple device example:
d1 2 0 mydiode m=10
d01 1 0 mydiode
d02 1 0 mydiode
d03 1 0 mydiode
d04 1 0 mydiode
d05 1 0 mydiode
d06 1 0 mydiode
d07 1 0 mydiode
d08 1 0 mydiode
d09 1 0 mydiode
d10 1 0 mydiode
...
The d1 instance connected between nodes 2 and 0 is equivalent to the parallel d01-d10 connected between 1 and 0.

63

64

3.1.2

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

Technology scaling

Still to be implemented and written.

3.1.3

Model binning

Binning is a kind of range partitioning for geometry dependent models like MOSFETs. The
purpose is to cover larger geometry ranges (Width and Length) with higher accuracy then the
model built-in geometry formulas. Each size range described by the additional model parameters LMIN, LMAX, WMIN and WMAX has its own model parameter set. These model cards
are defined by a number extension, like nch.1. NGSPICE has a algorithm to choose the right
model card by the requested W and L.
This is implemented for BSIM3 (11.2.9) and BSIM4 (11.2.10) models.

3.1.4

Multiplier m, initial conditions

The area factor m (often called parallel multiplier) used on the diode, BJT, JFET, and MESFET devices determines the number of equivalent parallel devices of a specified model. The
affected parameters are marked with an asterisk under the heading area in the model descriptions (see the various chapters on models below). Several geometric factors associated with the
channel and the drain and source diffusions can be specified on the MOSFET device line.
Two different forms of initial conditions may be specified for some devices. The first form
is included to improve the dc convergence for circuits that contain more than one stable state.
If a device is specified OFF, the dc operating point is determined with the terminal voltages
for that device set to zero. After convergence is obtained, the program continues to iterate to
obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state,
the OFF option can be used to force the solution to correspond to a desired state. If a device
is specified OFF when in reality the device is conducting, the program still obtains the correct
solution (assuming the solutions converge) but more iterations are required since the program
must independently converge to two separate solutions.
The .NODESET control line (see chapt. 15.2.1) serves a similar purpose as the OFF option. The
.NODESET option is easier to apply and is the preferred means to aid convergence. The second
form of initial conditions are specified for use with the transient analysis. These are true initial
conditions as opposed to the convergence aids above. See the description of the .IC control
line (chapt. 15.2.2) and the .TRAN control line (chapt. 15.3.9) for a detailed explanation of
initial conditions.

3.2. ELEMENTARY DEVICES

3.2

65

Elementary Devices

3.2.1

Resistors

General form:
RXXXXXXX n+ n v a l u e < a c = v a l > <m= v a l > < s c a l e = v a l > <temp= v a l >
+ <dtemp = v a l > < t c 1 = v a l > < t c 2 = v a l > < n o i s y =0|1 >
Examples:
R1 1 2
RC1 12
R2 5 7
RL 1 4

100
17 1K
1K a c =2K
2K m=2

Ngspice has a fairly complex model for resistors. It can simulate both discrete and semiconductor resistors. Semiconductor resistors in ngspice means: resistors described by geometrical
parameters. So, do not expect detailed modeling of semiconductor effects.
n+ and n- are the two element nodes, value is the resistance (in ohms) and may be positive or
negative1 but not zero.
Simulating small valued resistors: If you need to simulate very small resistors (0.001 Ohm or less), you should use CCVS (transresistance), it is less
efficient but improves overall numerical accuracy. Think about that a small
resistance is a large conductance.
Ngspice can assign a resistor instance a different value for AC analysis, specified using the ac
keyword. This value must not be zero as described above. The AC resistance is used in AC
analysis only (not Pole-Zero nor noise). If you do not specify the ac parameter, it is defaulted
to value. If you want to simulate temperature dependence of a resistor, you need to specify its
temperature coefficients, using a .model line, like in the example below:
Example:
RE1 1 2 800 n e w r e s dtemp =5
.MODEL n e w r e s R t c 1 = 0 . 0 0 1
The temperature coefficients tc1 and tc2 describe a quadratic temperature dependence (see
equation17.12) of the resistance. If given in the instance line (the R... line) their values will
override the tc1 and tc2 of the .model line (3.2.3). Instance temperature is useful even if
resistance does not vary with it, since the thermal noise generated by a resistor depends on its
absolute temperature. Resistors in ngspice generates two different noises: thermal and flicker.
While thermal noise is always generated in the resistor, to add a flicker noise2 source you have
to add a .model card defining the flicker noise parameters. It is possible to simulate resistors
that do not generate any kind of noise using the noisy keyword and assigning zero to it, as in
the following example:
Example:
Rmd 134 57 1 . 5 k n o i s y =0
1A

negative resistor modeling an active element can cause convergence problems, please avoid it.
noise can be used to model carbon resistors.

2 Flicker

66

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

Ngspice calculates the nominal resistance as described below:


Rnom =
Racnom =

VALUEscale
m
acscale
m

(3.1)

If you are interested in temperature effects or noise equations, read the next section on semiconductor resistors.

3.2.2

Semiconductor Resistors

General form:
RXXXXXXX n+ n < v a l u e > <mname> < l = l e n g t h > <w= w i d t h > <temp= v a l >
+ <dtemp = v a l > <m= v a l > < a c = v a l > < s c a l e = v a l > < n o i s y = 0 | 1 >
Examples:
RLOAD 2 10 10K
RMOD 3 7 RMODEL L=10 u W=1u
This is the more general form of the resistor presented before (3.2.1) and allows the modeling of
temperature effects and for the calculation of the actual resistance value from strictly geometric
information and the specifications of the process. If value is specified, it overrides the geometric information and defines the resistance. If mname is specified, then the resistance may be
calculated from the process information in the model mname and the given length and width.
If value is not specified, then mname and length must be specified. If width is not specified,
then it is taken from the default width given in the model.
The (optional) temp value is the temperature at which this device is to operate, and overrides
the temperature specification on the .option control line and the value specified in dtemp.

3.2.3

Semiconductor Resistor Model (R)

The resistor model consists of process-related device data that allow the resistance to be calculated from geometric information and to be corrected for temperature. The parameters available
are:
Name
Parameter
Units Default Example
/C
TC1
first order temperature coeff.
0.0

TC2
second order temperature coeff.
/C
0.0
/
RSH
sheet resistance
50
DEFW
default width
m
1e-6
2e-6
NARROW
narrowing due to side etching
m
0.0
1e-7
SHORT
shortening due to side etching
m
0.0
1e-7

TNOM
parameter measurement temperature
C
27
50
KF
flicker noise coefficient
0.0
1e-25
AF
flicker noise exponent
0.0
1.0
R (RES) default value if element value not given
W
1000
The sheet resistance is used with the narrowing parameter and l and w from the resistor device
to determine the nominal resistance by the formula:

3.2. ELEMENTARY DEVICES

67

Rnom = rsh

l SHORT
w NARROW

(3.2)

DEFW is used to supply a default value for w if one is not specified for the device. If either rsh
or l is not specified, then the standard default resistance value of 1 mOhm is used. TNOM is used
to override the circuit-wide value given on the .options control line where the parameters
of this model have been measured at a different temperature. After the nominal resistance is
calculated, it is adjusted for temperature by the formula:



R(T ) = R(TNOM) 1 + TC1 (T TNOM) + TC2 (T TNOM)2

(3.3)

where R(TNOM) = Rnom |Racnom . In the above formula, T represents the instance temperature, which can be explicitly set using the temp keyword or calculated using the circuit temperature and dtemp, if present. If both temp and dtemp are specified, the latter is ignored.
Ngspice improves spices resistors noise model, adding flicker noise (1/ f ) to it and the noisy
keyword to simulate noiseless resistors. The thermal noise in resistors is modeled according to
the equation:

4kT
f
i2R =
R

(3.4)

where "k" is the Boltzmanns constant, and "T " the instance temperature.
Flicker noise model is:

i2Rf n =

KFIRAF
f
f

(3.5)

A small list of sheet resistances (in /) for conductors is shown below. The table represents
typical values for MOS processes in the 0.5 - 1 um
range. The table is taken from: N. Weste, K. Eshraghian - Principles of CMOS VLSI Design
2nd Edition, Addison Wesley.
Material
Inter-metal (metal1 - metal2)
Top-metal (metal3)
Polysilicon (poly)
Silicide
Diffusion (n+, p+)
Silicided diffusion
n-well

Min.
0.005
0.003
15
2
10
2
1000

Typ.
0.007
0.004
20
3
25
4
2000

Max.
0.1
0.05
30
6
100
10
5000

68

3.2.4

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

Resistors, dependent on expressions (behavioral resistor)

General form:
RXXXXXXX n+ n R = e x p r e s s i o n < t c 1 = v a l u e > < t c 2 = v a l u e >
RXXXXXXX n+ n e x p r e s s i o n < t c 1 = v a l u e > < t c 2 = v a l u e >
Examples:
R1 r r 0 r = V( r r ) < { Vt } ? {R0} : {2 * R0 } t c 1 =2e 03 t c 2 = 3 . 3 e 06
R2 r 2 r r r = {5 k + 50 *TEMPER}
Expression may be an equation or an expression containing node voltages or branch currents
(in the form of i(vm)) and any other terms as given for the B source and described in chapter
5.1. It may contain parameters (2.8.1) and the special variables time, temper, and hertz (5.1.2).
An example file is given below.
Example input file for non-linear resistor:
Nonl i n e a r r e s i s t o r
. param R0=1k Vi =1 Vt = 0 . 5
* r e s i s t o r d e p e n d i n g on c o n t r o l v o l t a g e V( r r )
R1 r r 0 r = V( r r ) < { Vt } ? {R0} : {2 * R0 }
* control voltage
V1 r r 0 PWL( 0 0 100 u { Vi } )
. control
set noaskquit
t r a n 100 n 100 u u i c
p l o t i ( V1 )
. endc
. end

3.2.5

Capacitors

General form:
CXXXXXXX n+ n < v a l u e > <mname> <m= v a l > < s c a l e = v a l > <temp= v a l >
+ <dtemp = v a l > < t c 1 = v a l > < t c 2 = v a l > < i c = i n i t _ c o n d i t i o n >
Examples:
CBYP 13 0 1UF
COSC 17 23 10U IC =3V
Ngspice provides a detailed model for capacitors. Capacitors in the netlist can be specified
giving their capacitance or their geometrical and physical characteristics. Following the original
SPICE3 "convention", capacitors specified by their geometrical or physical characteristics are
called "semiconductor capacitors" and are described in the next section.
In this first form n+ and n- are the positive and negative element nodes, respectively and value
is the capacitance in Farads.
Capacitance can be specified in the instance line as in the examples above or in a .model line,
as in the example below:

3.2. ELEMENTARY DEVICES

69

C1 15 5 c s t d
C2 2 7 c s t d
. model c s t d C c a p =3n
Both capacitors have a capacitance of 3nF.
If you want to simulate temperature dependence of a capacitor, you need to specify its temperature coefficients, using a .model line, like in the example below:
CEB 1 2 1u c a p 1 dtemp =5
.MODEL c a p 1 C t c 1 = 0 . 0 0 1
The (optional) initial condition is the initial (time zero) value of capacitor voltage (in Volts).
Note that the initial conditions (if any) apply only if the uic option is specified on the .tran
control line.
Ngspice calculates the nominal capacitance as described below:
Cnom = value scale m

(3.6)

The temperature coefficients tc1 and tc2 describe a quadratic temperature dependence (see
equation17.12) of the capacitance. If given in the instance line (the C... line) their values will
override the tc1 and tc2 of the .model line (3.2.7).

3.2.6

Semiconductor Capacitors

General form:
CXXXXXXX n+ n < v a l u e > <mname> < l = l e n g t h > <w= w i d t h > <m= v a l >
+ < s c a l e = v a l > <temp= v a l > <dtemp = v a l > < i c = i n i t _ c o n d i t i o n >
Examples:
CLOAD 2 10 10P
CMOD 3 7 CMODEL L=10 u W=1u
This is the more general form of the Capacitor presented in section (3.2.5), and allows for the
calculation of the actual capacitance value from strictly geometric information and the specifications of the process. If value is specified, it defines the capacitance and both process and
geometrical information are discarded. If value is not specified, the capacitance is calculated
from information contained model mname and the given length and width (l, w keywords, respectively).
It is possible to specify mname only, without geometrical dimensions and set the capacitance in
the .model line (3.2.5).

3.2.7

Semiconductor Capacitor Model (C)

The capacitor model contains process information that may be used to compute the capacitance
from strictly geometric information.

70

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

Name
CAP
CJ
CJSW
DEFW
DEFL
NARROW
SHORT
TC1
TC2
TNOM
DI
THICK

Parameter
model capacitance
junction bottom capacitance
junction sidewall capacitance
default device width
default device length
narrowing due to side etching
shortening due to side etching
first order temperature coeff.
second order temperature coeff.
parameter measurement temperature
relative dielectric constant
insulator thickness

Units
F
F/m2
F/m
m
m
m
m
F/C
F/C2
C
F/m
m

Default
0.0
1e-6
0.0
0.0
0.0
0.0
0.0
27
0.0

Example
1e-6
5e-5
2e-11
2e-6
1e-6
1e-7
1e-7
0.001
0.0001
50
1
1e-9

The capacitor has a capacitance computed as:


If value is specified on the instance line then
Cnom = value scale m

(3.7)

If model capacitance is specified then


Cnom = CAP scale m

(3.8)

If neither value nor CAP are specified, then geometrical and physical parameters are take into
account:

C0 = CJ(l SHORT)(w NARROW) + 2CJSW(l SHORT + w NARROW)

(3.9)

CJ can be explicitly given on the .model line or calculated by physical parameters. When CJ is
not given, is calculated as:
If THICK is not zero:
CJ =
CJ =

DI0
THICK
SiO2
THICK

if DI is specified,
otherwise.

(3.10)

If the relative dielectric constant is not specified the one for SiO2 is used. The values of the
F
F
constants are: 0 = 8.854214871e 12 m
and SiO2 = 3.4531479969e 11 m
. The nominal
capacitance is then computed as:
Cnom = C0 scale m

(3.11)

After the nominal capacitance is calculated, it is adjusted for temperature by the formula:


C(T ) = C(TNOM) 1 + TC1 (T TNOM) + TC2 (T TNOM)2

(3.12)

3.2. ELEMENTARY DEVICES

71

where C(TNOM) = Cnom .


In the above formula, T represents the instance temperature, which can be explicitly set using
the temp keyword or calculated using the circuit temperature and dtemp, if present.

3.2.8

Capacitors, dependent on expressions (behavioral capacitor)

General form:
CXXXXXXX n+ n C = e x p r e s s i o n < t c 1 = v a l u e > < t c 2 = v a l u e >
CXXXXXXX n+ n e x p r e s s i o n < t c 1 = v a l u e > < t c 2 = v a l u e >
Examples:
C1 c c 0 c = V( c c ) < { Vt } ? {C1} : {Ch } t c 1 =1e 03 t c 2 = 1 . 3 e 05
Expression may be an equation or an expression containing node voltages or branch currents
(in the form of i(vm)) and any other terms as given for the B source and described in chapter
5.1. It may contain parameters (2.8.1) and the special variables time, temper, and hertz (5.1.2).
Example input file:
Behavioral Capacitor
. param Cl =5n Ch=1n Vt =1m I l =100 n
. i c v ( cc ) = 0
v ( cc2 ) = 0
* c a p a c i t o r d e p e n d i n g on c o n t r o l v o l t a g e V( c c )
C1 c c 0 c = V( c c ) < { Vt } ? { Cl } : {Ch }
* C1 c c 0 c ={Ch}
I1 0 1 { I l }
Exxx n1copy n2 n2 c c 2 1
Cxxx n1copy n2 1
Bxxx c c 2 n2 I = (V( c c 2 ) < { Vt } ? { Cl } : {Ch } ) * i ( Exxx )
I 2 n2 22 { I l }
vn2 n2 0 DC 0
* m e a s u r e c h a r g e by i n t e g r a t i n g c u r r e n t
a i n t 1 %i d ( 1 c c ) 2 t i m e _ c o u n t
a i n t 2 %i d ( 2 2 c c 2 ) 3 t i m e _ c o u n t
. model t i m e _ c o u n t i n t ( i n _ o f f s e t = 0 . 0 g a i n = 1 . 0
+ o u t _ l o w e r _ l i m i t =1e12 o u t _ u p p e r _ l i m i t =1 e12
+ l i m i t _ r a n g e =1e9 o u t _ i c = 0 . 0 )
. control
set noaskquit
t r a n 100 n 100 u
plot v (2)
p l o t v ( cc ) v ( cc2 )
. endc
. end

72

3.2.9

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

Inductors

General form:
LYYYYYYY n+ n < v a l u e > <mname> < n t = v a l > <m= v a l > < s c a l e = v a l > <temp= v a l >
+ <dtemp = v a l > < t c 1 = v a l > < t c 2 = v a l > <m= v a l > < i c = i n i t _ c o n d i t i o n >
Examples:
LLINK 42 69 1UH
LSHUNT 23 51 10U IC = 1 5 . 7MA
The inductor device implemented into ngspice has many enhancements over the original one.n+
and n- are the positive and negative element nodes, respectively. value is the inductance in
Henry. Inductance can be specified in the instance line as in the examples above or in a .model
line, as in the example below:

L1 15 5 indmod1
L2 2 7 indmod1
. model indmod1 L i n d =3n
Both inductors have an inductance of 3nH.
The nt is used in conjunction with a .model line, and is used to specify the number of turns
of the inductor. If you want to simulate temperature dependence of an inductor, you need to
specify its temperature coefficients, using a .model line, like in the example below:

L l o a d 1 2 1u i n d 1 dtemp =5
.MODEL i n d 1 L t c 1 = 0 . 0 0 1
The (optional) initial condition is the initial (time zero) value of inductor current (in Amps) that
flows from n+, through the inductor, to n-. Note that the initial conditions (if any) apply only if
the UIC option is specified on the .tran analysis line.
Ngspice calculates the nominal inductance as described below:

Lnom =

3.2.10

value scale
m

(3.13)

Inductor model

The inductor model contains physical and geometrical information that may be used to compute
the inductance of some common topologies like solenoids and toroids, wound in air or other
material with constant magnetic permeability.

3.2. ELEMENTARY DEVICES


Name
IND
CSECT
LENGTH
TC1
TC2
TNOM
NT
MU

73

Parameter
model inductance
cross section
length
first order temperature coeff.
second order temperature coeff.
parameter measurement temperature
number of turns
relative magnetic permeability

Units
H
m2
m
H/C
H/C2
C
H/m

Default
0.0
0.0
0.0
0.0
0.0
27
0.0
0.0

Example
1e-3
1e-3
1e-2
0.001
0.0001
50
10
-

The inductor has an inductance computed as:


If value is specified on the instance line then
Lnom =

value scale
m

(3.14)

Lnom =

IND scale
m

(3.15)

If model inductance is specified then

If neither value nor IND are specified, then geometrical and physical parameters are take into
account. In the following formulas
NT refers to both instance and model parameter (instance parameter overrides model parameter):
If LENGTH is not zero:
(
Lnom =
Lnom =

MU0 NT2 CSECT


LENGTH
0 NT2 CSECT
LENGTH

if MU is specified,

(3.16)

otherwise.

with:0 = 1.25663706143592e 6 H
m . After the nominal inductance is calculated, it is adjusted
for temperature by the formula:


2
L(T ) = L(TNOM) 1 + TC1 (T TNOM) + TC2 (T TNOM)

(3.17)

where L(TNOM) = Lnom . In the above formula, T represents the instance temperature, which
can be explicitly using the temp keyword or calculated using the circuit temperature and dtemp,
if present.

3.2.11

Coupled (Mutual) Inductors

General form:
KXXXXXXX LYYYYYYY LZZZZZZZ v a l u e
Examples:
K43 LAA LBB 0 . 9 9 9
KXFRMR L1 L2 0 . 8 7

74

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and value is the
coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the
dot convention, place a dot on the first node of each inductor.

3.2.12

Inductors, dependent on expressions (behavioral inductor)

General form:
LXXXXXXX n+ n L = e x p r e s s i o n < t c 1 = v a l u e > < t c 2 = v a l u e >
LXXXXXXX n+ n e x p r e s s i o n < t c 1 = v a l u e > < t c 2 = v a l u e >
Examples:
L1 l 2 l l l L = i (Vm) < { I t } ? { L l } : {Lh } t c 1 =4e 03 t c 2 =6e 05

Expression may be an equation or an expression containing node voltages or branch currents


(in the form of i(vm)) and any other terms as given for the B source and described in chapter
5.1. It may contain parameters (2.8.1) and the special variables time, temper, and hertz (5.1.2).

3.2. ELEMENTARY DEVICES

75

Example input file:


Variable inductor
. param L l = 0 . 5m Lh=5m I t =50 u Vi =2m
. ic v( int21 ) = 0
* v a r i a b l e i n d u c t o r d e p e n d i n g on c o n t r o l c u r r e n t i (Vm)
L1 l 2 l l l L = i (Vm) < { I t } ? { L l } : {Lh }
* measure c u r r e n t through i n d u c t o r
vm l l l 0 dc 0
* v o l t a g e on i n d u c t o r
V1 l 2 0 { Vi }
* fixed inductor
L3 33 331 { L l }
* measure c u r r e n t through i n d u c t o r
vm33 331 0 dc 0
* v o l t a g e on i n d u c t o r
V3 33 0 { Vi }
* non l i n e a r i n d u c t o r ( d i s c r e t e s e t u p )
F21 i n t 2 1 0 B21 1
L21 i n t 2 1 0 1
B21 n1 n2 V = ( i ( Vm21 ) < { I t } ? { L l } : {Lh } ) * v ( i n t 2 1 )
* measure c u r r e n t through i n d u c t o r
vm21 n2 0 dc 0
V21 n1 0 { Vi }
. control
set noaskquit
t r a n 1 u 100 u u i c
p l o t i (Vm) i ( vm33 )
p l o t i ( vm21 ) i ( vm33 )
p l o t i ( vm) i ( vm21 )
. endc
. end

3.2.13

Capacitor or inductor with initial conditions

The simulator supports the specification of voltage and current initial conditions on capacitor
and inductor models, respectively. These models are not the standard ones supplied with
SPICE3, but are in fact code models which can be substituted for the SPICE models when
realistic initial conditions are required. For details please refer to chapt. 12. A XSPICE deck
example using these models is shown below:
*
* This circuit contains a capacitor and an inductor with
* initial conditions on them. Each of the components

76

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

* has a parallel resistor so that an exponential decay


* of the initial condition occurs with a time constant of
* 1 second.
*
a1 1 0 cap
.model cap capacitor (c=1000uf ic=1)
r1 1 0 1k
*
a2 2 0 ind
.model ind inductor (l=1H ic=1)
r2 2 0 1.0
*
.control
tran 0.01 3
plot v(1) v(2)
.endc
.end

3.2.14

Switches

Two types of switches are available: a voltage controlled switch (type SXXXXXX, model SW)
and a current controlled switch (type WXXXXXXX, model CSW). A switching hysteresis may
be defined, as well as on- and off-resistances (0 < R < ).
General form:
SXXXXXXX N+ N NC+ NC MODEL <ON><OFF>
WYYYYYYY N+ N VNAM MODEL <ON><OFF>
Examples:
s 1 1 2 3 4 s w i t c h 1 ON
s 2 5 6 3 0 sm2 o f f
S w i t c h 1 1 2 10 0 s m o d e l 1
w1 1 2 v c l o c k s w i t c h m o d 1
W2 3 0 vramp sm1 ON
w r e s e t 5 6 v c l c k l o s s y s w i t c h OFF
Nodes 1 and 2 are the nodes between which the switch terminals are connected. The model
name is mandatory while the initial conditions are optional. For the voltage controlled switch,
nodes 3 and 4 are the positive and negative controlling nodes respectively. For the current
controlled switch, the controlling current is that through the specified voltage source. The
direction of positive controlling current flow is from the positive node, through the source, to
the negative node.
The instance parameters ON or OFF are required, when the controlling voltage (current) starts
inside the range of the hysteresis loop (different outputs during forward vs. backward voltage
or current ramp). Then ON or OFF determine the initial state of the switch.

3.2. ELEMENTARY DEVICES

3.2.15

77

Switch Model (SW/CSW)

The switch model allows an almost ideal switch to be described in ngspice. The switch is not
quite ideal, in that the resistance can not change from 0 to infinity, but must always have a finite
positive value. By proper selection of the on and off resistances, they can be effectively zero
and infinity in comparison to other circuit elements. The parameters available are:
Name
VT
IT
VH
IH
RON
ROFF

Parameter
threshold voltage
threshold current
hysteresis voltage
hysteresis current
on resistance
off resistance

Units
V
A
V
A

Default
0.0
0.0
0.0
0.0
1.0
1.0e+12 (*)

Switch model
SW
CSW
SW
CSW
SW,CSW
SW,CSW

(*) Or 1/GMIN, if you have set GMIN to any other value, see the .OPTIONS control line
(15.1.2) for a description of GMIN, its default value results in an off-resistance of 1.0e+12
ohms.
The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to occur in the circuit node voltages. A rapid change such as that associated with a switch
changing state can cause numerical round-off or tolerance problems leading to erroneous results
or time step difficulties. The user of switches can improve the situation by taking the following
steps:

First, it is wise to set ideal switch impedances just high or low enough to be negligible
with respect to other circuit elements. Using switch impedances that are close to "ideal"
in all cases aggravates the problem of discontinuities mentioned above. Of course, when
modeling real devices such as MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the device being modeled.

If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON


>1e+12), then the tolerance on errors allowed during transient analysis should be decreased by using the .OPTIONS control line and specifying TRTOL to be less than the
default value of 7.0.

When switches are placed around capacitors, then the option CHGTOL should also be reduced. Suggested values for these two options are 1.0 and 1e-16 respectively. These
changes inform ngspice to be more careful around the switch points so that no errors are
made due to the rapid change in the circuit.

78

CHAPTER 3. CIRCUIT ELEMENTS AND MODELS

Example input file:


Switch t e s t
. t r a n 2 u s 5ms
* switch control voltage
v1 1 0 DC 0 . 0 PWL( 0 0 2 e3 2 4 e3 0 )
* s w i t c h c o n t r o l v o l t a g e s t a r t i n g i n s i d e h y s t e r e s i s window
* p l e a s e n o t e i n f l u e n c e o f i n s t a n c e p a r a m e t e r s ON, OFF
v2 2 0 DC 0 . 0 PWL( 0 0 . 9 2 e3 2 4 e3 0 . 4 )
* switch control current
i 3 3 0 DC 0 . 0 PWL( 0 0 2 e3 2m 4 e3 0 ) $ < s w i t c h c o n t r o l c u r r e n t
* load voltage
v4 4 0 DC 2 . 0
* input load for current source i3
r 3 3 33 10 k
vm3 33 0 dc 0 $ < m e a s u r e t h e c u r r e n t
* ouput load r e s i s t o r s
r 1 0 4 10 10 k
r 2 0 4 20 10 k
r 3 0 4 30 10 k
r 4 0 4 40 10 k
*
s 1 10 0 1 0 s w i t c h 1 OFF
s 2 20 0 2 0 s w i t c h 1 OFF
s 3 30 0 2 0 s w i t c h 1 ON
. model s w i t c h 1 sw v t =1 vh = 0 . 2 r o n =1 r o f f =10 k
*
w1 40 0 vm3 w s w i t c h 1 o f f
. model w s w i t c h 1 csw i t =1m i h = 0 . 2m r o n =1 r o f f =10 k
*
. control
run
plot v (1) v (10)
p l o t v ( 1 0 ) v s v ( 1 ) $ < g e t h y s t e r e s i s l o o p
p l o t v ( 2 ) v ( 2 0 ) $ < d i f f e r e n t i n i t i a l v a l u e s
p l o t v ( 2 0 ) v s v ( 2 ) $ < g e t h y s t e r e s i s l o o p
p l o t v ( 2 ) v ( 3 0 ) $ < d i f f e r e n t i n i t i a l v a l u e s
p l o t v ( 3 0 ) v s v ( 2 ) $ < g e t h y s t e r e s i s l o o p
p l o t v ( 4 0 ) v s vm3# b r a n c h $ < c u r r e n t c o n t r o l l e d s w i t c h h y s t e r e s i s
. endc
. end

Chapter 4
Voltage and Current Sources
4.1

Independent Sources for Voltage or Current

General form:
VXXXXXXX N+ N <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
IYYYYYYY N+ N <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
+ <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
Examples:
VCC 10 0 DC 6
VIN 13 2 0 . 0 0 1 AC 1 SIN ( 0 1 1MEG)
ISRC 23 21 AC 0 . 3 3 3 4 5 . 0 SFFM( 0 1 10K 5 1K)
VMEAS 12 9
VCARRIER 1 0 DISTOF1 0 . 1 90.0
VMODULATOR 2 0 DISTOF2 0 . 0 1
I I N 1 1 5 AC 1 DISTOF1 DISTOF2 0 . 0 0 1
n+ and n- are the positive and negative nodes, respectively. Note that voltage sources need not
be grounded. Positive current is assumed to flow from the positive node, through the source, to
the negative node. A current source of positive value forces current to flow out of the n+ node,
through the source, and into the n- node. Voltage sources, in addition to being used for circuit
excitation, are the ammeters for ngspice, that is, zero valued voltage sources may be inserted
into the circuit for the purpose of measuring current. They of course have no effect on circuit
operation since they represent short-circuits.
DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for
dc and transient analyses, this value may be omitted. If the source value is time-invariant (e.g.,
a power supply), then the value may optionally be preceded by the letters DC.
ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to this value in the
ac analysis. If ACMAG is omitted following the keyword AC, a value of unity is assumed. If
ACPHASE is omitted, a value of zero is assumed. If the source is not an ac small-signal input,
the keyword AC and the ac values are omitted.
DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion
inputs at the frequencies F1 and F2 respectively (see the description of the .DISTO control line).

79

80

CHAPTER 4. VOLTAGE AND CURRENT SOURCES

The keywords may be followed by an optional magnitude and phase. The default values of the
magnitude and phase are 1.0 and 0.0 respectively.
Any independent source can be assigned a time-dependent value for transient analysis. If a
source is assigned a time-dependent value, the time-zero value is used for dc analysis. There
are nine independent source functions:
pulse,
exponential,
sinusoidal,
piece-wise linear,
single-frequency FM
AM
transient noise
random voltages or currents
and external data (only with ngspice shared library).
If parameters other than source values are omitted or set to zero, the default values shown are
assumed. (TSTEP is the printing increment and TSTOP is the final time (see the .TRAN control
line for explanation)).

4.1.1

Pulse

General form:
PULSE ( V1 V2 TD TR TF PW PER )
Examples:
VIN 3 0 PULSE(1 1 2NS 2NS 2NS 50NS 100NS )
Name
V1
V2
TD
TR
TF
PW
PER

Parameter
Initial value
Pulsed value
Delay time
Rise time
Fall time
Pulse width
Period

Default Value
0.0
TSTEP
TSTEP
TSTOP
TSTOP

Units
V, A
V, A
sec
sec
sec
sec
sec

A single pulse so specified is described by the following table:

4.1. INDEPENDENT SOURCES FOR VOLTAGE OR CURRENT


Time
0
TD
TD+TR
TD+TR+PW
TD+TR+PW+TF
TSTOP

81

Value
V1
V1
V2
V2
V1
V1

Intermediate points are determined by linear interpolation.

4.1.2

Sinusoidal

General form:
SIN (VO VA FREQ TD THETA)
Examples:
VIN 3 0 SIN ( 0 1 100MEG 1NS 1E10 )
Name
VO
VA
FREQ
TD
THETA

Parameter
Offset
Amplitude
Frequency
Delay
Damping factor

Default Value
1/T ST OP
0.0
0.0

Units
V, A
V, A
Hz
sec
1/sec

The shape of the waveform is described by the following formula:


(
V0
if 0 t < T D
V (t) =
(tT
D)T
HETA
V 0 +VAe
sin (2FREQ (t T D)) if T D t < T ST OP

4.1.3

Exponential

General Form:
EXP ( V1 V2 TD1 TAU1 TD2 TAU2 )
Examples:
VIN 3 0 EXP(4 1 2NS 30NS 60NS 40NS )
Name
V1
V2
TD1
TAU1
TD2
TAU2

Parameter
Initial value
pulsed value
rise delay time
rise time constant
fall delay time
fall time constant

Default Value
0.0
TSTEP
TD1+TSTEP
TSTEP

Units
V, A
V, A
sec
sec
sec
sec

The shape of the waveform is described by the following formula:

(4.1)

82

CHAPTER 4. VOLTAGE AND CURRENT SOURCES

Let V 21 = V 2 V 1 V 12 = V 1 V 2:

V1
if 0 t < T D1,




(tT D1)
TAU1
if T D1 t < T D2,
V (t) = V 1 +V 21 1 e





(tT D1)
(tT D2)

V 1 +V 21 1 e TAU1 +V 12 1 e TAU2
if T D2 t < T ST OP.

4.1.4

(4.2)

Piece-Wise Linear

General Form:
PWL( T1 V1 <T2 V2 T3 V3 T4 V4 . . . > ) < r = v a l u e > < t d = v a l u e >
Examples:
VCLOCK 7 5 PWL( 0 7 10NS 7 11NS 3 17NS 3 18NS 7 50NS 7) r =0 t d =15NS
Each pair of values (Ti , Vi ) specifies that the value of the source is Vi (in Volts or Amps) at
time = Ti . The value of the source at intermediate values of time is determined by using linear
interpolation on the input values. The parameter r determines a repeat time point. If r is not
given, the whole sequence of values (Ti , Vi ) is issued once, then the output stays at its final
value. If r = 0, the whole sequence from time = 0 to time = Tn is repeated forever. If r = 10ns,
the sequence between 10ns and 50ns is repeated forever. the r value has to be one of the time
points T1 to Tn of the PWL sequence. If td is given, the whole PWL sequence is delayed by a
delay time time = td. The current source still needs to be patched, td and r are not yet available.

4.1.5

Single-Frequency FM

General Form:
SFFM (VO VA FC MDI FS )
Examples:
V1 12 0 SFFM( 0 1M 20K 5 1K)
Name
VO
VA
FC
MDI
FS

Parameter
Offset
Amplitude
Carrier frequency
Modulation index
Signal frequency

Default value
1/T ST OP
1/T ST OP

Units
V, A
V, A
Hz
Hz

The shape of the waveform is described by the following equation:

V (t) = VO +VA sin (2FCt + MDI sin (2FSt))

(4.3)

4.1. INDEPENDENT SOURCES FOR VOLTAGE OR CURRENT

4.1.6

83

Amplitude modulated source (AM)

General Form:
AM(VA VO MF FC TD)
Examples:
V1 12 0 AM( 0 . 5 1 20K 5MEG 1m)
Name
VA
VO
MF
FC
TD

Parameter
Amplitude
Offset
Modulating frequency
Carrier frequency
Signal delay

Default value
1/T ST OP
-

Units
V, A
V, A
Hz
Hz
s

The shape of the waveform is described by the following equation:


V (t) = VA (VO + sin (2MFt)) sin (2FCt)

4.1.7

(4.4)

Transient noise source

General Form:
TRNOISE (NA NT NALPHA NAMP RTSAM RTSCAPT RTSEMT)
Examples:
VNoiw 1 0 DC 0 TRNOISE ( 2 0 n 0 . 5 n 0 0 )
VNoi1of 1 0 DC 0 TRNOISE ( 0 10 p 1 . 1 12 p )
VNoiw1of 1 0 DC 0 TRNOISE ( 2 0 10 p 1 . 1 12 p )
IALL 10 0 DC 0 t r n o i s e ( 1m 1u 1 . 0 0 . 1m 15m

$ white
$ 1/ f
$ w h i t e and 1 / f
22 u 50 u ) $ w h i t e , 1 / f , RTS

Transient noise is an experimental feature allowing (low frequency) transient noise injection and
analysis. See chapter 15.3.10 for a detailed description. NA is the Gaussian noise rms voltage
amplitude, NT is the time between sample values (breakpoints will be enforced on multiples of
this value). NALPHA (exponent to the frequency dependency), NAMP (rms voltage or current
amplitude) are the parameters for 1/f noise, RTSAM the random telegraph signal amplitude,
RTSCAPT the mean of the exponential distribution of the trap capture time, and RTSEMT
its emission time mean. White Gaussian, 1/f, and RTS noise may be combined into a single
statement.
Name
NA
NT
NALPHA
NAMP
RTSAM
RTSCAPT
RTSEMT

Parameter
Rms noise amplitude (Gaussian)
Time step
1/f exponent
Amplitude (1/f)
Amplitude
Trap capture time
Trap emission time

Default value
0< <2
-

Units
V, A
sec
V, A
V, A
sec
sec

84

CHAPTER 4. VOLTAGE AND CURRENT SOURCES

If you set NT and RTSAM to 0, the noise option TRNOISE ... is ignored. Thus you may switch
off the noise contribution of an individual voltage source VNOI by the command
alter @vnoi[trnoise] = [ 0 0 0 0 ] $ no noise
alter @vrts[trnoise] = [ 0 0 0 0 0 0 0] $ no noise
See chapt. 17.5.3 for the alter command.
You may switch off all TRNOISE noise sources by setting
set notrnoise
to your .spiceinit file (for all your simulations) or into your control section in front of the next
run or tran command (for this specific and all following simulations). The command
unset notrnoise
will reinstate all noise sources.
The noise generators are implemented into the independent voltage (vsrc) and current (isrc)
sources.

4.1.8

Random voltage source

The TRRANDOM option yields statistically distributed voltage values, derived from the ngspice
random number generator. These values may be used in the transient simulation directly within
a circuit, e.g. for generating a specific noise voltage, but especially they may be used in the control of behavioral sources (B, E, G sources 5, voltage controllable A sources 12, capacitors 3.2.8,
inductors 3.2.12, or resistors 3.2.4) to simulate the circuit dependence on statistically varying
device parameters. A Monte-Carlo simulation may thus be handled in a single simulation run.
General Form:
TRRANDOM( TYPE TS <TD <PARAM1 <PARAM2> > >)
Examples:
VR1 r 1

0 dc 0 t r r a n d o m ( 2 10m 0 1 ) $ G a u s s i a n

TYPE determines the random variates generated: 1 is uniformly distributed, 2 Gaussian, 3


exponential, 4 Poisson. TS is the duration of an individual voltage value. TD is a time delay
with 0 V output before the random voltage values start up. PARAM1 and PARAM2 depend on
the type selected.
TYPE
1
2
3
4

4.1.9

description
Uniform
Gaussian
Exponential
Poisson

PARAM1
Range
Standard Dev.
Mean
Lambda

default
1
1
1
1

External voltage or current input

General Form:
EXTERNAL

PARAM2
Offset
Mean
Offset
Offset

default
0
0
0
0

4.2. LINEAR DEPENDENT SOURCES

85

Examples:
Vex 1 0 dc 0 e x t e r n a l
I e x i 1 i 2 dc 0 e x t e r n a l <m = xx >
Voltages or currents may be set from the calling process, if ngspice is compiled as a shared
library and loaded by the process. See chapt 19.6.3 for an explanation.

4.1.10

Arbitrary Phase Sources

The XSPICE option supports arbitrary phase independent sources that output at TIME=0.0 a
value corresponding to some specified phase shift. Other versions of SPICE use the TD (delay
time) parameter to set phase-shifted sources to their time-zero value until the delay time has
elapsed. The XSPICE phase parameter is specified in degrees and is included after the SPICE3
parameters normally used to specify an independent source. Partial XSPICE deck examples of
usage for pulse and sine waveforms are shown below:
* Phase shift is specified after Berkeley defined parameters
* on the independent source cards. Phase shift for both of the
* following is specified as +45 degrees
*
v1 1 0 0.0 sin(0 1 1k 0 0 45.0)
r1 1 0 1k
*
v2 2 0 0.0 pulse(-1 1 0 1e-5 1e-5 5e-4 1e-3 45.0)
r2 2 0 1k
*

4.2

Linear Dependent Sources

Ngspice allows circuits to contain linear dependent sources characterized by any of the four
equations
i = gv

v = ev

i = fi

v = hi

where g, e, f , and h are constants representing transconductance, voltage gain, current gain,
and transresistance, respectively. Non-linear dependent sources for voltages or currents (B, E,
G) are described in chapter 5.

4.2.1

Gxxxx: Linear Voltage-Controlled Current Sources (VCCS)

General form:
GXXXXXXX N+ N NC+ NC VALUE <m= v a l >
Examples:
G1 2 0 5 0 0 . 1

86

CHAPTER 4. VOLTAGE AND CURRENT SOURCES

n+ and n- are the positive and negative nodes, respectively. Current flow is from the positive
node, through the source, to the negative
node. nc+ and nc- are the positive and negative controlling nodes, respectively. value is the
transconductance (in mhos). m is an optional multiplier to the output current. val may be a
numerical value or an expression according to 2.8.5 containing references to other parameters.

4.2.2

Exxxx: Linear Voltage-Controlled Voltage Sources (VCVS)

General form:
EXXXXXXX N+ N NC+ NC VALUE
Examples:
E1 2 3 14 1 2 . 0
n+ is the positive node, and n- is the negative node. nc+ and nc- are the positive and negative
controlling nodes, respectively. value is the voltage gain.

4.2.3

Fxxxx: Linear Current-Controlled Current Sources (CCCS)

General form:
FXXXXXXX N+ N VNAM VALUE <m= v a l >
Examples:
F1 13 5 VSENS 5 m=2
n+ and n- are the positive and negative nodes, respectively. Current flow is from the positive
node, through the source, to the negative node. vnam is the name of a voltage source through
which the controlling current flows. The direction of positive controlling current flow is from
the positive node, through the source, to the negative node of vnam. value is the current gain.
m is an optional multiplier to the output current.

4.2.4

Hxxxx: Linear Current-Controlled Voltage Sources (CCVS)

General form:
HXXXXXXX n+ n vnam v a l u e
Examples:
HX 5 17 VZ 0 . 5K
n+ and n- are the positive and negative nodes, respectively. vnam is the name of a voltage source
through which the controlling current flows. The direction of positive controlling current flow
is from the positive node, through the source, to the negative node of vnam. value is the
transresistance (in ohms).

4.2. LINEAR DEPENDENT SOURCES

4.2.5

87

Polynomial Source Compatibility

Dependent polynomial sources available in SPICE2G6 are fully supported in ngspice using the
XSPICE extension (25.1). The form used to specify these sources is shown in Table 4.1. For
details on its usage please see chapter 5.2.4.

Source Type
POLYNOMIAL VCVS
POLYNOMIAL VCCS
POLYNOMIAL CCCS
POLYNOMIAL CCVS

Dependent Polynomial Sources


Instance Card
EXXXXXXX N+ N- POLY(ND) NC1+ NC1- P0 (P1...)
GXXXXXXX N+ N- POLY(ND) NC1+ NC1- P0 (P1...)
FXXXXXXX N+ N- POLY(ND) VNAM1 !VNAM2...? P0 (P1...)
HXXXXXXX N+ N- POLY(ND) VNAM1 !VNAM2...? P0 (P1...)
Table 4.1: Dependent Polynomial Sources

88

CHAPTER 4. VOLTAGE AND CURRENT SOURCES

Chapter 5
Non-linear Dependent Sources (Behavioral
Sources)
The non-linear dependent sources B ( see chapt. 5.1), E (see 5.2), G see (5.3) described in
this chapter allow to generate voltages or currents which result from evaluating a mathematical
expression. Internally E and G sources are converted to the more general B source. All three
sources may be used to introduce behavioral modeling and analysis.

5.1

Bxxxx: Nonlinear dependent source (ASRC)

5.1.1

Syntax and usage

General form:
BXXXXXXX n+ n < i = e x p r > <v= e x p r > < t c 1 = v a l u e > < t c 2 = v a l u e >
+ <temp= v a l u e > <dtemp = v a l u e >
Examples:
B1
B2
B3
B4
B5

0
0
3
3
2

1
1
4
4
0

I =cos ( v ( 1 ) ) + s i n ( v ( 2 ) )
V= l n ( c o s ( l o g ( v ( 1 , 2 ) ^ 2 ) ) ) v ( 3 ) ^ 4 + v ( 2 ) ^ v ( 1 )
I =17
V= exp ( p i ^ i ( vdd ) )
V = V( 1 ) < {Vlow} ? {Vlow} : V( 1 ) > { Vhigh } ? { Vhigh } : V( 1 )

n+ is the positive node, and n- is the negative node. The values of the V and I parameters
determine the voltages and currents across and through the device, respectively. If I is given
then the device is a current source, and if V is given the device is a voltage source. One and only
one of these parameters must be given.
A simple model is implemented for temperature behavior by the formula:


I(T ) = I(TNOM) 1 + TC1 (T TNOM) + TC2 (T TNOM)2
or

89

(5.1)

90

CHAPTER 5. NON-LINEAR DEPENDENT SOURCES (BEHAVIORAL SOURCES)



V (T ) = V (TNOM) 1 + TC1 (T TNOM) + TC2 (T TNOM)2

(5.2)

In the above formula, T represents the instance temperature, which can be explicitly set using
the temp keyword or calculated using the circuit temperature and dtemp, if present. If both
temp and dtemp are specified, the latter is ignored.
The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources)
with a proportionality constant equal to the derivative (or derivatives) of the source at the DC
operating point. The expressions given for V and I may be any function of voltages and currents
through voltage sources in the system.
The following functions of a single real variable are defined:
Trigonometric functions: cos, sin, tan, acos, asin, atan
Hyperbolic functions: cosh, sinh, acosh, asinh, atanh
Exponential and logarithmic: exp, ln, log
Other: abs, sqrt, u, u2, uramp, floor, ceil
Functions of two variables are: min, max, pow
Functions of three variables are: a ? b:c
The function u is the unit step function, with a value of one for arguments greater than zero
and a value of zero for arguments less than zero. The function u2 returns a value of zero
for arguments less than zero, one for arguments greater than one and assumes the value of the
argument between these limits. The function "uramp" is the integral of the unit step: for an
input x, the value is zero if x is less than zero, or if x is greater than zero the value is x. These
three functions are useful in synthesizing piece-wise non-linear functions, though convergence
may be adversely affected.
The following standard operators are defined: +, -, *, /, ^, unary Logical operators are !=, <>, >=, <=, ==, >, <, ||, &&, ! .
A ternary function is defined as a ? b : c , which means IF a, THEN b, ELSE c. Be
sure to place a space in front of ? to allow the parser distinguishing it from other tokens.
Example: Ternary function
* B s o u r c e t e s t Clamped v o l t a g e s o u r c e
* C . P . B a s s o " S w i t c h e d mode power s u p p l i e s " , New York , 2008
. param Vhigh = 4 . 6
. param Vlow = 0 . 4
Vin1 1 0 DC 0 PWL( 0 0 1u 5 )
B c l 2 0 V = V( 1 ) < Vlow ? Vlow : V( 1 ) > Vhigh ? Vhigh : V( 1 )
. control
set noaskquit
t r a n 5 n 1u
p l o t V( 2 ) v s V( 1 )
. endc
. end

5.1. BXXXX: NONLINEAR DEPENDENT SOURCE (ASRC)

91

If the argument of log, ln, or sqrt becomes less than zero, the absolute value of the argument is
used. If a divisor becomes zero or the argument of log or ln becomes zero, an error will result.
Other problems may occur when the argument for a function in a partial derivative enters a
region where that function is undefined.
Parameters may be used like {Vlow} shown in the example above. Parameters will be evaluated
upon set up of the circuit, vectors like V(1) will be evaluated during the simulation.
To get time into the expression you can integrate the current from a constant current source
with a capacitor and use the resulting voltage (dont forget to set the initial voltage across the
capacitor).
Non-linear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent
source. Nonlinear resistors, capacitors and inductors are implemented with their linear counterparts by a change of variables implemented with the nonlinear dependent source. The following
subcircuit will implement a nonlinear capacitor:
Example: Non linear capacitor
. S u b c k t n l c a p p o s neg
* Bx : c a l c u l a t e f ( i n p u t v o l t a g e )
Bx 1 0 v = f ( v ( pos , neg ) )
* Cx : l i n e a r c a p a c i t a n c e
Cx 2 0 1
* Vx : Ammeter t o m e a s u r e c u r r e n t i n t o t h e c a p a c i t o r
Vx 2 1 DC 0 V o l t s
* D r i v e t h e c u r r e n t t h r o u g h Cx b a c k i n t o t h e c i r c u i t
Fx p o s neg Vx 1
. ends
Example for f(v(pos,neg)):
Bx 1 0 V = v ( pos , neg ) * v ( pos , neg )
Non-linear resistors or inductors may be described in a similar manner. An example for a
nonlinear resistor using this template is shown below.
Example: Non linear resistor
* use of hertz v a r i a b l e in n o n l i n e a r r e s i s t o r
* . param r b a s e =1k
* some t e s t s
B1 1 0 V = h e r t z * v ( 3 3 )
B2 2 0 V = v ( 3 3 ) * h e r t z
b3 3 0 V = 6 . 2 8 3 e3 / ( h e r t z + 6 . 2 8 3 e3 ) * v ( 3 3 )
V1 33 0 DC 0 AC 1
*** T r a n s l a t e R1 10 0 R= 1 k / s q r t (HERTZ) t o B s o u r c e ***
. S u b c k t n l r e s p o s neg r b = r b a s e
* Bx : c a l c u l a t e f ( i n p u t v o l t a g e )
Bx
1
0
v = 1 / { r b } / s q r t (HERTZ) * v ( pos , neg )
* Rx : l i n e a r r e s i s t a n c e
Rx
2
0
1

92

CHAPTER 5. NON-LINEAR DEPENDENT SOURCES (BEHAVIORAL SOURCES)

Example: Non linear resistor (continued)


* Vx : Ammeter t o m e a s u r e c u r r e n t i n t o t h e r e s i s t o r
Vx
2
1
DC 0 V o l t s
* D r i v e t h e c u r r e n t t h r o u g h Rx b a c k i n t o t h e c i r c u i t
Fx
p o s neg Vx 1
. ends
X r e s 33 10 n l r e s r b =1k
* R r e s 33 10 1k
V r e s 10 0 DC 0
. control
d e f i n e c h e c k ( a , b ) vecmax ( a b s ( a b ) )
a c l i n 10 100 1k
* some c h e c k s
print v (1) v (2) v (3)
i f c h e c k ( v ( 1 ) , f r e q u e n c y ) < 1 e 12
e c h o " INFO : ok "
end
p l o t vres # branch
. endc
. end

5.1.2

Special B-Source Variables time, temper, hertz

The special variables time and temper are available in a transient analysis, reflecting the
actual simulation time and circuit temperature. temper returns the circuit temperature, given
in degree C (see 2.11). The variable hertz is available in an AC analysis. time is zero in
the AC analysis, hertz is zero during transient analysis. Using the variable hertz may cost
some CPU time if you have a large circuit, because for each frequency the operating point has
to be determined before calculating the AC response.

5.1.3

par(expression)

The B source syntax may also be used in output lines like .plot as algebraic expressions for
output (see chapt.15.5.6 ).

5.1.4

Piecewise Linear Function: pwl

Both B source types may contain a piece-wise linear dependency of one network variable:
Example: pwl_current
Bdio 1 0 I = pwl ( v (A) , 0 , 0 , 3 3 , 1 0m, 1 0 0 , 3 3m, 2 0 0 , 5 0m)
v(A) is the independent variable x. Each pair of values following describes the x,y functional
relation: In this example at node A voltage of 0V the current of 0A is generated - next pair gives
10mA flowing from ground to node 1 at 33V on node A and so forth.
The same is possible for voltage sources:

5.1. BXXXX: NONLINEAR DEPENDENT SOURCE (ASRC)

93

Example: pwl_voltage
B l i m i t b 0 V = pwl ( v ( 1 ) , 4 ,0 , 2 ,2 , 2 , 4 , 4 , 5 , 6 , 5 )

Monotony of the independent variable in the pwl definition is checked - non-monotonic x entries
will stop the program execution. v(1) may be replaced by a controlling current source. v(1) may
also be replaced by an expression, e.g. -2*i(Vin). The value pairs may also be parameters, which
have to be defined before by a .param statement. An example for the pwl function using all of
these options is shown below:

94

CHAPTER 5. NON-LINEAR DEPENDENT SOURCES (BEHAVIORAL SOURCES)

Example: pwl function in B source


D e m o n s t r a t e s u s a g e o f t h e pwl f u n c t i o n i n an B s o u r c e (ASRC)
* A l s o e m u l a t e s t h e TABLE f u n c t i o n w i t h l i m i t s
. param
. param
. param
. param
. param
. param

x0=4 y0 =0
x1=2 y1 =2
x2 =2 y2=2
x3 =4 y3 =1
xx0=x01
xx3=x3 +1

Vin
1 0
R 1 0 2

DC=0V

* no l i m i t s o u t s i d e o f t h e t a b u l a t e d x v a l u e s ( c o n t i n u e s l i n e a r i l y )
Btest2 2 0
I = pwl ( v ( 1 ) , x0 , y0 , x1 , y1 , x2 , y2 , x3 , y3 )
* l i k e TABLE f u n c t i o n w i t h l i m i t s :
Btest3 3 0
I = ( v ( 1 ) < x0 ) ? y0 : ( v ( 1 ) < x3 ) ?
+ pwl ( v ( 1 ) , x0 , y0 , x1 , y1 , x2 , y2 , x3 , y3 ) : y3
* more e f f i c i e n t and e l e g a n t TABLE f u n c t i o n w i t h l i m i t s
*( voltage c o n t r o l l e d ) :
Btest4 4 0
I = pwl ( v ( 1 ) ,
+ xx0 , y0 , x0 , y0 ,
+
x1 , y1 ,
+
x2 , y2 ,
+
x3 , y3 , xx3 , y3 )
*
* more e f f i c i e n t and e l e g a n t TABLE f u n c t i o n w i t h l i m i t s
* ( c o n t r o l l e d by c u r r e n t ) :
Btest5 5 0
I = pwl (2 * i ( Vin ) ,
+ xx0 , y0 , x0 , y0 ,
+
x1 , y1 ,
+
x2 , y2 ,
+
x3 , y3 , xx3 , y3 )
Rint2 2 0 1
Rint3 3 0 1
Rint4 4 0 1
Rint5 5 0 1
. control
dc Vin 6 6 0 . 2
p l o t v ( 2 ) v ( 3 ) v (4) 0.5 v ( 5 ) + 0 . 5
. endc
. end

5.2. EXXXX: NON-LINEAR VOLTAGE SOURCE*

5.2
5.2.1

95

Exxxx: non-linear voltage source*


VOL

General form:
EXXXXXXX n+ n v o l = e x p r
Examples:
E41 4 0 v o l = V( 3 ) * V(3) O f f s
Expression may be an equation or an expression containing node voltages or branch currents
(in the form of i(vm)) and any other terms as given for the B source and described in chapter
5.1. It may contain parameters (2.8.1) and the special variables time, temper, hertz (5.1.2). or
{, } may be used to delimit the function.

5.2.2

VALUE

Optional syntax:
EXXXXXXX n+ n v a l u e ={ e x p r }
Examples:
E41 4 0 v a l u e = {V( 3 ) * V(3) O f f s }

5.2.3

TABLE

Data may be entered from the listings of a data table similar to the pwl B-Source (5.1.4). Data
are grouped into x, y pairs. Expression may be an equation or an expression containing node
voltages or branch currents (in the form of i(vm)) and any other terms as given for the B source
and described in chapter 5.1. It may contain parameters (2.8.1). or {, } may be used to delimit
the function. Expression delivers the x-value, which is used to generate a corresponding yvalue, according to the tabulated value pairs, using linear interpolation. If the x-value is below
x0 , y0 is returned, above x2 y2 is returned (limiting function). The value pairs have to be real
numbers, parameters are not allowed!
Syntax for data entry from table:
Exxx n1 n2 TABLE { e x p r e s s i o n } = ( x0 , y0 ) ( x1 , y1 ) ( x2 , y2 )
Example (simple comparator):
ECMP 11 0 TABLE {V( 1 0 , 9 ) } = (5MV, 0V) ( 5MV, 5V)

5.2.4

POLY

Polynomial sources are only available when the XSPICE option (see 32) is enabled.

96

CHAPTER 5. NON-LINEAR DEPENDENT SOURCES (BEHAVIORAL SOURCES)

General form:
EXXXX N+ N POLY(ND) NC1+ NC1 ( NC2+ NC2 . . . ) P0 ( P1 . . . )
Example:
ENONLIN 100 101 POLY ( 2 ) 3 0 4 0 0 . 0 1 3 . 6 0 . 2 0 . 0 0 5
POLY(ND) Specifies the number of dimensions of the polynomial. The number of pairs of
controlling nodes must be equal to the number of dimensions.
(N+) and (N-) nodes are output nodes. Positive current flows from the (+) node through the
source to the (-) node.
The <NC1+> and <NC1-> are in pairs and define a set of controlling voltages. A particular
node can appear more than once, and the output and controlling nodes need not be different.
The example yields a voltage output controlled by two input voltages v(3,0) and v(4,0). Four
polynomial coefficients are given. The equivalent function to generate the output is:
0 + 13.6 * v(3) + 0.2 * v(4) + 0.005 * v(3) * v(3)
Generally you will set the equation according to
POLY(1) y = p0 +
POLY(2) y = p0 +
+
+
+
POLY(3) y = p0 +
+
+

k1*X1 + p2*X1*X1
+ p3*X1*X1*X1 + ...
p1*X1
+ p2*X2 +
p3*X1*X1
+ p4*X2*X1
+ p5*X2*X2
+
p6*X1*X1*X1
+ p7*X2*X1*X1 + p8*X2*X2*X1 +
p9*X2*X2*X2
+ ...
p1*X1
+ p2*X2
+ p3*X3
+
p4*X1*X1 + p5*X2*X1 + p6*X3*X1 +
p7*X2*X2 + p8*X2*X3 + p9*X3*X3 + ...

where X1 is the voltage difference of the first input node pair, X2 of the second pair and so
on. Keeping track of all polynomial coefficient obviously becomes rather tedious for larger
polynomials.

5.2.5

LAPLACE

Currently ngspice does not offer a direct E-Source element with the LAPLACE option. There
is however, a XSPICE code model equivalent called x_fer (see chapt. 12.2.16), which you may
invoke manually. The XSPICE option has to enabled (32.1). AC (15.3.1) and transient analysis
(15.3.9) is supported.
The following E-Source:
ELOPASS 4 0 LAPLACE {V( 1 ) } {10 / ( s / 6 8 0 0 + 1 ) }
may be replaced by:
AELOPASS 1 i n t _ 4 f i l t e r 1
. model f i l t e r 1 x _ f e r ( g a i n =10 i n t _ i c = [0 0 ] n u m _ c o e f f = [ 1 ]
+
d e n _ c o e f f = [1 1 . 4 7 e 4]
ELOPASS 4 0 i n t _ 4 0 1

5.3. GXXXX: NON-LINEAR CURRENT SOURCE*

97

where you have the voltage of node 1 as input, an intermediate output node int_4 and an Esource as buffer, so to keep the name ELOPASS available if further processing is required.
If the controlling expression is more complex than just a voltage node, you may add a B-Source
(5.1) for evaluating the expression before entering the A-device.
E-Source with complex controlling expression:
ELOPASS 4 0 LAPLACE {V( 1 ) * v ( 2 ) } {10 / ( s / 6 8 0 0 + 1 ) }
may be replaced by:
BELOPASS i n t _ 1 0 V=V( 1 ) * v ( 2 )
AELOPASS i n t _ 1 i n t _ 4 f i l t e r 1
. model f i l t e r 1 x _ f e r ( g a i n =10 i n t _ i c = [0 0 ] n u m _ c o e f f = [ 1 ]
+
d e n _ c o e f f = [1 1 . 4 7 e 4]
ELOPASS 4 0 i n t _ 4 0 1

5.3
5.3.1

Gxxxx: non-linear current source*


CUR

General form:
GXXXXXXX n+ n c u r = e x p r <m= v a l >
Examples:
G51 55 225 c u r = V( 3 ) * V(3) O f f s
Expression may be an equation or an expression containing node voltages or branch currents
(in the form of i(vm)) and any other terms as given for the B source and described in chapter
5.1. It may contain parameters (2.8.1) and special variables (5.1.2). m is an optional multiplier
to the output current. val may be a numerical value or an expression according to 2.8.5 containing only references to other parameters (no node voltages or branch currents!), because it is
evaluated before the simulation commences.

5.3.2

VALUE

Optional syntax:
GXXXXXXX n+ n v a l u e = e x p r <m= v a l >
Examples:
G51 55 225 v a l u e = V( 3 ) * V(3) O f f s

5.3.3

TABLE

A data entry by a tabulated listing is available with syntax similar to the E-Source (see chapt.
5.2.3).

98

CHAPTER 5. NON-LINEAR DEPENDENT SOURCES (BEHAVIORAL SOURCES)

Syntax for data entry from table:


Gxxx n1 n2 TABLE { e x p r e s s i o n } = ( x0 , y0 ) ( x1 , y1 ) ( x2 , y2 ) <m= v a l >
Example (simple comparator with current output and voltage control):
GCMP 0 11 TABLE {V( 1 0 , 9 ) } = (5MV, 0V) ( 5MV, 5V)
R 11 0 1 k

m is an optional multiplier to the output current. val may be a numerical value or an expression
according to 2.8.5 containing only references to other parameters (no node voltages or branch
currents!), because it is evaluated before the simulation commences.

5.3.4

POLY

see E-Source at chapt. 5.2.4.

5.3.5

LAPLACE

See E-Source, chapt. 5.2.5 , for an equivalent code model replacement.

5.3.6

Example

An example file is given below.

5.4. DEBUGGING A BEHAVIORAL SOURCE

99

Example input file:


VCCS , VCVS, nonl i n e a r d e p e n d e n c y
. param Vi =1
. param O f f s = 0 . 0 1 * Vi
* VCCS d e p e n d i n g on V( 3 )
B21 i n t 1 0 V = V( 3 ) * V( 3 )
G1 21 22 i n t 1 0 1
* m e a s u r e c u r r e n t t h r o u g h VCCS
vm 22 0 dc 0
R21 21 0 1
* new VCCS d e p e n d i n g on V( 3 )
G51 55 225 c u r = V( 3 ) * V(3) O f f s
* m e a s u r e c u r r e n t t h r o u g h VCCS
vm5 225 0 dc 0
R51 55 0 1
* VCVS d e p e n d i n g on V( 3 )
B31 i n t 2 0 V = V( 3 ) * V( 3 )
E1 1 0 i n t 2 0 1
R1 1 0 1
* new VCVS d e p e n d i n g on V( 3 )
E41 4 0 v o l = V( 3 ) * V(3) O f f s
R4 4 0 1
* control voltage
V1 3 0 PWL( 0 0 100 u { Vi } )
. control
set noaskquit
t r a n 10 n 100 u u i c
p l o t i ( E1 ) i ( E41 )
p l o t i ( vm ) i ( vm5 )
. endc
. end

*) To get this functionality, the compatibility mode has to be set in spinit or .spiceinit by set
ngbehavior=all.

5.4

Debugging a behavioral source

The B, E, G, sources and the behavioral R, C, L elements are powerful tools to set up user
defined models. Unfortunately debugging these models is not very comfortable.

100

CHAPTER 5. NON-LINEAR DEPENDENT SOURCES (BEHAVIORAL SOURCES)

Example input file with bug (log(-2)):


B source debugging
V1 1 0 1
V2 2 0 2
E41 4 0 v o l = V( 1 ) * l o g (V ( 2 ) )
. control
tran 1 1
. endc
. end
The input file given above results in an error message:
Error:

-2 out of range for log

In this trivial example, the reason and location for the bug is obvious. However, if you have
several equations using behavioral sources, and several occurrences of the log function, then
debugging is nearly impossible.
However, if the variable ngdebug (see 17.7) is set (e.g. in file .spiceinit), a more distinctive
error message is issued, which (after some closer investigation) will reveal the location and
value of the buggy parameter.
Detailed error message for input file with bug (log(-2)):
E r r o r : 2 o u t o f r a n g e f o r l o g
c a l l i n g PTeval , t r e e =
( v0 ) * ( l o g ( v1 ) )
d / d v0 : l o g ( v1 )
d / d v1 : ( v0 ) * ( ( 0 . 4 3 4 2 9 4 ) / ( v1 ) )
values :
var0 = 1
v a r 1 = 2
If variable strict_errorhandling (see 17.7) is set, ngspice exits after this message. If not, gmin
and source stepping may be started, typically without success.

Chapter 6
Transmission Lines
Ngspice implements both the original SPICE3f5 transmission lines models and the one introduced with KSPICE. The latter provide an improved transient analysis of lossy transmission
lines. Unlike SPICE models, which uses the state-based approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems
using the recursive convolution method. The impulse response of an arbitrary transfer function
can be determined by deriving a recursive convolution from the Pade approximations of the
function. We use this approach for simulating each transmission lines characteristics and each
multiconductor lines modal functions. This method of lossy transmission line simulation has
been proved to give a speedup of one to two orders of magnitude over SPICE3f5.

6.1

Lossless Transmission Lines

General form:
TXXXXXXX N1 N2 N3 N4 Z0=VALUE <TD=VALUE> <F=FREQ <NL=NRMLEN>>
+ <IC=V1 , I1 , V2 , I2 >
Examples:
T1 1 0 2 0 Z0=50 TD=10NS
n1 and n2 are the nodes at port 1; n3 and n4 are the nodes at port 2. z0 is the characteristic
impedance. The length of the line may be expressed in either of two forms. The transmission
delay, td, may be specified directly (as td=10ns, for example). Alternatively, a frequency f may
be given, together with nl, the normalized electrical length of the transmission line with respect
to the wavelength in the line at the frequency f. If a frequency is specified but nl is omitted,
0.25 is assumed (that is, the frequency is assumed to be the quarter-wave frequency). Note that
although both forms for expressing the line length are indicated as optional, one of the two must
be specified.
Note that this element models only one propagating mode. If all four nodes are distinct in the actual circuit, then two modes may be excited. To simulate such a situation, two transmission-line
elements are required. (see the example in chapt. 21.7 for further clarification.) The (optional)
initial condition specification consists of the voltage and current at each of the transmission line
ports. Note that the initial conditions (if any) apply only if the UIC option is specified on the
.TRAN control line.

101

102

CHAPTER 6. TRANSMISSION LINES

Note that a lossy transmission line (see below) with zero loss may be more accurate than the
lossless transmission line due to implementation details.

6.2

Lossy Transmission Lines

General form:
OXXXXXXX n1 n2 n3 n4 mname
Examples:
O23 1 0 2 0 LOSSYMOD
OCONNECT 10 5 20 5 INTERCONNECT

This is a two-port convolution model for single conductor lossy transmission lines. n1 and n2
are the nodes at port 1; n3 and n4 are the nodes at port 2. Note that a lossy transmission line
with zero loss may be more accurate than the lossless transmission line due to implementation
details.

6.2.1

Lossy Transmission Line Model (LTRA)

The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth) models a uniform constant-parameter distributed transmission line. The RC and LC cases
may also be modeled using the URC and TRA models; however, the newer LTRA model is usually faster and more accurate than the others. The operation of the LTRA model is based on the
convolution of the transmission lines impulse responses with its inputs (see [8]). The LTRA
model takes a number of parameters, some of which must be given and some of which are
optional.

6.2. LOSSY TRANSMISSION LINES


Name
R
L
G
C
LEN
REL
ABS
NOSTEPLIMIT
NO CONTROL
LININTERP
MIXEDINTERP
COMPACTREL
COMPACTABS
TRUNCNR
TRUNCDONTCUT

Parameter
resistance/length
inductance/length
conductance/length
capacitance/length
length of line
breakpoint control
breakpoint control
dont limit time-step to less
than line delay
dont do complex time-step
control
use linear interpolation
use linear when quadratic
seems bad
special reltol for history
compaction
special abstol for history
compaction
use Newton-Raphson method
for time-step control
dont limit time-step to keep
impulse-response errors low

103
Units/Type
/unit
H/unit
mhos/unit
F/unit
unit
arbitrary unit
flag

Default
0.0
0.0
0.0
0.0
no default
1
1
not set

Example
0.2
9.13e-9
0.0
3.65e-12
1.0
0.5
5
set

flag

not set

set

flag
flag

not set
not set

set
set

RELTOL

1.0e-3

ABSTOL

1.0e-9

flag

not set

set

flag

not set

set

The following types of lines have been implemented so far:


RLC (uniform transmission line with series loss only),
RC (uniform RC line),
LC (lossless transmission line),
RG (distributed series resistance and parallel conductance only).
Any other combination will yield erroneous results and should not be tried. The length LEN
of the line must be specified. NOSTEPLIMIT is a flag that will remove the default restriction
of limiting time-steps to less than the line delay in the RLC case. NO CONTROL is a flag that
prevents the default limiting of the time-step based on convolution error criteria in the RLC and
RC cases. This speeds up simulation but may in some cases reduce the accuracy of results.
LININTERP is a flag that, when specified, will use linear interpolation instead of the default
quadratic interpolation for calculating delayed signals. MIXEDINTERP is a flag that, when specified, uses a metric for judging whether quadratic interpolation is not applicable and if so uses
linear interpolation; otherwise it uses the default quadratic interpolation. TRUNCDONTCUT is a
flag that removes the default cutting of the time-step to limit errors in the actual calculation of
impulse-response related quantities. COMPACTREL and COMPACTABS are quantities that control
the compaction of the past history of values stored for convolution. Larger values of these lower
accuracy but usually increase simulation speed. These are to be used with the TRYTOCOMPACT
option, described in the .OPTIONS section. TRUNCNR is a flag that turns on the use of NewtonRaphson iterations to determine an appropriate time-step in the time-step control routines. The

104

CHAPTER 6. TRANSMISSION LINES

default is a trial and error procedure by cutting the previous time-step in half. REL and ABS are
quantities that control the setting of breakpoints.
The option most worth experimenting with for increasing the speed of simulation is REL. The
default value of 1 is usually safe from the point of view of accuracy but occasionally increases
computation time. A value greater than 2 eliminates all breakpoints and may be worth trying
depending on the nature of the rest of the circuit, keeping in mind that it might not be safe from
the viewpoint of accuracy.
Breakpoints may usually be entirely eliminated if it is expected the circuit will not display
sharp discontinuities. Values between 0 and 1 are usually not required but may be used for
setting many breakpoints.
COMPACTREL may also be experimented with when the option TRYTOCOMPACT is specified in
a .OPTIONS card. The legal range is between 0 and 1. Larger values usually decrease the
accuracy of the simulation but in some cases improve speed. If TRYTOCOMPACT is not specified
on a .OPTIONS card, history compaction is not attempted and accuracy is high.
NO CONTROL, TRUNCDONTCUT and NOSTEPLIMIT also tend to increase speed at the expense of
accuracy.

6.3

Uniform Distributed RC Lines

General form:
UXXXXXXX n1 n2 n3 mname l = l e n <n=lumps >
Examples:
U1 1 2 0 URCMOD L=50U
URC2 1 12 2 UMODL l =1MIL N=6
n1 and n2 are the two element nodes the RC line connects, while n3 is the node to which the
capacitances are connected. mname is the model name, len is the length of the RC line in
meters. lumps, if specified, is the number of lumped segments to use in modeling the RC line
(see the model description for the action taken if this parameter is omitted).

6.3.1

Uniform Distributed RC Model (URC)

The URC model is derived from a model proposed by L. Gertzberg in 1974. The model is
accomplished by a subcircuit type expansion of the URC line into a network of lumped RC
segments with internally generated nodes. The RC segments are in a geometric progression,
increasing toward the middle of the URC line, with K as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the
following formula:

N=





(K1) 2
RC
2

log Fmax L L 2L K

(6.1)
log K
The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a nonzero value, in which case the capacitors are replaced with reverse biased diodes

6.4. KSPICE LOSSY TRANSMISSION LINES

105

with a zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current of ISPERL amps per meter of transmission line and an optional series resistance
equivalent to RSPERL ohms per meter.
Name
K
FMAX
RPERL
CPERL
ISPERL
RSPERL

6.4

Parameter
Propagation Constant
Maximum Frequency of interest
Resistance per unit length
Capacitance per unit length
Saturation Current per unit length
Diode Resistance per unit length

Units
Hz
/m
F/m
A/m
/m

Default
2.0
1.0 G
1000
10e-15
0
0

Example
1.2
6.5 Meg
10
1p
-

Area
-

KSPICE Lossy Transmission Lines

Unlike SPICE3, which uses the state-based approach to simulate lossy transmission lines,
KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the
recursive convolution method. The impulse response of an arbitrary transfer function can be
determined by deriving a recursive convolution from the Pade approximations of the function.
NGSPICE is using this approach for simulating each transmission lines characteristics and each
multiconductor lines modal functions. This method of lossy transmission line simulation has
shown to give a speedup of one to two orders of magnitude over SPICE3E. Please note that the
following two models will support only transient simulation, no ac.
Additional Documentation Available:
S. Lin and E. S. Kuh, "Pade Approximation Applied to Transient Simulation of Lossy
Coupled Transmission Lines," Proc. IEEE Multi-Chip Module Conference, 1992, pp.
52-55.
S. Lin, M. Marek-Sadowska, and E. S. Kuh, "SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits," European Design Automation Conf.,
February 1991, pp. 142-148.
S. Lin and E. S. Kuh, "Transient Simulation of Lossy Interconnect," Proc. Design Automation Conference, Anaheim, CA, June 1992, pp. 81-86.

6.4.1

Single Lossy Transmission Line (TXL)

General form:
YXXXXXXX N1 0 N2 0 mname <LEN=LENGTH>
Example:
Y1 1 0 2 0 ymod LEN=2
.MODEL ymod t x l R= 1 2 . 4 5 L = 8 . 9 7 2 e9 G=0 C= 0 . 4 6 8 e 12 l e n g t h =16
n1 and n2 are the nodes of the two ports. The optional instance parameter len is the length of
the line and may be expressed in multiples of [unit]. Typically unit is given in meters. len will
override the model parameter length for the specific instance only.

106

CHAPTER 6. TRANSMISSION LINES

The TXL model takes a number of parameters:


Name
R
L
G
C
LENGTH

Parameter
resistance/length
inductance/length
conductance/length
capacitance/length
length of line

Units/Type
/unit
H/unit
mhos/unit
F/unit
unit

Default
0.0
0.0
0.0
0.0
no default

Example
0.2
9.13e-9
0.0
3.65e-12
1.0

Model parameter length must be specified as a multiple of unit. Typically unit is given in [m].
For transient simulation only.

6.4.2

Coupled Multiconductor Line (CPL)

The CPL multiconductor line model is in theory similar to the RLGC model, but without frequency dependent loss (neither skin effect nor frequency-dependent dielectric loss). Up to 8
coupled lines are supported in NGSPICE.
General form:
PXXXXXXX NI1 NI2 . . . NIX GND1 NO1 NO2 . . . NOX GND2 mname <LEN=LENGTH>
Example:
P1 i n 1 i n 2 0 b1 b2 0 PLINE
. model PLINE CPL l e n g t h ={ Len }
+R=1 0 1
+L={L11 } { L12 } { L22 }
+G=0 0 0
+C={C11} {C12} {C22}
. param Len =1 Rs=0
+ C11 = 9 . 1 4 3 5 7 9 E11 C12 = 9.78265E12 C22 = 9 . 1 4 3 5 7 8 E11
+ L11 = 3 . 8 3 5 7 2 E7 L12 = 8 . 2 6 2 5 3 E8 L22 = 3 . 8 3 5 7 2 E7
ni1 ... nix are the nodes at port 1 with gnd1; no1 ... nox are the nodes at port 2 with gnd2.
The optional instance parameter len is the length of the line and may be expressed in multiples
of [unit]. Typically unit is given in meters. len will override the model parameter length for
the specific instance only.
The CPL model takes a number of parameters:
Name
R
L
G
C
LENGTH

Parameter
resistance/length
inductance/length
conductance/length
capacitance/length
length of line

Units/Type
/unit
H/unit
mhos/unit
F/unit
unit

Default
0.0
0.0
0.0
0.0
no default

Example
0.2
9.13e-9
0.0
3.65e-12
1.0

All RLGC parameters are given in Maxwell matrix form. For the R and G matrices the diagonal
elements must be specified, for L and C matrices the lower or upper triangular elements must
specified. The parameter LENGTH is a scalar and is mandatory. For transient simulation only.

Chapter 7
Diodes
7.1

Junction Diodes

General form:
DXXXXXXX n+ n mname < a r e a = v a l > <m= v a l > < p j = v a l > < o f f > < i c =vd >
+ <temp= v a l > <dtemp = v a l >
Examples:
DBRIDGE 2 10 DIODE1
DCLMP 3 7 DMOD AREA= 3 . 0 IC = 0 . 2
The pn junction (diode) implemented in ngspice expands the one found in SPICE3f5. Perimeter
effects and high injection level have been introduced into the original model and temperature
dependence of some parameters has been added. n+ and n- are the positive and negative nodes,
respectively. mname is the model name. Instance parameters may follow, dedicated to only
the diode described in the respective line. area is the area scale factor, which may scale
the saturation current given by the model parameters (and others, see table below). pj is the
perimeter scale factor, scaling the sidewall saturation current and its associated capacitance. m
is a multiplier to area and perimeter, and off indicates an (optional) starting condition on the
device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional)
initial condition specification using ic is intended for use with the uic option on the .tran
control line, when a transient analysis is desired starting from other than the quiescent operating
point. You should supply the initial voltage across the diode there. The (optional) temp value
is the temperature at which this device is to operate, and overrides the temperature specification
on the .option control line. The temperature of each instance can be can be specified as an
offset to the circuit temperature with the dtemp option.

7.2

Diode Model (D)

The dc characteristics of the diode are determined by the parameters is and n. An ohmic resistance, rs, is included. Charge storage effects are modeled by a transit time, tt, and a nonlinear
depletion layer capacitance which is determined by the parameters cjo, vj, and m. The temperature dependence of the saturation current is defined by the parameters eg, the energy and xti,

107

108

CHAPTER 7. DIODES

the saturation current temperature exponent. The nominal temperature at which these parameters were measured is tnom, which defaults to the circuit-wide value specified on the .options
control line. Reverse breakdown is modeled by an exponential increase in the reverse diode
current and is determined by the parameters bv and ibv (both of which are positive numbers).

Junction DC parameters

Name
BV
IBV
IK (IKF)
IKR
IS (JS)
JSW
N
RS

Parameter
Reverse breakdown voltage
Current at breakdown voltage
Forward knee current
Reverse knee current
Saturation current
Sidewall saturation current
Emission coefficient
Ohmic resistance

Units
V
A
A
A
A
A

Default

1.0e-3
1.0e-3
1.0e-3
1.0e-14
1.0e-14
1
0.0

Example
40
1.0e-4
1.0e-6
1.0e-6
1.0e-16
1.0e-15
1.5
100

Scale factor

Parameter
Zero-bias junction bottom-wall
capacitance
Zero-bias junction sidewall
capacitance
Coefficient for forward-bias
depletion bottom-wall capacitance
formula
Coefficient for forward-bias
depletion sidewall capacitance
formula
Area junction grading coefficient
Periphery junction grading
coefficient
Junction potential
Periphery junction potential
Transit-time

Units
F

Default
0.0

Example
2pF

0.0

.1pF

0.5

0.5

0.5
0.33

0.5
0.5

V
V
sec

1
1
0

0.6
0.6
0.1ns

area
perimeter
1/area

Junction capacitance parameters

Name
CJO (CJ0)
CJP (CJSW)
FC

FCS

M (MJ)
MJSW
VJ (PB)
PHP
TT

Scale factor
area
perimeter

7.3. DIODE EQUATIONS

109

Temperature effects
Name

Parameter

Units

Default

EG

Activation energy

eV

1.11

TM1
TM2
TNOM (TREF)
TRS1 (TRS)
TRS2
TM1
TM2
TTT1
TTT2

1st order tempco for MJ


2nd order tempco for MJ
Parameter measurement temperature
1st order tempco for RS
2nd order tempco for RS
1st order tempco for MJ
2nd order tempco for MJ
1st order tempco for TT
2nd order tempco for TT

1/C

1/C2

0.0
0.0
27
0.0
0.0
0.0
0.0
0.0
0.0

XTI

Saturation current temperature exponent

3.0

TLEV
TLEVC
CTA (CTC)
CTP
TCV

Diode temperature equation selector


Diode capac. temperature equation selector
Area junct. cap. temperature coefficient
Perimeter junct. cap. temperature coefficient
Breakdown voltage temperature coefficient

1/C
1/C
1/C

0
0
0.0
0.0
0.0

1/C2
C
1/C
1/C2
1/C
1/C2
1/C

Example
1.11 Si
0.69 Sbd
0.67 Ge
50
3.0 pn
2.0 Sbd

Noise modeling
Name
KF
AF

Parameter
Flicker noise coefficient
Flicker noise exponent

Units
-

Default
0
1

Example

Scale factor

Diode models may be described in the input file (or an file included by .inc) according to the
following example:
General form:
. model mname t y p e ( pname1= p v a l 1 pname2= p v a l 2 . . . )
Examples:
. model DMOD D ( b f =50 i s =1e 13 v b f = 50 )

7.3

Diode Equations

The junction diode is the basic semiconductor device and the simplest one modeled in ngspice,
but its model is quite complex, even if not all the physical phenomena affecting a pn junction
are modeled. The diode is modeled in three different regions:
Forward bias: the anode is more positive than the cathode, the diode is "on" and can
conduct large currents. To avoid convergence problems and unrealistic high current, it is
better to specify a series resistance to limit current with rs model parameter.

Scale fac

110

CHAPTER 7. DIODES
Reverse bias: the cathode is more positive than the anode and the diode is "off". A reverse
bias diode conducts a small leakage current.
Breakdown: the breakdown region is model led only if the bv model parameter is given.
When a diode enters breakdown the current increase exponentially (remember to limit it);
bv is a positive value.

Parameters Scaling
Model parameters are scaled using the unit-less parameters area and pj and the multiplier m as
depicted below:
AREAe f f = AREA M
PJe f f = PJ M
ISe f f = IS AREAe f f + JSW PJe f f
IBVe f f = IBV AREAe f f
IKe f f = IK AREAe f f
IKRe f f = IKR AREAe f f
CJe f f = CJ0 AREAe f f
CJPe f f = CJP PJe f f
Diode DC, Transient and AC model equations

qVD

NkT 1) +VD GMIN,


if VD 3 NkT
IS
(e

e
f
f
q

3NkT 3
ID = ISe f f [1 + ( qVD e ) ] +VD GMIN, if BVe f f < VD < 3 NkT
q

q(BVe f f +VD )

NkT
ISe f f (e
) +VD GMIN, if VD BVe f f

(7.1)

The breakdown region must be described with more depth since the breakdown is not modeled
in physically. As written before, the breakdown modeling is based on two model parameters:
the "nominal breakdown voltage" bv and the current at the onset of breakdown ibv. For the
diode model to be consistent, the current value cannot be arbitrary chosen, since the reverse bias
and breakdown regions must match. When the diode enters breakdown region from reverse bias,
the current is calculated using the formula1 :
Ibdwn = ISe f f (e

qBV
NkT

1)

(7.2)

The computed current is necessary to adjust the breakdown voltage making the two regions
match. The algorithm is a little bit convoluted and only a brief description is given here:
Most real diodes shows a current increase that, at high current levels, does not follow the exponential relationship given above. This behavior is due to high level of carriers injected into the
junction. High injection effects (as they are called) are modeled with ik and ikr.
1 if

you look at the source code in file diotemp.c you will discover that the exponential relation is replaced
with a first order Taylor series expansion.

7.3. DIODE EQUATIONS

111

Algorithm 7.1 Diode breakdown current calculation


if IBVe f f < Ibdwn then
IBVe f f = Ibdwn
BVe f f = BV
else
IBVe f f
BVe f f = BV NVt ln( Ibdwn
)

IDe f f =

rID
,

1+ IKID

if VD 3 NkT
q

ef f

(7.3)

rID

, otherwise.

1+ IKRID
ef f

Diode capacitance is divided into two different terms:


Depletion capacitance
Diffusion capacitance
Depletion capacitance is composed by two different contributes, one associated to the bottom
of the junction (bottom-wall depletion capacitance) and the other to the periphery (sidewall
depletion capacitance). The basic equations are:
CDiode = Cdi f f usion +Cdepletion
Where the depletion capacitance i defined as:
Cdepletion = Cdeplbw +Cdeplsw
The diffusion capacitance, due to the injected minority carriers is modeled with the transit time
tt:
Cdi f f usion = TT

IDe f f
VD

The depletion capacitance is more complex to model, since the function used to approximate it
diverges when the diode voltage become greater than the junction built-in potential. To avoid
function divergence, the capacitance function is approximated with a linear extrapolation for
applied voltage greater than a fraction of the junction built-in potential.

Cdeplbw =

Cdeplsw =

CJe f f (1 VD )MJ ,
VJ
CJe f f

VD
1FC(1+MJI)+MJ VJ
(1FC)(1+MJ)

CJPe f f (1 VD )MJSW ,
PHP
CJPe f f

if VD < FC VJ
, otherwise.

VD
1FCS(1+MJSW)+MJSW PHP
(1+MJSW)
(1FCS)

if VD < FCS PHP


, otherwise.

(7.4)

(7.5)

112

CHAPTER 7. DIODES

Temperature dependence
The temperature affects many of the parameters in the equations above, the following equations show how. One of the most significant parameter that varies with the temperature for a
semiconductor is the band-gap energy:
EGnom = 1.16 7.02e4

TNOM2
TNOM + 1108.0

(7.6)

EG(T ) = 1.16 7.02e4

T2
TNOM + 1108.0

(7.7)

The leakage currents temperature dependence is:


IS(T ) = IS e

log f actor
N

JSW (T ) = JSW e

log f actor
N

(7.8)
(7.9)

where "logfactor" is defined:


log f actor =

EG
T
EG

+ XTI ln(
)
Vt (TNOM) Vt (T )
TNOM

(7.10)

The contact potentials (bottom-wall an sidewall) temperature dependence is:




T
T
EGnom
EG(T)
V J(T ) = VJ (
) Vt (T ) 3 ln(
)+

TNOM
TNOM
Vt (TNOM) Vt (T )


T
T
EGnom
EG(T)
PHP(T ) = PHP (
) Vt (T ) 3 ln(
)+

TNOM
TNOM
Vt (TNOM) Vt (T )

(7.11)

(7.12)

The depletion capacitances temperature dependence is:




V J(T )
4
CJ(T ) = CJ 1 + MJ (4.0e (T TNOM)
+ 1)
VJ


PHP(T )
4
CJSW (T ) = CJSW 1 + MJSW (4.0e (T TNOM)
+ 1)
PHP

(7.13)

(7.14)

The transit time temperature dependence is:


T T (T ) = TT (1 + TTT1 (T TNOM) + TTT2 (T TNOM)2 )

(7.15)

The junction grading coefficient temperature dependence is:


MJ(T ) = MJ (1 + TM1 (T TNOM) + TM2 (T TNOM)2 )

(7.16)

The series resistance temperature dependence is:


RS(T ) = RS (1 + TRS (T TNOM) + TRS2 (T TNOM)2 )

(7.17)

7.3. DIODE EQUATIONS

113

Noise model
The diode has three noise contribution, one due to the presence of the parasitic resistance rs
and the other two (shot and flicker) due to the pn junction.
The thermal noise due to the parasitic resistance is:
i2RS =

4kT f
RS

(7.18)

The shot and flicker noise contributions are:


i2d = 2qID f +

KF IDAF
f
f

(7.19)

114

CHAPTER 7. DIODES

Chapter 8
BJTs
8.1

Bipolar Junction Transistors (BJTs)

General form:
QXXXXXXX nc nb ne <ns > mname < a r e a = v a l > < a r e a c = v a l > < a r e a b = v a l >
+ <m= v a l > < o f f > < i c =vbe , vce > <temp= v a l > <dtemp = v a l >
Examples:
Q23 10 24 13 QMOD IC = 0 . 6 , 5 . 0
Q50A 11 26 4 20 MOD1
nc, nb, and ne are the collector, base, and emitter nodes, respectively. ns is the (optional)
substrate node. If unspecified, ground is used. mname is the model name, area, areab, areac
are the area factors (emitter, base and collector respectively), and off indicates an (optional)
initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is
assumed.
The (optional) initial condition specification using ic=vbe,vce is intended for use with the
uic option on a .tran control line, when a transient analysis is desired starting from other
than the quiescent operating point. See the .ic control line description for a better way to set
transient initial conditions. The (optional) temp value is the temperature at which this device
is to operate, and overrides the temperature specification on the .option control line. Using
dtemp option you can specify instances temperature relative to the circuit temperature.

8.2

BJT Models (NPN/PNP)

Ngspice provides three BJT device models, which are selected by the .model card.
.model QMOD1 BJT level=2
This is the minimal version, further optional parameters listed in the table below may replace
the ngspice default parameters. The level keyword specifies the model to be used:
level=1 : This is the original SPICE BJT model, and it is the default model if the level
keyword is not specified on the .model line.

115

116

CHAPTER 8. BJTS
level=2 : This is a modified version of the original SPICE BJT that models both vertical
and lateral devices and includes temperature corrections of collector, emitter and base
resistors.
level=4: Advanced VBIC model (see http://www.designers-guide.org/VBIC/ for details)

The bipolar junction transistor model in ngspice is an adaptation of the integral charge control
model of Gummel and Poon. This modified Gummel-Poon model extends the original model
to include several effects at high bias levels. The model automatically simplifies to the simpler
Ebers-Moll model when certain parameters are not specified. The parameter names used in the
modified Gummel-Poon model have been chosen to be more easily understood by the program
user, and to reflect better both physical and circuit design thinking.
The dc model is defined by the parameters is, bf, nf, ise, ikf, and ne which determine
the forward current gain characteristics, is, br, nr, isc, ikr, and nc which determine the
reverse current gain characteristics, and vaf and var which determine the output conductance
for forward and reverse regions.
Level 1 model has among the standard temperature model a extension which is compatible with
most foundry provided process design kits (see parameter table below tlev).
Level 1 and 2 model includes substrate saturation current iss. Three ohmic resistances rb, rc,
and re are included, where rb can be high current dependent. Base charge storage is modeled
by forward and reverse transit times, tf and tr, the forward transit time tf being bias dependent
if desired, and nonlinear depletion layer capacitances which are determined by cje, vje, and
nje for the B-E junction, cjc, vjc, and njc for the B-C junction and cjs, vjs, and mjs for
the C-S (Collector-Substrate) junction.
Level 1 and 2 model defines a substrate capacitance that will be connected to devices base or
collector, to model lateral or vertical devices dependent from the parameter subs. The temperature dependence of the saturation currents, is and iss (for level 2 model), is determined by
the energy-gap, eg, and the saturation current temperature exponent, xti.
Additionally base current temperature dependence is modeled by the beta temperature exponent
xtb in the new model. The values specified are assumed to have been measured at the temperature tnom, which can be specified on the .options control line or overridden by a specification
on the .model line.
Level 4 model (VBIC) has the following improvements beyond the GP models: Improved Early
effect modeling, Quasi-saturation modeling, Parasitic substrate transistor modeling, Parasitic
fixed (oxide) capacitance modeling, Includes an avalanche multiplication model, Improved temperature modeling, Base current is decoupled from collector current, Electrothermal modeling,
Smooth, continuous mode.
The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter
names used in earlier versions of SPICE2 are still accepted.
Gummel-Poon BJT Parameters (incl. model extensions)
Name

Parameters

Units

Default

Example

Scale factor

8.2. BJT MODELS (NPN/PNP)

SUBS

IS
ISS

BF
NF
VAF (VA)
IKF
NKF
ISE
NE
BR
NR
VAR (VB)
IKR
ISC

NC
RB
IRB
RBM
RE
RC
CJE
VJE (PE)
MJE (ME)
TF
XTF
VTF
ITF

Substrate connection: for vertical


geometry, -1 for lateral geometry
(level 2 only).
Transport saturation current.
Reverse saturation current,
substrate-to-collector for vertical
device or substrate-to-base for
lateral (level 2 only).
Ideal maximum forward beta.
Forward current emission
coefficient.
Forward Early voltage.
Corner for forward beta current
roll-off.
High current Beta rolloff exponent
B-E leakage saturation current.
B-E leakage emission coefficient.
Ideal maximum reverse beta.
Reverse current emission
coefficient.
Reverse Early voltage.
Corner for reverse beta high
current roll-off.
B-C leakage saturation current
(area is "areab" for vertical devices
and "areac" for lateral).
B-C leakage emission coefficient.
Zero bias base resistance.
Current where base resistance falls
halfway to its min value.
Minimum base resistance at high
currents.
Emitter resistance.
Collector resistance.
B-E zero-bias depletion
capacitance.
B-E built-in potential.
B-E junction exponential factor.
Ideal forward transit time.
Coefficient for bias dependence of
TF.
Voltage describing VBC
dependence of TF.
High-current parameter for effect
on TF.

117

A
A

1.0e-16
1.0e-16

1.0e-15
1.0e-15

100
1.0

100
1

V
A

200
0.01

A
-

0.5
0.0
1.5
1
1

0.58
1e-13
2
0.1
1

V
A

200
0.01

area

0.0

1e-13

area

2
0

1.5
100
0.1

area
area

RB

10

area

0
0
0

1
10
2pF

area
area
area

V
sec
-

0.75
0.33
0
0

0.6
0.33
0.1ns

area
area

area

area

area

118

CHAPTER 8. BJTS

PTF
CJC

VJC (PC)
MJC
XCJC

TR
CJS

VJS (PS)
MJS (MS)
XTB
EG
XTI
KF
AF
FC
TNOM (TREF)
TLEV
TLEVC
TRE1
TRE2
TRC1
TRC2
TRB1

Excess phase at freq=1.0/(TF*2PI)


Hz.
B-C zero-bias depletion
capacitance (area is "areab" for
vertical devices and "areac" for
lateral).
B-C built-in potential.
B-C junction exponential factor.
Fraction of B-C depletion
capacitance connected to internal
base node.
Ideal reverse transit time.
Zero-bias collector-substrate
capacitance (area is "areac" for
vertical devices and"areab" for
lateral).
Substrate junction built-in
potential.
Substrate junction exponential
factor.
Forward and reverse beta
temperature exponent.
Energy gap for temperature effect
on IS.
Temperature exponent for effect on
IS.
Flicker-noise coefficient.
Flicker-noise exponent.
Coefficient for forward-bias
depletion capacitance formula.
Parameter measurement
temperature.
BJT temperature equation selector
BJT capac. temperature equation
selector
1st order temperature coefficient
for RE.
2nd order temperature coefficient
for RE.
1st order temperature coefficient
for RC .
2nd order temperature coefficient
for RC.
1st order temperature coefficient
for RB.

deg

2pF

V
-

0.75
0.33
1

0.5
0.5

sec
F

0
0

10ns
2pF

0.75

eV

1.11

0
1
0.5

27

50

0
0

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

0.5

area

area

8.2. BJT MODELS (NPN/PNP)

TRB2
TRBM1
TRBM2
TBF1
TBF2
TBR1
TBR2
TIKF1
TIKF2
TIKR1
TIKR2
TIRB1
TIRB2
TNC1
TNC2
TNE1
TNE2
TNF1
TNF2
TNR1
TNR2
TVAF1
TVAF2

2nd order temperature coefficient


for RB.
1st order temperature coefficient
for RBM
2nd order temperature coefficient
for RBM
1st order temperature coefficient
for BF
2nd order temperature coefficient
for BF
1st order temperature coefficient
for BR
2nd order temperature coefficient
for BR
1st order temperature coefficient
for IKF
2nd order temperature coefficient
for IKF
1st order temperature coefficient
for IKR
2nd order temperature coefficient
for IKR
1st order temperature coefficient
for IRB
2nd order temperature coefficient
for IRB
1st order temperature coefficient
for NC
2nd order temperature coefficient
for NC
1st order temperature coefficient
for NE
2nd order temperature coefficient
for NE
1st order temperature coefficient
for NF
2nd order temperature coefficient
for NF
1st order temperature coefficient
for IKF
2nd order temperature coefficient
for IKF
1st order temperature coefficient
for VAF
2nd order temperature coefficient
for VAF

119

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

120

CHAPTER 8. BJTS

TVAR1
TVAR2
CTC
CTE
CTS
TVJC
TVJE
TITF1
TITF2
TTF1
TTF2
TTR1
TTR2
TMJE1
TMJE2
TMJC1
TMJC2

1st order temperature coefficient


for VAR
2nd order temperature coefficient
for VAR
1st order temperature coefficient
for CJC
1st order temperature coefficient
for CJE
1st order temperature coefficient
for CJS
1st order temperature coefficient
for VJC
1st order temperature coefficient
for VJE
1st order temperature coefficient
for ITF
2nd order temperature coefficient
for ITF
1st order temperature coefficient
for TF
2nd order temperature coefficient
for TF
1st order temperature coefficient
for TR
2nd order temperature coefficient
for TR
1st order temperature coefficient
for MJE
2nd order temperature coefficient
for MJE
1st order temperature coefficient
for MJC
2nd order temperature coefficient
for MJC

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C

0.0

1e-3

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

1/C

0.0

1e-3

1/C2

0.0

1e-5

Chapter 9
JFETs
9.1

Junction Field-Effect Transistors (JFETs)

General form:
JXXXXXXX nd ng n s mname < a r e a > < o f f > < i c =vds , vgs > <temp= t >
Examples:
J 1 7 2 3 JM1 OFF
nd, ng, and ns are the drain, gate, and source nodes, respectively. mname is the model name,
area is the area factor, and off indicates an (optional) initial condition on the device for dc
analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition
specification, using ic=VDS,VGS is intended for use with the uic option on the .TRAN control
line, when a transient analysis is desired starting from other than the quiescent operating point.
See the .ic control line for a better way to set initial conditions. The (optional) temp value is
the temperature at which this device is to operate, and overrides the temperature specification
on the .option control line.

9.2
9.2.1

JFET Models (NJF/PJF)


JFET level 1 model with Parker Skellern modification

The level 1 JFET model is derived from the FET model of Shichman and Hodges. The dc
characteristics are defined by the parameters VTO and BETA, which determine the variation
of drain current with gate voltage, LAMBDA, which determines the output conductance, and
IS, the saturation current of the two gate junctions. Two ohmic resistances, RD and RS, are
included.
vgst = vgs V T O

(9.1)

p = BETA (1 + LAMBDA vds)

(9.2)

121

122

CHAPTER 9. JFETS

b f ac =

1B
PB V T O

(9.3)

if vgst
vds GMIN,
IDrain = p vds (vds (b f ac vds B) vgst (2 B + 3 b f ac (vgst vds))) + vds GMIN, if vgst

p vgst 2 (B + vgst b f ac) + vds GMIN,


if vgst <
(9.4)
Note that in Spice3f and later, the fitting parameter B has been added by Parker and Skellern.
For details, see [9]. If parameter B is set to 1 equation above simplifies to

if vgst 0
vds GMIN,
IDrain = p vds (2 vgst vds) + vds GMIN, if vgst vds

p vgst 2 + vds GMIN,


if vgst < vds

(9.5)

Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions
which vary as the 1/2 power of junction voltage and are defined by the parameters CGS, CGD,
and PB.
Name
VTO
BETA
LAMBDA
RD
RS
CGS
CGD
PB
IS
B
KF
AF
NLEV
GDSNOI
FC
TNOM
TCV
BEX

Parameter
Threshold voltage VT 0
Transconductance parameter ( )
Channel-length modulation
parameter ( )
Drain ohmic resistance
Source ohmic resistance
Zero-bias G-S junction capacitance
Cgs
Zero-bias G-D junction
capacitance Cgd
Gate junction potential
Gate saturation current IS
Doping tail parameter
Flicker noise coefficient
Flicker noise exponent
Noise equation selector
Channel noise coefficient for
nlev=3
Coefficient for forward-bias
depletion capacitance formula
Parameter measurement
temperature
Threshold voltage temperature
coefficient
Mobility temperature exponent

Units
V
A/V
1/V

Default
-2.0
1.0e-4
0

Example
-2.0
1.0e-3
1.0e-4

Scaling factor

0
0
0

100
100
5pF

area
area
area

1pF

area

V
A
-

1
1.0e-14
1
0
1
1
1.0

0.6
1.0e-14
1.1

area

3
2.0

0.5
C

27

50

1/C

0.0

0.1

0.0

1.1

area

9.2. JFET MODELS (NJF/PJF)

123

Additional to the standard thermal and flicker noise model an alternative thermal channel noise
model is implemented and is selectable by setting NLEV parameter to 3. This follows in a
correct channel thermal noise in the linear region.

Snoise =

(1 + + 2 )
2
4 k T BETA V gst
GDSNOI
3
1+

(9.6)

with

9.2.2

(
vds
1 vgsV
T O , if vgs V T O vds
0,

else

(9.7)

JFET level 2 Parker Skellern model

The level 2 model is an improvement to level 1. Details are available from Macquarie University. Some important items are:

The description maintains strict continuity in its high-order derivatives, which is essential
for prediction of distortion and intermodulation.
Frequency dependence of output conductance and transconductance is described as a
function of bias.
Both drain-gate and source-gate potentials modulate the pinch-off potential, which is consistent with S-parameter and pulsed-bias measurements.
Self-heating varies with frequency.
Extreme operating regions - subthreshold, forward gate bias, controlled resistance, and
breakdown regions - are included.
Parameters provide independent fitting to all operating regions. It is not necessary to
compromise one region in favor of another.
Strict drain-source symmetry is maintained. The transition during drain-source potential
reversal is smooth and continuous.

The model equations are described in this pdf document and in [19].

124
Name
ID
ACGAM
BETA
CGD
CGS
DELTA
FC
HFETA
HFE1
HFE2
HFGAM
HFG1
HFG2
IBD
IS
LFGAM
LFG1
LFG2
MVST
N
P
Q
RS
RD
TAUD
TAUG
VBD
VBI
VST
VTO
XC
XI
Z
RG
LG
LS
LD
CDSS
AFAC
NFING
TNOM
TEMP

CHAPTER 9. JFETS
Description
Device IDText
Capacitance modulation
Linear-region transconductance scale
Zero-bias gate-source capacitance
Zero-bias gate-drain capacitance
Thermal reduction coefficient
Forward bias capacitance parameter
High-frequency VGS feedback parameter
HFGAM modulation by VGD
HFGAM modulation by VGS
High-frequency VGD feedback parameter
HFGAM modulation by VSG
HFGAM modulation by VDG
Gate-junction breakdown current
Gate-junction saturation current
Low-frequency feedback parameter
LFGAM modulation by VSG
LFGAM modulation by VDG
Subthreshold modulation
Gate-junction ideality factor
Linear-region power-law exponent
Saturated-region power-law exponent
Source ohmic resistance
Drain ohmic resistance
Relaxation time for thermal reduction
Relaxation time for gamma feedback
Gate-junction breakdown potential
Gate-junction potential
Subthreshold potential
Threshold voltage
Capacitance pinch-off reduction factor
Saturation-knee potential factor
Knee transition parameter
Gate ohmic resistance
Gate inductance
Source inductance
Drain inductance
Fixed Drain-source capacitance
Gate-width scale factor
Number of gate fingers scale factor
Nominal Temperature (Not implemented)
Temperature

Unit Type
Text
None
None
Capacitance
Capacitance
None
None
None
None
None
None
None
None
Current
Current
None
None
None
None
None
None
None
Resistance
Resistance
Time
Time
Voltage
Voltage
Voltage
Voltage
None
None
None
Resistance
Inductance
Inductance
Inductance
Capacitance
None
None
Temperature
Temperature

Default
PF1
0
104
0F
0F
0W
0.5
0
0V 1
0 V1
0
0 V1
0 V1
0A
1014A
0
0 V1
0 V1
0 V1
1
2
2
0 Ohm
0 Ohm
0s
0s
1V
1V
0V
-2.0 V
0
1000
0.5
0 Ohm
0H
0H
0H
0F
1
1
300 K
300 K

Chapter 10
MESFETs
10.1

MESFETs

General form:
ZXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS>
Examples:
Z1 7 2 3 ZM1 OFF

10.2

MESFET Models (NMF/PMF)

10.2.1

Model by Statz e.a.

The MESFET model level 1 is derived from the GaAs FET model of Statz et al. as described in
[11]. The dc characteristics are defined by the parameters VTO, B, and BETA, which determine
the variation of drain current with gate voltage, ALPHA, which determines saturation voltage,
and LAMBDA, which determines the output conductance. The formula are given by:

Id =

3


B(Vgs VT )2
Vds
1

A

3 (1 + LVds )
1+b(Vgs VT )
B(Vgs VT )2
1+b(Vgs VT ) (1 + LVds )

for 0 < Vds <


for V >

3
A

(10.1)

3
A

Two ohmic resistances, rd and rs, are included. Charge storage is modeled by total gate charge
as a function of gate-drain and gate-source voltages and is defined by the parameters cgs, cgd,
and pb.

125

126

CHAPTER 10. MESFETS

Name
VTO
BETA
B
ALPHA
LAMBDA
RD
RS
CGS
CGD
PB
KF
AF
FC

Parameter
Pinch-off voltage
Transconductance parameter
Doping tail extending parameter
Saturation voltage parameter
Channel-length modulation parameter
Drain ohmic resistance
Source ohmic resistance
Zero-bias G-S junction capacitance
Zero-bias G-D junction capacitance
Gate junction potential
Flicker noise coefficient
Flicker noise exponent
Coefficient for forward-bias depletion
capacitance formula

Units
V
A/V 2
1/V
1/V
1/V

F
F
V
-

Default
-2.0
1.0e-4
0.3
2
0
0
0
0
0
1
0
1
0.5

Example
-2.0
1.0e-3
0.3
2
1.0e-4
100
100
5pF
1pF
0.6

Area
*
*
*
*
*
*
*

Device instance:
z1 2 3 0 mesmod a r e a = 1 . 4
Model:
. model mesmod nmf l e v e l =1 r d =46 r s =46 v t 0 = 1.3
+ lambda = 0 . 0 3 a l p h a =3 b e t a = 1 . 4 e3

10.2.2

Model by Ytterdal e.a.

level 2 (and levels 3,4) Copyright 1993: T. Ytterdal, K. Lee, M. Shur and T. A. Fjeldly
to be written
M. Shur, T.A. Fjeldly, T. Ytterdal, K. Lee, "Unified GaAs MESFET Model for Circuit Simulation", Int. Journal of High Speed Electronics, vol. 3, no. 2, pp. 201-233, 1992

10.2.3

hfet1

level 5
to be written
no documentation available

10.2.4

hfet2

level6
to be written
no documentation available

Chapter 11
MOSFETs
Ngspice supports all the original mosfet models present in SPICE3f5 and almost all the newer
ones that have been published and made open-source. Both bulk and SOI (Silicon on Insulator) models are available. When compiled with the cider option, ngspice implements the four
terminals numerical model that can be used to simulate a MOSFET (please refer to numerical
modeling documentation for additional information and examples).

11.1

MOSFET devices

General form:
MXXXXXXX nd ng ns nb mname <m= v a l > < l = v a l > <w= v a l >
+ <ad= v a l > <as= v a l > <pd= v a l > <ps= v a l > <nrd= v a l >
+ < n r s = v a l > < o f f > < i c =vds , vgs , vbs > <temp= t >
Examples:
M1 24 2 0 20 TYPE1
M31 2 17 6 10 MOSN L=5U W=2U
M1 2 9 3 0 MOSP L=10U W=5U AD=100P AS=100P PD=40U PS=40U
Note the suffixes in the example: the suffix u specifies microns (1e-6 m) and p sq-microns
(1e-12 m2 ).
The instance card for MOS devices starts with the letter M. nd, ng, ns, and nb are the drain,
gate, source, and bulk (substrate) nodes, respectively. mname is the model name and m is the
multiplicity parameter, which simulates m paralleled devices. All MOS models support the
m multiplier parameter. Instance parameters l and w, channel length and width respectively,
are expressed in meters. The areas of drain and source diffusions: ad and as, in squared meters
(m2 ).
If any of l, w, ad, or as are not specified, default values are used. The use of defaults simplifies
input file preparation, as well as the editing required if device geometries are to be changed. pd
and ps are the perimeters of the drain and source junctions, in meters. nrd and nrs designate
the equivalent number of squares of the drain and source diffusions; these values multiply the
sheet resistance rsh specified on the .model control line for an accurate representation of the
parasitic series drain and source resistance of each transistor. pd and ps default to 0.0 while nrd

127

128

CHAPTER 11. MOSFETS

and nrs to 1.0. off indicates an (optional) initial condition on the device for dc analysis. The
(optional) initial condition specification using ic=vds,vgs,vbs is intended for use with the
uic option on the .tran control line, when a transient analysis is desired starting from other
than the quiescent operating point. See the .ic control line for a better and more convenient way
to specify transient initial conditions. The (optional) temp value is the temperature at which this
device is to operate, and overrides the temperature specification on the .option control line.
The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4
or 5 (BSIM) devices.
BSIM3.2 version is also supporting the instance parameter delvto and mulu0 for local mismatch and NBTI (negative bias temperature instability) modeling:
Name
delvto
mulu0

11.2

Parameter
Threshold voltage shift
Low-field mobility multiplier (U0)

Units
V
-

Default
0.0
1.0

Example
0.07
0.9

MOSFET models (NMOS/PMOS)

MOSFET models are the central part of ngspice, probably because they are the most widely
used devices in the electronics world. Ngspice provides all the MOSFETs implemented in the
original Spice3f and adds several models developed by UC Berkeleys Device Group and other
independent groups.
Each model is invoked with a .model card. A minimal version is:
.model MOSN NMOS level=8 version=3.3.0
The model name MOSN corresponds to the model name in the instance card (see 11.1). Parameter NMOS selects an n-channel device, PMOS would point to a p-channel transistor. The
level and version parameters select the specific model. Further model parameters are optional and replace ngspice default values. Due to the large number of parameters (more than
100 for modern models), model cards may be stored in extra files and loaded into the netlist by
the .include (2.6) command. Model cards are specific for a an IC manufacturing process and
are typically provided by the IC foundry. Some generic parameter sets, not linked to a specific
process, are made available by the model developers, e.g. UC Berkeleys Device Group for
BSIM4 and BSIMSOI.
Ngspice provides several MOSFET device models, which differ in the formulation of the I-V
characteristic, and are of varying complexity. Models available are listed in table 11.1. Current
models for IC design are BSIM3 (11.2.9, down to channel length of 0.35 m), BSIM4 (11.2.10,
below 0.35 m), BSIMSOI (11.2.12, silicon-on-insulator devices), HiSIM2 and HiSIM_HV
(11.2.14, surface potential models for standard and high voltage/high power MOS devices).

11.2.1

MOS Level 1

This model is also known as the Shichman-Hodges model. This is the first model written and
the one often described in the introductory textbooks for electronics. This model is applicable
only to long channel devices. The use of Meyers model for the C-V part makes it non charge
conserving.

Level
1
2
3
4
5
6
9
8, 49
8, 49
8, 49
8, 49
10, 58
14, 54
14, 54
14, 54
14, 54
44
45
55
56
57
60
61, 68
62, 73

Name
MOS1
MOS2
MOS3
BSIM1
BSIM2
MOS6
MOS9
BSIM3v0
BSIM3v1
BSIM3v32
BSIM3
B4SOI
BSIM4v4
BSIM4v5
BSIM4v6
BSIM4
EKV
PSP
B3SOIFD
B3SOIDD
B3SOIPD
STAG
HiSIM2
HiSIM_HV

Model
Shichman-Hodges
Grove-Frhoman

Table 11.1: MOSFET model summary


SOI3
2.7.0
1.2.2

1.0.2

3.0
3.1
3.2 - 3.2.4
3.3.0
4.3.1
4.0 - 4.4
4.5.0
4.6.5
4.7.0

Version
-

Developer
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Alan Gillespie
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
EPFL
Gildenblatt
Berkeley
Berkeley
Berkeley
Southampton
Hiroshima
Hiroshima

References

High Voltage Version for LDMOS

adms configured
adms configured

Multi version code

extensions by Alan Gillespie


extensions by Serban Popescu
Multi version code
Described in [13]

Notes
This is the classical quadratic model.
Described in [2]
A semi-empirical model (see [1])
Described in [3]
Described in [5]
Described in [2]

11.2. MOSFET MODELS (NMOS/PMOS)


129

130

11.2.2

CHAPTER 11. MOSFETS

MOS Level 2

This model tries to overcome the limitations of the Level 1 model addressing several shortchannel effects, like velocity saturation. The implementation of this model is complicated and
this leads to many convergence problems. C-V calculations can be done with the original Meyer
model (non charge conserving).

11.2.3

MOS Level 3

This is a semi-empirical model derived from the Level 2 model. In the 80s this model has often
been used for digital design and, over the years, has proved to be robust. A discontinuity in the
model with respect to the KAPPA parameter has been detected (see [10]). The supplied fix has
been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option
badmos3 may be set to use the old implementation (see the section on simulation variables
and the .options line). Ngspice level 3 implementation takes into account length and width
mask adjustments (xl and xw) and device width narrowing due to diffusion (wd).

11.2.4

MOS Level 6

This model is described in [2]. The model can express the current characteristics of shortchannel MOSFETs at least down to 0. 25 m channel-length, GaAs FET, and resistance inserted
MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 mos
level 3 model. The model also enables analytical treatments of circuits in short-channel region
and makes up for a missing link between a complicated MOSFET current characteristics and
circuit behaviors in the deep submicron region.

11.2.5

Notes on Level 1-6 models

The dc characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters vto, kp, lambda, phi and gamma. These parameters are computed by ngspice if process
parameters (nsub, tox, ...) are given, but users specified values always override. vto is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel
(P-channel) devices.
Charge storage is modeled by three constant capacitors, cgso, cgdo, and cgbo which represent
overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the
gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both
substrate junctions divided into bottom and periphery, which vary as the mj and mjsw power
of junction voltage respectively, and are determined by the parameters cbd, cbs, cj, cjsw, mj,
mjsw and pb.
Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance
model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the level 1 model. These voltage-dependent capacitances are included only if tox is
specified in the input description and they are represented using Meyers formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current
can be input either as is (in A) or as js (in A/m2 ). Whereas the first is an absolute value the

11.2. MOSFET MODELS (NMOS/PMOS)

131

second is multiplied by ad and as to give the reverse current of the drain and source junctions
respectively.
This methodology has been chosen since there is no sense in relating always junction characteristics with ad and as entered on the device line; the areas can be defaulted. The same idea
applies also to the zero-bias junction capacitances cbd and cbs (in F) on one hand, and cj (in
F/m2 ) on the other.
The parasitic drain and source series resistance can be expressed as either rd and rs (in ohms)
or rsh (in ohms/sq.), the latter being multiplied by the number of squares nrd and nrs input on
the device line.
NGSPICE level 1, 2, 3 and 6 parameters

Name
LEVEL
VTO
KP
GAMMA
PHI
LAMBDA

RD
RS
CBD
CBS
IS
PB
CGSO

CGDO

CGBO

RSH

Parameter
Model index
Zero-bias threshold voltage
(VT 0 )
Transconductance
parameter
Bulk threshold parameter
Surface potential (U)
Channel length modulation
(MOS1 and MOS2 only)
( )
Drain ohmic resistance
Source ohmic resistance
Zero-bias B-D junction
capacitance
Zero-bias B-S junction
capacitance
Bulk junction saturation
current (IS )
Bulk junction potential
Gate-source overlap
capacitance per meter
channel width
Gate-drain overlap
capacitance per meter
channel width
Gate-bulk overlap
capacitance per meter
channel width
Drain and source diffusion
sheet resistance

Units
V

Default
1
0.0

Example

A/V 2

2.0e-5

3.1e-5

V
V
1/V

0.0
0.6
0.0

0.37
0.65
0.02

0.0
0.0
0.0

1.0
1.0
20fF

0.0

20fF

1.0e-14

1.0e-15

V
F/m

0.8
0.0

0.87
4.0e-11

F/m

0.0

4.0e-11

F/m

0.0

2.0e-11

/

0.0

10

1.0

132

CHAPTER 11. MOSFETS


Name
CJ

MJ
CJSW

MJSW
JS
TOX
NSUB
NSS
NFS
TPG

XJ
LD
UO
UCRIT
UEXP

UTRA

VMAX
NEFF

KF
AF
FC

DELTA
THETA
ETA

Parameter
Zero-bias bulk junction
bottom cap. per sq-meter of
junction area
Bulk junction bottom
grading coeff.
Zero-bias bulk junction
sidewall cap. per meter of
junction perimeter

Units
F/m2

Default
0.0

Example
2.0e-4

0.5

0.5

F/m

0.0

1.0e-9

Bulk junction sidewall


grading coeff.
Bulk junction saturation
current
Oxide thickness
Substrate doping
Surface state density
Fast surface state density
Type of gate material: +1
opp. to substrate, -1 same as
substrate, 0 Al gate
Metallurgical junction depth
Lateral diffusion
Surface mobility
Critical field for mobility
degradation (MOS2 only)
Critical field exponent in
mobility degradation
(MOS2 only)
Transverse field coeff.
(mobility) (deleted for
MOS2)
Maximum drift velocity of
carriers
Total channel-charge (fixed
and mobile) coefficient
(MOS2 only)
Flicker noise coefficient
Flicker noise exponent
Coefficient for forward-bias
depletion capacitance
formula
Width effect on threshold
voltage (MOS2 and MOS3)
Mobility modulation
(MOS3 only)
Static feedback (MOS3
only)

0.50 (level1)
0.33 (level2, 3)

m
cm3
cm2
cm2
-

1.0e-7
0.0
0.0
0.0
1.0

1.0e-7
4.0e15
1.0e10
1.0e10

m
m
2
cm /V sec
V/cm

0.0
0.0
600
1.0e4

1M
0.8M
700
1.0e4

0.0

0.1

0.0

0.3

m/s

0.0

5.0e4

1.0

5.0

0.0
1.0
0.5

1.0e-26
1.2

0.0

1.0

1/V

0.0

0.1

0.0

1.0

11.2. MOSFET MODELS (NMOS/PMOS)


Name
KAPPA
TNOM

11.2.6

133

Parameter
Saturation field factor
(MOS3 only)
Parameter measurement
temperature

Units
-

Default
0.2

Example
0.5

27

50

BSIM Models

Ngspice implements many of the BSIM models developed by Berkeleys BSIM group. BSIM
stands for Berkeley Short-Channel IGFET Model and groups a class of models that is continuously updated. In general, all parameters of BSIM models are obtained from process characterization, in particular level 4 and level 5 (BSIM1 and BSIM2) parameters are can be generated
automatically. J. Pierret [4] describes a means of generating a process file, and the program
ngproc2mod provided with ngspice converts this file into a sequence of BSIM1 .model lines
suitable for inclusion in an ngspice input file.
Parameters marked below with an * in the l/w column also have corresponding parameters with
a length and width dependency. For example, vfb is the basic parameter with units of Volts,
and lvfb and wvfb also exist and have units of Volt-meter.
The formula
P = P0 +

PL
Leffective

PW
Weffective

(11.1)

is used to evaluate the parameter for the actual device specified with
Leffective = Linput DL

(11.2)

Weffective = Winput DW

(11.3)

Note that unlike the other models in ngspice, the BSIM models are designed for use with a
process characterization system that provides all the parameters, thus there are no defaults for
the parameters, and leaving one out is considered an error. For an example set of parameters
and the format of a process file, see the SPICE2 implementation notes[3]. For more information
on BSIM2, see reference [5]. BSIM3 (11.2.9) and BSIM4 (11.2.10) represent state of the art
for submicron and deep submicron IC design.

11.2.7

BSIM1 model (level 4)

BSIM1 model (the first is a long series) is an empirical model. Developers placed less emphasis on device physics and based the model on parametrical polynomial equations to model the
various physical effects. This approach pays in terms of circuit simulation behavior but the accuracy degrades in the submicron region. A known problem of this model is the negative output
conductance and the convergence problems, both related to poor behavior of the polynomial
equations.

134
Ngspice BSIM (level 4) parameters

CHAPTER 11. MOSFETS

11.2. MOSFET MODELS (NMOS/PMOS)


Name
VFB
PHI
K1
K2
ETA
MUZ
DL
DW
U0
U1
X2MZ
X2E
X3E
X2U0
X2U1
MUS
X2MS
X3MS
X3U1
TOX
TEMP
VDD
CGDO
CGSO
CGBO
XPART
N0
NB
ND
RSH
JS
PB
MJ

Parameter
Flat-band voltage
Surface inversion potential
Body effect coefficient
Drain/source depletion charge-sharing
coefficient
Zero-bias drain-induced barrier-lowering
coefficient
Zero-bias mobility
Shortening of channel
Narrowing of channel
Zero-bias transverse-field mobility degradation
coefficient
Zero-bias velocity saturation coefficient
Sens. of mobility to substrate bias at v=0
Sens. of drain-induced barrier lowering effect
to substrate bias
Sens. of drain-induced barrier lowering effect
to drain bias at Vds = Vdd
Sens. of transverse field mobility degradation
effect to substrate bias
Sens. of velocity saturation effect to substrate
bias
Mobility at zero substrate bias and at Vds = Vdd
Sens. of mobility to substrate bias at Vds = Vdd
Sens. of mobility to drain bias at Vds = Vdd
Sens. of velocity saturation effect on drain bias
at Vds=Vdd
Gate oxide thickness
Temperature at which parameters were
measured
Measurement bias range
Gate-drain overlap capacitance per meter
channel width
Gate-source overlap capacitance per meter
channel width
Gate-bulk overlap capacitance per meter
channel length
Gate-oxide capacitance-charge model flag
Zero-bias subthreshold slope coefficient
Sens. of subthreshold slope to substrate bias
Sens. of subthreshold slope to drain bias
Drain and source diffusion sheet resistance
Source drain junction current density
Built in potential of source drain junction
Grading coefficient of source drain junction

135
Units
V
V
V
-

l/w
*
*
*
*

cm2/V sec

m
m
1/V
/V

/V 2 sec
1/V

*
*
*

1/V

1/V 2

m/V 2

cm2

cm2/V 2 sec
cm2/V 2 sec
cm2/V 2 sec
m/V 2

*
*
*

m
C
V
F/m
F/m
F/m

/
A/m2
V
-

*
*
*

136

CHAPTER 11. MOSFETS


Name
PBSW
MJSW
CJ
CJSW
WDF
DELL

Parameter
Built in potential of source, drain junction
sidewall
Grading coefficient of source drain junction
sidewall
Source drain junction capacitance per unit area
source drain junction sidewall capacitance per
unit length
Source drain junction default width
Source drain junction length reduction

Units
V

l/w

F/m2
F/m

m
m

xpart = 0 selects a 40/60 drain/source charge partition in saturation, while xpart=1 selects
a 0/100 drain/source charge partition. nd, ng, and ns are the drain, gate, and source nodes,
respectively. mname is the model name, area is the area factor, and off indicates an (optional)
initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is
assumed. The (optional) initial condition specification, using ic=vds,vgs is intended for use
with the uic option on the .tran control line, when a transient analysis is desired starting from
other than the quiescent operating point. See the .ic control line for a better way to set initial
conditions.

11.2.8

BSIM2 model (level 5)

This model contains many improvements over BSIM1 and is suitable for analog simulation.
Nevertheless, even BSIM2 breaks transistor operation into several distinct regions and this leads
to discontinuities in the first derivative in C-V and I-V characteristics that can cause numerical
problems during simulation.

11.2.9

BSIM3 model (levels 8, 49)

BSIM3 solves the numerical problems of previous models with the introduction of smoothing
functions. It adopts a single equation to describe device characteristics in the operating regions.
This approach eliminates the discontinuities in the I-V and C-V characteristics. The original model, BSIM3 evolved through three versions: BSIM3v1, BSIM3v2 and BSIM3v3. Both
BSIM3v1 and BSIM3v2 had suffered from many mathematical problems and were replaced by
BSIM3v3. The latter is the only surviving release and has itself a long revision history
The following table summarizes the story of this model:
Release
BSIM3v3.0
BSIM3v3.1
BSIM3v3.2

Date
10/30/1995
12/09/1996
06/16/1998

BSIM3v3.3

07/29/2005

Notes

Revisions available: BSIM3v3.2.2,


BSIM3v3.2.3, and BSIM3v3.2.4
Parallel processing with OpenMP is available
for this model.

Version flag
3.0
3.1
3.2, 3.2.2,
3.2.3, 3.2.4
3.3.0

BSIM3v2 and 3v3 models has proved for accurate use in 0.18 m technologies. The model is
publicly available as source code form from University of California, Berkeley.

11.2. MOSFET MODELS (NMOS/PMOS)

137

A detailed description is given in the users manual available from here .


We recommend that you use only the most recent BSIM3 model (version 3.3.0), because it
contains corrections to all known bugs. To achieve that, change the version parameter in your
modelcard files to
VERSION = 3.3.0.
If no version number is given in the .model card, this (newest) version is selected as the default.
The older models will not be supported, they are made available for reference only.

11.2.10

BSIM4 model (levels 14, 54)

This is the newest class of the BSIM family and introduces noise modeling and extrinsic parasitics. BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into
sub-100nm regime. It is a physics-based, accurate, scalable, robust and predictive MOSFET
SPICE model for circuit simulation and CMOS technology development. It is developed by
the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences
(EECS) at the University of California, Berkeley (see BSIM4 home page). BSIM4 has a long
revision history, which is summarized below.
Release
BSIM4.0.0
BSIM4.1.0
BSIM4.2.0
BSIM4.2.1
BSIM4.3.0
BSIM4.4.0
BSIM4.5.0
BSIM4.6.0
...
BSIM4.6.5
BSIM4.7.0

Date
03/24/2000
10/11/2000
04/06/2001
10/05/2001
05/09/2003
03/04/2004
07/29/2005
12/13/2006

Notes

Version flag

*
*
*
*

4.2.1
4.3.0
4.4.0
4.5.0

09/09/2009
04/08/2011

* **
* **

4.6.5
4.7

*) supported in ngspice, using e.g. the version=<version flag> flag in the parameter file.
**) Parallel processing using OpenMP support is available for this model.
Details of any revision are to be found in the Berkeley users manuals, a pdf download of the
most recent edition is to be found here .
We recommend that you use only the most recent BSIM4 model (version 4.7.0), because it
contains corrections to all known bugs. To achieve that, change the version parameter in your
modelcard files to
VERSION = 4.7.
If no version number is given in the .model card, this (newest) version is selected as the default.
The older models will typically not be supported, they are made available for reference only.

11.2.11

EKV model

Level 44 model (EKV) is not available in the standard distribution since it is not released in
source form by the EKV group. To obtain the code please refer to the (EKV model home page,

138

CHAPTER 11. MOSFETS

EKV group home page). A verilog-A version is available contributed by Ivan Riis Nielsen
11/2006.

11.2.12

BSIMSOI models (levels 10, 58, 55, 56, 57)

BSIMSOI is a SPICE compact model for SOI (Silicon-On-Insulator) circuit design, created by
University of California at Berkeley . This model is formulated on top of the BSIM3 framework. It shares the same basic equations with the bulk model so that the physical nature and
smoothness of BSIM3v3 are retained. Four models are supported in ngspice, those based on
BSIM3 and modeling fully depleted (FD, level 55), partially depleted (PD, level 57) and both
(DD, level 56), as well as the modern BSIMSOI version 4 model (levels 10, 58). Detailed descriptions are beyond the scope of this manual, but see e.g. BSIMSOIv4.4 User Manual for a
very extensive description of the recent model version. OpenMP support is available for levels
10, 58, version 4.4.

11.2.13

SOI3 model (level 60)

see literature citation [18] for a description.

11.2.14

HiSIM models of the University of Hiroshima

There are two model implementations available - see also HiSIM Research Center:
1. HiSIM2 model: Surface-Potential-Based MOSFET Model for Circuit Simulation version
2.7.0 - level 61 & 68 (see link to HiSIM2 for source code and manual).
2. HiSIM_HV model: Surface-Potential-Based HV/LD-MOSFET Model for Circuit Simulation version 1.2.2 - level 62 & 73 (see link to HiSIM_HV for source code and manual).

Chapter 12
Mixed-Mode and Behavioral Modeling
with XSPICE
Ngspice implements XSPICE extensions for behavioral and mixed-mode (analog and digital)
modeling. In the XSPICE framework this is referred to as code level modeling. Behavioral
modeling may benefit dramatically because XSPICE offers a means to add analog functionality
programmed in C. Many examples (amplifiers, oscillators, filters ...) are presented in the following. Even more flexibility is available because you may define your own models and use them
in addition and in combination with all the already existing ngspice functionality. Mixed mode
simulation is speeded up significantly by simulating the digital part in an event driven manner,
in that state equations use only a few allowed states and are evaluated only during switching,
and not continuously in time and signal as in a pure analog simulator.
This chapter describes the predefined models available in ngspice, stemming from the original
XSPICE simulator. The instructions for writing new code models are given in chapter 28.
To make use of the XSPICE extensions, you need to compile them in. LINUX, CYGWIN,
MINGW and other users may add the flag --enable-xspice to their ./configure command
and then recompile. The prebuilt ngspice for Windows distribution has XSPICE already enabled. For detailed compiling instructions see chapter 32.1.

12.1

Code Model Element & .MODEL Cards

Ngspice includes a library of predefined Code Models that can be placed within any circuit
description in a manner similar to that used to place standard device models. Code model
instance cards always begin with the letter A, and always make use of a .MODEL card to
describe the code model desired. Section 28 of this document goes into greater detail as to how
a code model similar to the predefined models may be developed, but once any model is created
and linked into the simulator it may be placed using one instance card and one .MODEL card
(note here we conform to the SPICE custom of referring to a single logical line of information
as a card). As an example, the following uses the predefined gain code model which takes
as an input some value on node 1, multiplies it by a gain of 5.0, and outputs the new value to
node 2. Note that, by convention, input ports are specified first on code models. Output ports
follow the inputs.

139

140

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Example:
a1 1 2 amp
. model amp gain ( gain =5.0)

In this example the numerical values picked up from single-ended (i.e. ground referenced)
input node 1 and output to single-ended output node 2 will be voltages, since in the Interface
Specification File for this code model (i.e., gain), the default port type is specified as a voltage
(more on this later). However, if you didnt know this, the following modifications to the
instance card could be used to insure it:

Example:
a1 % v (1) % v (2) amp
. model amp gain ( gain =5.0)
The specification "%v" preceding the input and output node numbers of the instance card indicate to the simulator that the inputs to the model should be single-ended voltage values. Other
possibilities exist, as described later.
Some of the other features of the instance and .MODEL cards are worth noting. Of particular
interest is the portion of the .MODEL card which specifies gain=5.0. This portion of the
card assigns a value to a parameter of the "gain" model. There are other parameters which can
be assigned values for this model, and in general code models will have several. In addition
to numeric values, code model parameters can take non-numeric values (such as TRUE and
FALSE), and even vector values. All of these topics will be discussed at length in the following
pages. In general, however, the instance and .MODEL cards which define a code model will
follow the abstract form described below. This form illustrates that the number of inputs and
outputs and the number of parameters which can be specified is relatively open-ended and can be
interpreted in a variety of ways (note that angle-brackets < and > enclose optional inputs):

Example:
AXXXXXXX <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd , or %d >
+ <[ > <~ > <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd , or %d >
+ < NIN1 or + NIN1 - NIN1 or " null " >
+ <~ >... < NIN2 .. <] > >
+ <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd ,% d or % vnam >
+ <[ > <~ > <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd ,
or %d > < NOUT1 or + NOUT1 - NOUT1 >
+ <~ >... < NOUT2 .. <] > >
+ MODELNAME
. MODEL MODELNAME MODELTYPE
+ <( PARAMNAME1 = <[ > VAL1 < VAL2 ... <] > > PARAMNAME2 .. >) >

12.1. CODE MODEL ELEMENT & .MODEL CARDS

141

Square brackets ([ ]) are used to enclose vector input nodes. In addition, these brackets are used
to delineate vectors of parameters.
The literal string null, when included in a node list, is interpreted as no connection at that input
to the model. "Null" is not allowed as the name of a models input or output if the model only
has one input or one output. Also, null should only be used to indicate a missing connection
for a code model; use on other XSPICE component is not interpreted as a missing connection,
but will be interpreted as an actual node name.
The tilde, ~, when prepended to a digital node name, specifies that the logical value of that
node be inverted prior to being passed to the code model. This allows for simple inversion of
input and output polarities of a digital model in order to handle logically equivalent cases and
others that frequently arise in digital system design. The following example defines a NAND
gate, one input of which is inverted:

a1 [~1 2] 3 nand1
. model nand1 d_nand ( rise_delay =0.1 fall_delay =0.2)
The optional symbols %v, %i, %vd, etc. specify the type of port the simulator is to expect for
the subsequent port or port vector. The meaning of each symbol is given in Table 12.1.
The symbols described in Table 12.1 may be omitted if the default port type for the model is
desired. Note that non-default port types for multi-input or multi-output (vector) ports must be
specified by placing one of the symbols in front of EACH vector port. On the other hand, if all
ports of a vector port are to be declared as having the same non-default type, then a symbol may
be specified immediately prior to the opening bracket of the vector. The following examples
should make this clear:

Example 1: - Specifies two differential voltage connections, one


to nodes 1 & 2, and one to nodes 3 & 4.
%vd [1 2 3 4]
Example 2: - Specifies two single-ended connections to node 1 and
at node 2, and one differential connection to
nodes 3 & 4.
%v [1 2 %vd 3 4]
Example 3: - Identical to the previous example...parenthesis
are added for additional clarity.
%v [1 2 %vd(3 4)]
Example 4: - Specifies that the node numbers are to be treated in the
default fashion for the particular model.
If this model had %v as a default for this
port, then this notation would represent four single-ended
voltage connections.
[1 2 3 4]

142

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Port Type Modifiers


Modifier
%v
%i
%g

%h

%d
%vnam

%vd
%id
%gd
%hd

Interpretation
represents a single-ended voltage port - one node name or number is expected
for each port.
represents a single-ended current port - one node name or number is expected
for each port.
represents a single-ended voltage-input, current-output (VCCS) port - one
node name or number is expected for each port. This type of port is automatically an input/output.
represents a single-ended current-input, voltage-output (CCVS) port - one
node name or number is expected for each port. This type of port is automatically an input/output.
represents a digital port - one node name or number is expected for each port.
This type of port may be either an input or an output.
represents the name of a voltage source, the current through which is taken as
an input. This notation is provided primarily in order to allow models defined
using SPICE2G6 syntax to operate properly in XSPICE.
represents a differential voltage port - two node names or numbers are expected for each port.
represents a differential current port - two node names or numbers are expected for each port.
represents a differential VCCS port - two node names or numbers are expected
for each port.
represents a differential CCVS port - two node names or numbers are expected
for each port.
Table 12.1: Port Type Modifiers

12.2. ANALOG MODELS

143

The parameter names listed on the .MODEL card must be identical to those named in the code
model itself. The parameters for each predefined code model are described in detail in Sections
12.2 (analog), 12.3 (Hybrid, A/D) and 12.4 (digital) . The steps required in order to specify
parameters for user-defined models are described in Chapter 28.
The following is a list of instance card and associated .MODEL card examples showing use of
predefined models within an XSPICE deck:
a1 1 2 amp
.model amp gain(in_offset=0.1 gain=5.0 out_offset=-0.01)
a2 %i[1 2] 3 sum1
.model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0]
+ out_gain=5.0 out_offset=-0.01)
a21 %i[1 %vd(2 5) 7 10] 3 sum2
.model sum2 summer(out_gain=10.0)
a5 1 2 limit5 .model limit5 limit(in_offset=0.1 gain=2.5
+ out_lower.limit=-5.0 out_upper_limit=5.0 limit_domain=0.10
+ fraction=FALSE)
a7 2 %id(4 7) xfer.cntl1
.model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0]
+ y_array=[-0.2 -0.2 0.1 2.0 10.0]
+ input_domain=0.05 fraction=TRUE)
a8 3 %gd(6 7) switch3
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
+ r_on=10.0 log=TRUE)

12.2

Analog Models

The following analog models are supplied with XSPICE. The descriptions included consist
of the model Interface Specification File and a description of the models operation. This is
followed by an example of a simulator-deck placement of the model, including the .MODEL
card and the specification of all available parameters.

12.2.1

Gain

NAME_TABLE :
C_Function_Name :
Spice_Model_Name :
Description :

cm_gain
gain
" A simple gain block "

PORT_TABLE :
Port Name :
Description :
Direction :
Default_Type :
Allowed_Types :
Vector :

in
" input "
in
v
[v , vd ,i , id , vnam ]
no

out
" output "
out
v
[v , vd ,i , id ]
no

144

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector . Bounds :
Null . Allowed :

no

PARAMETER_TABLE :
Parameter_Name :
Description :
Data_Type :
Default_Value :
Limits :
Vector :
Vector_Bounds :
Null_Allowed :

in_offset
" input offset "
real
0.0
no
yes

no

gain
" gain "
real
1.0
no
yes

out_offset
" output offset "
real
0.0
no
yes

Description: This function is a simple gain block with optional offsets on the input and the
output. The input offset is added to the input, the sum is then multiplied by the gain, and
the result is produced by adding the output offset. This model will operate in DC, AC,
and Transient analysis modes.

Example:

a1 1 2 amp
. model amp gain ( in_offset =0.1 gain =5.0
+ out_offset = -0.01)

12.2.2

Summer

NAME_TABLE :
C_Function_Name :
Spice_Model_Name :
Description :

cm_summer
summer
" A summer block "

PORT_TABLE :
Port Name :
Description :
Direction :
Default_Type :
Allowed_Types :
Vector :
Vector_Bounds :
Null_Allowed :

in
" input vector "
in
v
[v , vd ,i , id , vnam ]
yes
no

PARAMETER_TABLE :
Parameter_Name :
Description :
Data_Type :

in_offset
" input offset vector "
real

out
" output "
out
v
[v , vd ,i , id ]
no
no

in_gain
" input gain vector "
real

12.2. ANALOG MODELS

145

Default_Value :
Limits :
Vector :
Vector_Bounds :
Null_Allowed :

0.0
yes
in
yes

1.0
yes
in
yes

PARAMETER_TABLE :
Parameter_Name :
Description :
Data_Type :
Default_Value :
Limits :
Vector :
Vector_Bounds :
Null_Allowed :

out_gain
" output gain "
real
1.0
no
yes

out_offset
" output offset "
real
0.0
no
yes

Description: This function is a summer block with 2-to-N input ports. Individual gains and
offsets can be applied to each input and to the output. Each input is added to its respective
offset and then multiplied by its gain. The results are then summed, multiplied by the
output gain and added to the output offset. This model will operate in DC, AC, and
Transient analysis modes.
Example usage:
a2 [1 2] 3 sum1
. model sum1 summer ( in_offset =[0.1 -0.2] in_gain =[2.0 1.0]
+ out_gain =5.0 out_offset = -0.01)

12.2.3

Multiplier

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:

cm_mult
mult
"multiplier block"
in
"input vector"
in
v
[v,vd,i,id,vnam]
yes
[2 -]
no

out
"output"
out
v
[v,vd,i,id]
no
no

in_offset

in_gain

146

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

"input offset vector"


real
0.0
yes
in
yes

"input gain vector"


real
1.0
yes
in
yes

out_gain
"output gain"
real
1.0
no
yes

out_offset
"output offset"
real
0.0
no
yes

Description: This function is a multiplier block with 2-to-N input ports. Individual gains and
offsets can be applied to each input and to the output. Each input is added to its respective
offset and then multiplied by its gain. The results are multiplied along with the output
gain and are added to the output offset. This model will operate in DC, AC, and Transient
analysis modes. However, in ac analysis it is important to remember that results are
invalid unless only ONE INPUT of the multiplier is connected to a node which bears
an AC signal (this is exemplified by the use of a multiplier to perform a potentiometer
function: one input is DC, the other carries the AC signal).

Example SPICE Usage:


a3 [1 2 3] 4 sigmult
. model sigmult mult ( in_offset =[0.1 0.1 -0.1]
+ in_gain =[10.0 10.0 10.0] out_gain =5.0 out_offset =0.05)

12.2.4

Divider

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:

cm_divide
divide
"divider block"
num
"numerator"
in
v
[v,vd,i,id,vnam]
no
-

den
"denominator"
in
v
[v,vd,i,id,vnam]
no
-

out
"output"
out
v
[v,vd,i,id]
no
-

12.2. ANALOG MODELS

Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:

147

no

no

num_offset
"numerator offset"
real
0.0
no
yes

num_gain
"numerator gain"
real
1.0
no
yes

den_offset
"denominator offset"
real
0.0
no
yes

den_gain
"denominator gain"
real
1.0
no
yes

den_lower_limit
"denominator lower limit"
real
1.0e-10
no
yes
den_domain
"denominator smoothing domain"
real
1.0e-10
no
yes
fraction
"smoothing fraction/absolute value switch"
boolean
false
no
yes
out_gain

out_offset

no

148

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

"output gain"
real
1.0
no
yes

"output offset"
real
0.0
no
yes

Description: This function is a two-quadrant divider. It takes two inputs; num (numerator) and
den (denominator). Divide offsets its inputs, multiplies them by their respective gains,
divides the results, multiplies the quotient by the output gain, and offsets the result. The
denominator is limited to a value above zero via a user specified lower limit. This limit is
approached through a quadratic smoothing function, the domain of which may be specified as a fraction of the lower limit value (default), or as an absolute value. This model
will operate in DC, AC and Transient analysis modes. However, in ac analysis it is important to remember that results are invalid unless only ONE INPUT of the divider is
connected to a node which bears an AC signal (this is exemplified by the use of the divider to perform a potentiometer function: one input is DC, the other carries the AC
signal).
Example SPICE Usage:
a4 1 2 4 divider
.model divider divide(num_offset=0.1 num_gain=2.5 den_offset=-0.1
+ den_gain=5.0 den_lower.limit=1e-5 den_domain=1e-6
+ fraction=FALSE out_gain=1.0 out_offset=0.0)

12.2.5

Limiter

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

cm_limit
limit
"limit block"
in
"input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

in_offset
"input offset"
real
0.0
no

gain
"gain"
real
1.0
no

12.2. ANALOG MODELS

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

149

yes

yes

out_lower_limit
"output lower limit"
real
0.0
no
yes

out_upper_limit
"output upper limit"
real
1.0
no
yes

limit_range
"upper & lower smoothing range"
real
1.0e-6
no
yes
fraction
"smoothing fraction/absolute value switch"
boolean
FALSE
no
yes

Description: The Limiter is a single input, single output function similar to the Gain Block.
However, the output of the Limiter function is restricted to the range specified by the
output lower and upper limits. This model will operate in DC, AC and Transient analysis
modes. Note that the limit range is the value BELOW THE UPPER LIMIT AND ABOVE
THE LOWER LIMIT at which smoothing of the output begins. For this model, then, the
limit range represents the delta WITH RESPECT TO THE OUTPUT LEVEL at which
smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts,
the output will begin to smooth out at 0.9 volts, which occurs when the input value is at
0.4.
Example SPICE Usage:
a5 1 2 limit5
.model limit5 limit(in_offset=0.1 gain=2.5 out_lower_limit=-5.0
+ out_upper_limit=5.0 limit_range=0.10 fraction=FALSE)

12.2.6

Controlled Limiter

NAME_TABLE:

150

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

cm_climit
climit
"controlled limiter block"
in
"input"
in
v
[v,vd,i,id,vnam]
no
no

cntl_upper
"upper lim. control input"
in
v
[v,vd,i,id,vnam]
no
no

cntl_lower
"lower limit control input"
in
v
[v,vd,i,id,vnam]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

in_offset
"input offset"
real
0.0
no
yes

gain
"gain"
real
1.0
no
yes

upper_delta
"output upper delta"
real
0.0
no
yes

lower_delta
"output lower delta"
real
0.0
no
yes

limit_range
"upper & lower sm. range"
real
1.0e-6
no
yes

fraction
"smoothing %/abs switch"
boolean
FALSE
no
yes

12.2. ANALOG MODELS

151

Description: The Controlled Limiter is a single input, single output function similar to the Gain
Block. However, the output of the Limiter function is restricted to the range specified by
the output lower and upper limits. This model will operate in DC, AC, and Transient analysis modes. Note that the limit range is the value BELOW THE CNTL_UPPER LIMIT
AND ABOVE THE CNTL_LOWER LIMIT at which smoothing of the output begins
(minimum positive value of voltage must exist between the CNTL_UPPER input and the
CNTL_LOWER input at all times). For this model, then, the limit range represents the
delta WITH RESPECT TO THE OUTPUT LEVEL at which smoothing occurs. Thus,
for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the output will begin to
smooth out at 0.9 volts, which occurs when the input value is at 0.4. Note also that
the Controlled Limiter code tests the input values of cntl_lower and cntl_upper to make
sure that they are spaced far enough apart to guarantee the existence of a linear range between them. The range is calculated as the difference between (cntl_upper - upper_delta
- limit_range) and (cntl_lower + lower_delta + limit_range) and must be greater than or
equal to zero. Note that when the limit range is specified as a fractional value, the limit
range used in the above is taken as the calculated fraction of the difference between cntl
upper and cntl lower. Still, the potential exists for too great a limit range value to be
specified for proper operation, in which case the model will return an error message.
Example SPICE Usage:
a6 3 6 8 4 varlimit
.
.
.model varlimit climit(in_offset=0.1 gain=2.5 upper_delta=0.0
+ lower_delta=0.0 limit_range=0.10 fraction=FALSE)

12.2.7

PWL Controlled Source

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

cm_pwl
pwl
"piecewise linear controlled source"
in
"input"
in
v
[v,vd,i,id,vnam]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

x_array
"x-element array"
real
yes

y_array
"y-element array"
real
yes

152

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
STATIC_VAR_TABLE:
Static_Var_Name:
Data_Type:

[2 -]
no

[2 -]
no

input_domain
"input sm. domain"
real
0.01
[1e-12 0.5]
no
yes

fraction
"smoothing %/abs switch"
boolean
TRUE
no
yes

last_x_value
pointer Description: "iteration holding
variable for limiting"

Description: The Piece-Wise Linear Controlled Source is a single input, single output function similar to the Gain Block. However, the output of the PWL Source is not necessarily
linear for all values of input. Instead, it follows an I/O relationship specified by you via
the x_array and y_array coordinates. This is detailed below.
The x_array and y_array values represent vectors of coordinate points on the x and y axes,
respectively. The x_array values are progressively increasing input coordinate points, and
the associated y_array values represent the outputs at those points. There may be as few
as two (x_array[n], y_array[n]) pairs specified, or as many as memory and simulation
speed allow. This permits you to very finely approximate a non-linear function by capturing multiple input-output coordinate points.
Two aspects of the PWL Controlled Source warrant special attention. These are the handling of endpoints and the smoothing of the described transfer function near coordinate
points.
In order to fully specify outputs for values of in outside of the bounds of the PWL
function (i.e., less than x_array[0] or greater than x_array[n], where n is the largest userspecified coordinate index), the PWL Controlled Source model extends the slope found
between the lowest two coordinate pairs and the highest two coordinate pairs. This has
the effect of making the transfer function completely linear for in less than x_array[0]
and in greater than x_array[n]. It also has the potentially subtle effect of unrealistically
causing an output to reach a very large or small value for large inputs. You should thus
keep in mind that the PWL Source does not inherently provide a limiting capability.
In order to diminish the potential for non-convergence of simulations when using the
PWL block, a form of smoothing around the x_array, y_array coordinate points is necessary. This is due to the iterative nature of the simulator and its reliance on smooth first
derivatives of transfer functions in order to arrive at a matrix solution. Consequently, the
input_domain and fraction parameters are included to allow you some control over
the amount and nature of the smoothing performed.
Fraction is a switch that is either TRUE or FALSE. When TRUE (the default setting),
the simulator assumes that the specified input domain value is to be interpreted as a fractional figure. Otherwise, it is interpreted as an absolute value. Thus, if fraction=TRUE
and input_domain=0.10, The simulator assumes that the smoothing radius about each coordinate point is to be set equal to 10% of the length of either the x_array segment above

12.2. ANALOG MODELS

153

each coordinate point, or the x_array segment below each coordinate point. The specific
segment length chosen will be the smallest of these two for each coordinate point.
On the other hand, if fraction=FALSE and input=0.10, then the simulator will begin
smoothing the transfer function at 0.10 volts (or amperes) below each x_array coordinate and will continue the smoothing process for another 0.10 volts (or amperes) above
each x_array coordinate point. Since the overlap of smoothing domains is not allowed,
checking is done by the model to ensure that the specified input domain value is not excessive.
One subtle consequence of the use of the fraction=TRUE feature of the PWL Controlled
Source is that, in certain cases, you may inadvertently create extreme smoothing of functions by choosing inappropriate coordinate value points. This can be demonstrated by
considering a function described by three coordinate pairs, such as (-1,-1), (1,1), and
(2,1). In this case, with a 10% input_domain value specified (fraction=TRUE, input domain=0.10), you would expect to see rounding occur between in=0.9 and in=1.1, and
nowhere else. On the other hand, if you were to specify the same function using the
coordinate pairs (-100,-100), (1,1) and (201,1), you would find that rounding occurs between in=-19 and in=21. Clearly in the latter case the smoothing might cause an excessive
divergence from the intended linearity above and below in=1.
Example SPICE Usage:
a7 2 4 xfer_cntl1
.
.
.model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0]
+
y_array=[-0.2 -0.2 0.1 2.0 10.0]
+
input_domain=0.05 fraction=TRUE)

12.2.8

Filesource

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:

cm_filesource
filesource
"File Source"
out
"output"
out
v
[v,vd,i,id]
yes
[1 -]
no
timeoffset
"time offset"
real
0.0
-

timescale
"timescale"
real
1.0
-

154

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

no
yes

no
yes

timerelative
"relative time"
boolean
FALSE
no
yes

amplstep
"step amplitude"
boolean
FALSE
no
yes

amploffset
"ampl offset"
real
yes
[1 -]
yes

amplscale
"amplscale"
real
yes
[1 -]
yes

file
"file name"
string
"filesource.txt"
no
yes

Description: The File Source is similar to the Piece-Wise Linear Source, except that the waveform data is read from a file instead of being taken from parameter vectors.
The file format is line oriented ASCII. # and ; are comment characters; all characters from
a comment character until the end of the line are ignored.
Each line consists of two or more real values. The first value is the time; subsequent
values correspond to the outputs. Values are separated by spaces.
Time values are absolute and must be monotonically increasing, unless timerelative is set
to TRUE, in which case the values specify the interval between two samples and must be
positive. Waveforms may be scaled and shifted in the time dimension by setting timescale
and timeoffset.
Amplitudes can also be scaled and shifted using amplscale and amploffset. Amplitudes
are normally interpolated between two samples, unless amplstep is set to TRUE.
Note: The parameter filename in file="filename" has to give an absolute path or name a
file placed in an input directory specified with the environmental variable NGSPICE_INPUT_DIR
(see 16.7).

12.2. ANALOG MODELS

155

Example SPICE Usage:


a8 %vd([1 0 2 0]) filesrc
.
.
.model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1]
+
timeoffset=0 timescale=1
+
timerelative=false amplstep=false)

Example input file:


# name: sine.m
# two output ports
# column 1: time
# columns 2, 3: values
0 0 1
3.90625e-09 0.02454122852291229 0.9996988186962042
7.8125e-09 0.04906767432741801 0.9987954562051724
1.171875e-08 0.07356456359966743 0.9972904566786902
...

12.2.9

multi_input_pwl block

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:

cm_multi_input_pwl
multi_input_pwl
"multi_input_pwl block"
in
"input array"
in
vd
[vd,id]
yes
[2 -]
no

out
"output"
out
vd
[vd,id]
no
no

x
"x array"
real
0.0
yes
[2 -]
no

y
"y array"
real
0.0
yes
[2 -]
no

model
"model type"
string

156

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

"and"
no
yes

Description: Multi-input gate voltage controlled voltage source that supports and or or gating.
The xs and ys represent the piecewise linear variation of output (y) as a function of
input (x). Only one input determines the state of the outputs, seleczable by the parameter
model. and: the smallest value of all the inputs is chosen as the controlling input and
determines the output value, or: the smallest value of all the inputs is chosen as the
controlling input and determines the output value.
Example SPICE Usage:
a82 [1 0 2 0 3 0] 7 0 pwlm
.
.
.model pwlm multi_input_pwl((x_array=[-2.0 -1.0 2.0 4.0 5.0]
+
y_array=[-0.2 -0.2 0.1 2.0 10.0]
+
model="and")

12.2.10

Analog Switch

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:

cm_aswitch
aswitch
"analog switch"
cntl_in
"input"
in
v
[v,vd,i,id]
no
no

out
"resistive output"
out
gd
[gd]
no
no

cntl_off
cntl_on
"control off value" "control on value"
real
real
0.0
1.0
no
no
yes
yes
r_off
"off resistance"

log
"log/linear switch"

12.2. ANALOG MODELS

Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

157

real
1.0e12
no
yes

boolean
TRUE
no
yes

r_on
"on resistance"
real
1.0
no
yes

Description: The Analog Switch is a resistor that varies either logarithmically or linearly between specified values of a controlling input voltage or current. Note that the input is
not internally limited. Therefore, if the controlling signal exceeds the specified OFF state
or ON state value, the resistance may become excessively large or excessively small (in
the case of logarithmic dependence), or may become negative (in the case of linear dependence). For the experienced user, these excursions may prove valuable for modeling
certain devices, but in most cases you are advised to add limiting of the controlling input
if the possibility of excessive control value variation exists.
Example SPICE Usage:
a8 3 (6 7) switch3
.
.
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
+
r_on=10.0 log=TRUE)

12.2.11

Zener Diode

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:

cm_zener
zener
"zener diode"
z
"zener"
inout
gd
[gd]
no
no

158

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
STATIC_VAR_TABLE:
Static_Var_Name:
Data_Type:
Description:

v_breakdown
"breakdown voltage"
real
[1.0e-6 1.0e6]
no
no

i_breakdown
"breakdown current"
real
2.0e-2
[1.0e-9 -]
no
yes

i_sat
"saturation current"
real
1.0e-12
[1.0e-15 -]
no
yes

n_forward
"forward emission coefficient"
real
1.0
[0.1 10]
no
yes

limit_switch
"switch for on-board limiting (convergence aid)"
boolean
FALSE
no
yes
previous_voltage
pointer
"iteration holding variable for limiting"

Description: The Zener Diode models the DC characteristics of most zeners. This model
differs from the Diode/Rectifier by providing a user-defined dynamic resistance in the
reverse breakdown region. The forward characteristic is defined by only a single point,
since most data sheets for zener diodes do not give detailed characteristics in the forward
region.
The first three parameters define the DC characteristics of the zener in the breakdown
region and are usually explicitly given on the data sheet.
The saturation current refers to the relatively constant reverse current that is produced
when the voltage across the zener is negative, but breakdown has not been reached. The
reverse leakage current determines the slight increase in reverse current as the voltage
across the zener becomes more negative. It is modeled as a resistance parallel to the
zener with value v breakdown / i rev.
Note that the limit switch parameter engages an internal limiting function for the zener.
This can, in some cases, prevent the simulator from converging to an unrealistic solution
if the voltage across or current into the device is excessive. If use of this feature fails to
yield acceptable results, the convlimit option should be tried (add the following statement
to the SPICE input deck: .options convlimit)

12.2. ANALOG MODELS

159

Example SPICE Usage:


a9 3 4 vref10
.
.
.model vref10 zener(v_breakdown=10.0 i_breakdown=0.02
+
r_breakdown=1.0 i_rev=1e-6 i_sat=1e-12)

12.2.12

Current Limiter

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:

cm_ilimit
ilimit
"current limiter block"
in
"input"
in
v
[v,vd]
no
no

pos_pwr
"positive power supply"
inout
g
[g,gd]
no
yes

neg_pwr
"negative power supply"
inout
g
[g,gd]
no
yes

out
"output"
inout
g
[g,gd]
no
no

in_offset
"input offset"
real
0.0
no
yes

gain
"gain"
real
1.0
no
yes

r_out_source
"sourcing resistance"
real
1.0
[1.0e-9 1.0e9]
no
-

r_out_sink
"sinking resistance"
real
1.0
[1.0e-9 1.0e9]
no
-

160

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

yes

yes

i_limit_source
"current sourcing limit"
real
[1.0e-12 -]
no
yes
i_limit_sink
"current sinking limit"
real
[1.0e-12 -]
no
yes
v_pwr_range
"upper & lower power
supply smoothing range"
real
1.0e-6
[1.0e-15 -]
no
yes

i_source_range
"sourcing current
smoothing range"
real
1.0e-9
[1.0e-15 -]
no
yes

i_sink_range
"sinking current smoothing range"
real
1.0e-9
[1.0e-15 -]
no
yes
r_out_domain
"internal/external voltage delta smoothing range"
real
1.0e-9
[1.0e-15 -]
no
yes

Description: The Current Limiter models the behavior of an operational amplifier or compara-

12.2. ANALOG MODELS

161

tor device at a high level of abstraction. All of its pins act as inputs; three of the four
also act as outputs. The model takes as input a voltage value from the in connector. It
then applies an offset and a gain, and derives from it an equivalent internal voltage (veq),
which it limits to fall between pos pwr and neg pwr. If veq is greater than the output
voltage seen on the out connector, a sourcing current will flow from the output pin.
Conversely, if the voltage is less than vout, a sinking current will flow into the output pin.
Depending on the polarity of the current flow, either a sourcing or a sinking resistance
value (r_out_source, r_out_sink) is applied to govern the vout/i_out relationship. The
chosen resistance will continue to control the output current until it reaches a maximum
value specified by either i_limit_source or i_limit_sink. The latter mimics the current
limiting behavior of many operational amplifier output stages.
During all operation, the output current is reflected either in the pos_pwr connector current or the neg_pwr current, depending on the polarity of i_out. Thus, realistic power
consumption as seen in the supply rails is included in the model.
The user-specified smoothing parameters relate to model operation as follows: v_pwr_range
controls the voltage below vpos_pwr and above vneg_pwr inputs beyond which veq [=
gain * (vin + voffset)] is smoothed; i_source_range specifies the current below i_limit_source
at which smoothing begins, as well as specifying the current increment above i_out=0.0 at
which i_pos_pwr begins to transition to zero; i_sink_range serves the same purpose with
respect to i_limit_sink and i_neg_pwr that i_source_range serves for i_limit_source &
i_pos_pwr; r_out_domain specifies the incremental value above and below (veq-vout)=0.0
at which r_out will be set to r_out_source and r_out_sink, respectively. For values of
(veq-vout) less than r_out_domain and greater than -r_out_domain, r_out is interpolated
smoothly between r_out_source & r_out_sink.
Example SPICE Usage:
a10 3 10 20 4 amp3
.
.
.model amp3 ilimit(in_offset=0.0 gain=16.0 r_out_source=1.0
+
r_out_sink=1.0 i_limit_source=1e-3
+
i_limit_sink=10e-3 v_pwr_range=0.2
+
i_source_range=1e-6 i_sink_range=1e-6
+
r_out_domain=1e-6)

12.2.13

Hysteresis Block

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:

cm_hyst
hyst
"hysteresis block"
in
"input"
in
v
[v,vd,i,id]
no

out
"output"
out
v
[v,vd,i,id]
no

162

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

no

no

in_low
"input low value"
real
0.0
no
yes

in_high
"input high value"
real
1.0
no
yes

hyst
"hysteresis"
real
0.1
[0.0 -]
no
yes

out_lower_limit
"output lower limit"
real
0.0
no
yes

out_upper_limit
"output upper limit"
real
1.0
no
yes

input_domain
"input smoothing domain"
real
0.01
no
yes

fraction
"smoothing fraction/absolute value switch"
boolean
TRUE
no
yes

Description: The Hysteresis block is a simple buffer stage that provides hysteresis of the output
with respect to the input. The in low and in high parameter values specify the center
voltage or current inputs about which the hysteresis effect operates. The output values
are limited to out lower limit and out upper limit. The value of hyst is added to the in
low and in high points in order to specify the points at which the slope of the hysteresis
function would normally change abruptly as the input transitions from a low to a high
value. Likewise, the value of hyst is subtracted from the in high and in low values in
order to specify the points at which the slope of the hysteresis function would normally
change abruptly as the input transitions from a high to a low value. In fact, the slope of the

12.2. ANALOG MODELS

163

hysteresis function is never allowed to change abruptly but is smoothly varied whenever
the input domain smoothing parameter is set greater than zero.
Example SPICE Usage:
a11 1 2 schmitt1
.
.
.model schmitt1 hyst(in_low=0.7 in_high=2.4 hyst=0.5
+
out_lower_limit=0.5 out_upper_limit=3.0
+
input_domain=0.01 fraction=TRUE)

12.2.14

Differentiator

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:

cm_d_dt
d_dt
"time-derivative block"
in
"input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

gain
"gain"
real
1.0
no
yes

out_offset
"output offset"
real
0.0
no
yes

out_lower_limit
"output lower limit"
real
no
yes

out_upper_limit
"output upper limit"
real
no
yes

limit_range
"upper & lower limit smoothing range"
real

164

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

1.0e-6
no
yes

Description: The Differentiator block is a simple derivative stage that approximates the time
derivative of an input signal by calculating the incremental slope of that signal since the
previous time point. The block also includes gain and output offset parameters to allow
for tailoring of the required signal, and output upper and lower limits to prevent convergence errors resulting from excessively large output values. The incremental value of
output below the output upper limit and above the output lower limit at which smoothing
begins is specified via the limit range parameter. In AC analysis, the value returned is
equal to the radian frequency of analysis multiplied by the gain.
Note that since truncation error checking is not included in the d_dt block, it is not recommended that the model be used to provide an integration function through the use of
a feedback loop. Such an arrangement could produce erroneous results. Instead, you
should make use of the "integrate" model, which does include truncation error checking
for enhanced accuracy.
Example SPICE Usage:
a12 7 12 slope_gen
.
.
.model slope_gen d_dt(out_offset=0.0 gain=1.0
+
out_lower_limit=1e-12 out_upper_limit=1e12
+
limit_range=1e-9)

12.2.15

Integrator

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:

cm_int
int
"time-integration block"
in
"input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

in_offset
"input offset"
real
0.0

gain
"gain"
real
1.0

12.2. ANALOG MODELS

Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

165

no
yes

no
yes

out_lower_limit
"output lower limit"
real
no
yes

out_upper_limit
"output upper limit"
real
no
yes

limit_range
"upper & lower limit smoothing range"
real
1.0e-6
no
yes
out_ic
"output initial condition"
real
0.0
no
yes

Description: The Integrator block is a simple integration stage that approximates the integral
with respect to time of an input signal. The block also includes gain and input offset
parameters to allow for tailoring of the required signal, and output upper and lower limits
to prevent convergence errors resulting from excessively large output values. Note that
these limits specify integrator behavior similar to that found in an operational amplifierbased integration stage, in that once a limit is reached, additional storage does not occur.
Thus, the input of a negative value to an integrator which is currently driving at the out
upper limit level will immediately cause a drop in the output, regardless of how long
the integrator was previously summing positive inputs. The incremental value of output
below the output upper limit and above the output lower limit at which smoothing begins
is specified via the limit range parameter. In AC analysis, the value returned is equal to
the gain divided by the radian frequency of analysis.
Note that truncation error checking is included in the int block. This should provide
for a more accurate simulation of the time integration function, since the model will
inherently request smaller time increments between simulation points if truncation errors
would otherwise be excessive.

166

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Example SPICE Usage:


a13 7 12 time_count
.
.
.model time_count int(in_offset=0.0 gain=1.0
+
out_lower_limit=-1e12 out_upper_limit=1e12
+
limit_range=1e-9 out_ic=0.0)

12.2.16

S-Domain Transfer Function

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

cm_s_xfer
s_xfer
"s-domain transfer function"
in
"input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

in_offset
"input offset"
real
0.0
no
yes

gain
"gain"
real
1.0
no
yes

num_coeff
"numerator polynomial coefficients"
real
yes
[1 -]
no
den_coeff
"denominator polynomial coefficients"
real
yes

12.2. ANALOG MODELS

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

167

[1 -]
no
int_ic
"integrator stage initial conditions"
real
0.0
yes
den_coeff
yes
denormalized_freq
"denorm. corner freq.(radians) for 1 rad/s coeffs"
real
1.0
no
yes

Description: The s-domain transfer function is a single input, single output transfer function
in the Laplace transform variable s that allows for flexible modulation of the frequency
domain characteristics of a signal. Ac and transient simulations are supported. The code
model may be configured to produce an arbitrary s-domain transfer function with the
following restrictions:
1. The degree of the numerator polynomial cannot exceed that
of the denominator polynomial in the variable "s".
2. The coefficients for a polynomial must be stated
explicitly. That is, if a coefficient is zero, it must be
included as an input to the num coeff or den coeff vector.
The order of the coefficient parameters is from that associated with the highest-powered term
decreasing to that of the lowest. Thus, for the coefficient parameters specified below, the equation in s is shown:
.model filter s_xfer(gain=0.139713 int_ic=[0 0 0]
+ num_coeff=[1.0 0.0 0.07464102]
+ den_coeff=[1.0 0.998942 0.01170077])
...specifies a transfer function of the form...
2

s +0.7464102
}
N(s) = 0.139713 { s2 +0.998942s+0.00117077

The s-domain transfer function includes gain and in_offset (input offset) parameters to allow
for tailoring of the required signal. There are no limits on the internal signal values or on
the output value of the s-domain transfer function, so you are cautioned to specify gain and

168

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

coefficient values that will not cause the model to produce excessively large values. In AC
analysis, the value returned is equal to the real and imaginary components of the total s-domain
transfer function at each frequency of interest.
The denormalized_freq term allows you to specify coefficients for a normalized filter (i.e. one
in which the frequency of interest is 1 rad/s). Once these coefficients are included, specifying
the denormalized frequency value shifts the corner frequency to the actual one of interest. As
an example, the following transfer function describes a Chebyshev low-pass filter with a corner
(pass-band) frequency of 1 rad/s:
1.0
}
N(s) = 0.139713 { s2 +1.09773s+1.10251

In order to define an s_xfer model for the above, but with the corner frequency equal to 1500
rad/s (9425 Hz), the following instance and model lines would be needed:
a12 node1 node2 cheby1
.model cheby1 s_xfer(num_coeff=[1] den_coeff=[1 1.09773 1.10251]
+
int_ic=[0 0 0] denormalized_freq=1500)
In the above, you add the normalized coefficients and scale the filter through the use of the
denormalized freq parameter. Similar results could have been achieved by performing the denormalization prior to specification of the coefficients, and setting denormalized freq to the
value 1.0 (or not specifying the frequency, as the default is 1.0 rad/s) Note in the above that
frequencies are ALWAYS SPECIFIED AS RADIANS/SECOND.
Truncation error checking is included in the s-domain transfer block. This should provide for
more accurate simulations, since the model will inherently request smaller time increments
between simulation points if truncation errors would otherwise be excessive.
The int_ic parameter is an array that must be of the same size as the array of values specified
for the den_coeff parameter. Even if a 0 start value is required, you have to add the specific
int_ic vector to the set of coefficients (see the examples above and below).
Example SPICE Usage:
a14 9 22 cheby_LP_3KHz
.
.
.model cheby_LP_3KHz s_xfer(in_offset=0.0 gain=1.0 int_ic=[0 0 0]
+
num_coeff=[1.0]
+
den_coeff=[1.0 1.42562 1.51620])

12.2.17

Slew Rate Block

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:

cm_slew
slew
"A simple slew rate follower block"
in

out

12.2. ANALOG MODELS

Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

169

"input"
in
v
[v,vd,i,id]
no
no

"output"
out
v
[v,vd,i,id]
no
no

rise_slope
"maximum rising slope value"
real
1.0e9
no
yes
fall_slope
"maximum falling slope value"
real
1.0e9
no
yes
range
"smoothing range"
real
0.1
no
yes

Description: This function is a simple slew rate block that limits the absolute slope of the
output with respect to time to some maximum or value. The actual slew rate effects of
over-driving an amplifier circuit can thus be accurately modeled by cascading the amplifier with this model. The units used to describe the maximum rising and falling slope
values are expressed in volts or amperes per second. Thus a desired slew rate of 0.5 V/s
will be expressed as 0.5e+6, etc.
The slew rate block will continue to raise or lower its output until the difference between
the input and the output values is zero. Thereafter, it will resume following the input signal, unless the slope again exceeds its rise or fall slope limits. The range input specifies
a smoothing region above or below the input value. Whenever the model is slewing and
the output comes to within the input + or - the range value, the partial derivative of the
output with respect to the input will begin to smoothly transition from 0.0 to 1.0. When
the model is no longer slewing (output = input), dout/din will equal 1.0.

170

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Example SPICE Usage:


a15 1 2 slew1
.model slew1 slew(rise_slope=0.5e6 fall_slope=0.5e6)

12.2.18

Inductive Coupling

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

cm_lcouple
lcouple
"inductive coupling (for use with core model)"
l
"inductor"
inout
hd
[h,hd]
no
no

mmf_out
"mmf output (in ampere-turns)"
inout
hd
[hd]
no
no

num_turns
"number of inductor turns"
real
1.0
no
yes

Description: This function is a conceptual model which is used as a building block to create a
wide variety of inductive and magnetic circuit models. This function is normally used in
conjunction with the core model, but can also be used with resistors, hysteresis blocks,
etc. to build up systems which mock the behavior of linear and nonlinear components.
The lcouple takes as an input (on the l port) a current. This current value is multiplied by
the num_turns value, N, to produce an output value (a voltage value which appears on the
mmf_out port). The mmf_out acts similar to a magnetomotive force in a magnetic circuit;
when the lcouple is connected to the core model, or to some other resistive device, a
current will flow. This current value (which is modulated by whatever the lcouple is
connected to) is then used by the lcouple to calculate a voltage seen at the l port. The
voltage is a function of the derivative with respect to time of the current value seen at
mmf_out.
The most common use for lcouples will be as a building block in the construction of
transformer models. To create a transformer with a single input and a single output, you
would require two lcouple models plus one core model. The process of building up
such a transformer is described under the description of the core model, below.
Example SPICE Usage:
a150 (7 0) (9 10) lcouple1
.model lcouple1 lcouple(num_turns=10.0)

12.2. ANALOG MODELS

12.2.19

171

Magnetic Core

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector: no
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

cm_core
core
"magnetic core"
mc
"magnetic core"
inout
gd
[g,gd]
no
H_array
"magnetic field array"
real
yes
[2 -]
no

B_array
"flux density array"
real
yes
[2 -]
no

area
"cross-sectional area"
real
no
no

length
"core length"
real
no
no

input_domain
"input sm. domain"
real
0.01
[1e-12 0.5]
no
yes
fraction
"smoothing fraction/abs switch"
boolean
TRUE
no

172

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

yes
mode
"mode switch (1 = pwl, 2 = hyst)"
int
1
[1 2]
no
yes
in_low
"input low value"
real
0.0
no
yes

in_high
"input high value"
real
1.0
no
yes

hyst
"hysteresis"
real
0.1
[0 -]
no
yes

out_lower_limit
"output lower limit"
real
0.0
no
yes

out_upper_limit
"output upper limit"
real
1.0
no
yes

Description: This function is a conceptual model which is used as a building block to create
a wide variety of inductive and magnetic circuit models. This function is almost always
expected to be used in conjunction with the lcouple model to build up systems which
mock the behavior of linear and nonlinear magnetic components. There are two fundamental modes of operation for the core model. These are the pwl mode (which is the
default, and which is the most likely to be of use to you) and the hysteresis mode. These
are detailed below.
PWL Mode (mode = 1)

12.2. ANALOG MODELS

173

The core model in PWL mode takes as input a voltage which it treats as a magnetomotive force
(mmf) value. This value is divided by the total effective length of the core to produce a value
for the Magnetic Field Intensity, H. This value of H is then used to find the corresponding Flux
Density, B, using the piecewise linear relationship described by you in the H array / B array
coordinate pairs. B is then multiplied by the cross-sectional area of the core to find the Flux
value, which is output as a current. The pertinent mathematical equations are listed below:
H = mmf =L, where L = Length
Here H, the Magnetic Field Intensity, is expressed in ampere-turns/meter.
B = f (H)
The B value is derived from a piecewise linear transfer function described to the model via
the (H_array[],B_array[]) parameter coordinate pairs. This transfer function does not include
hysteretic effects; for that, you would need to substitute a HYST model for the core.
= BA, where A = Area
The final current allowed to flow through the core is equal to . This value in turn is used by
the "lcouple" code model to obtain a value for the voltage reflected back across its terminals to
the driving electrical circuit.
The following example code shows the use of two lcouple models and one core model to
produce a simple primary/secondary transformer.
Example SPICE Usage:
a1 (2 0) (3 0) primary
.model primary lcouple (num_turns = 155)
a2 (3 4) iron_core
.model iron_core core (H_array = [-1000 -500 -375 -250 -188 -125 -63 0
+
63 125 188 250 375 500 1000]
+
B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3
+
-1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4
+
6.25e-4 1.5e-3 1.93e-3 2.33e-3
+
2.63e-3 3.13e-3]
+
area = 0.01 length = 0.01)
a3 (5 0) (4 0) secondary
.model secondary lcouple (num_turns = 310)
HYSTERESIS Mode (mode = 2)
The core model in HYSTERESIS mode takes as input a voltage which it treats as a magnetomotive force (mmf) value. This value is used as input to the equivalent of a hysteresis code model
block. The parameters defining the input low and high values, the output low and high values,
and the amount of hysteresis are as in that model. The output from this mode, as in PWL mode,
is a current value which is seen across the mc port. An example of the core model used in this
fashion is shown below:

174

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Example SPICE Usage:


a1 (2 0) (3 0) primary
.model primary lcouple (num_turns = 155)
a2 (3 4) iron_core
.model iron_core core (mode = 2 in_low=-7.0 in_high=7.0
+
out_lower_limit=-2.5e-4 out_upper_limit=2.5e-4
+
hyst = 2.3 )
a3 (5 0) (4 0) secondary
.model secondary lcouple (num_turns = 310)
One final note to be made about the two core model nodes is that certain parameters are available in one mode, but not in the other. In particular, the in_low, in_high, out_lower_limit,
out_upper_limit, and hysteresis parameters are not available in PWL mode. Likewise, the
H_array, B_array, area, and length values are unavailable in HYSTERESIS mode. The input
domain and fraction parameters are common to both modes (though their behavior is somewhat
different; for explanation of the input domain and fraction values for the HYSTERESIS mode,
you should refer to the hysteresis code model discussion).

12.2.20

Controlled Sine Wave Oscillator

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:

cm_sine
sine
"controlled sine wave oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

cntl_array
"control array"
real
0.0
yes
[2 -]
no

freq_array
"frequency array"
real
1.0e3
[0 -]
yes
cntl_array
no

out_low
out_high
"output peak low value" "output peak high value"
real
real
-1.0
1.0
-

12.2. ANALOG MODELS

Vector:
Vector_Bounds:
Null_Allowed:

175

no
yes

no
yes

Description: This function is a controlled sine wave oscillator with parametrizable values of
low and high peak output. It takes an input voltage or current value. This value is used as
the independent variable in the piecewise linear curve described by the coordinate points
of the cntl array and freq array pairs. From the curve, a frequency value is determined,
and the oscillator will output a sine wave at that frequency. From the above, it is easy
to see that array sizes of 2 for both the cntl array and the freq array will yield a linear
variation of the frequency with respect to the control input. Any sizes greater than 2 will
yield a piecewise linear transfer characteristic. For more detail, refer to the description of
the piecewise linear controlled source, which uses a similar method to derive an output
value given a control input.
Example SPICE Usage:
asine 1 2 in_sine
.model in_sine sine(cntl_array = [-1 0 5 6]
+
freq_array=[10 10 1000 1000] out_low = -5.0
+
out_high = 5.0)

12.2.21

Controlled Triangle Wave Oscillator

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:

cm_triangle
triangle
"controlled triangle wave oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

cntl_array
"control array"
real
0.0
yes
[2 -]
no

freq_array
"frequency array"
real
1.0e3
[0 -]
yes
cntl_array
no

out_low
out_high
"output peak low value" "output peak high value"

176

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

real
-1.0
no
yes

real
1.0
no
yes

rise_duty
"rise time duty cycle"
real
0.5
[1e-10 0.999999999]
no
yes

Description: This function is a controlled triangle/ramp wave oscillator with parametrizable


values of low and high peak output and rise time duty cycle. It takes an input voltage or
current value. This value is used as the independent variable in the piecewise linear curve
described by the coordinate points of the cntl_array and freq_array pairs.
From the curve, a frequency value is determined, and the oscillator will output a triangle
wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the
cntl_array and the freq_array will yield a linear variation of the frequency with respect to
the control input. Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description of the piecewise linear controlled source,
which uses a similar method to derive an output value given a control input.
Example SPICE Usage:
ain 1 2 ramp1
.model ramp1 triangle(cntl_array = [-1 0 5 6]
+
freq_array=[10 10 1000 1000] out_low = -5.0
+
out_high = 5.0 duty_cycle = 0.9)

12.2.22

Controlled Square Wave Oscillator

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:

cm_square
square
"controlled square wave oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

12.2. ANALOG MODELS

PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER.TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector: no
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

177

cntl_array
"control array"
real
0.0
yes
[2 -]
no

freq_array
"frequency array"
real
1.0e3
[0 -]
yes
cntl_array
no

out_low
out_high
"output peak low value" "output peak high value"
real
real
-1.0
1.0
no
no
yes
yes
duty_cycle
"duty cycle"
real
0.5
[1e-6 0.999999]

rise_time
"output rise time"
real
1.0e-9
-

yes

yes

fall_time
"output fall time"
real
1.0e-9
no
yes

Description: This function is a controlled square wave oscillator with parametrizable values
of low and high peak output, duty cycle, rise time, and fall time. It takes an input voltage
or current value. This value is used as the independent variable in the piecewise linear
curve described by the coordinate points of the cntl_array and freq_array pairs. From the
curve, a frequency value is determined, and the oscillator will output a square wave at
that frequency.
From the above, it is easy to see that array sizes of 2 for both the cntl_array and the
freq_array will yield a linear variation of the frequency with respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more
detail, refer to the description of the piecewise linear controlled source, which uses a
similar method to derive an output value given a control input.

178

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Example SPICE Usage:


ain 1 2 pulse1
.model pulse1 square(cntl_array = [-1 0 5 6]
+
freq_array=[10 10 1000 1000] out_low = 0.0
+
out_high = 4.5 duty_cycle = 0.2
+
rise_time = 1e-6 fall_time = 2e-6)

12.2.23

Controlled One-Shot

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:

cm_oneshot
oneshot
"controlled one-shot"
clk
"clock input"
in
v
[v,vd,i,id]
no
no

cntl_in
"control input"
in
v
[v,vd,i,id]
no
yes

clear
"clear signal"
in
v
[v,vd,i,id]
no
yes

out
"output"
out
v
[v,vd,i,id]
no
no

clk_trig
"clock trigger value"
real
0.5
no
no

retrig
"retrigger switch"
boolean
FALSE
no
yes

pos_edge_trig
"positive/negative edge trigger switch"
boolean
TRUE
no
-

12.2. ANALOG MODELS

Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

179

no
cntl_array
"control array"
real
0.0
yes
yes

pw_array
"pulse width array"
real
1.0e-6
[0.00 -]
yes
cntl_array
yes

out_low
"output low value"
real
0.0
no
yes

out_high
"output high value"
real
1.0
no
yes

fall_time
"output fall time"
real
1.0e-9
no
yes

rise_time
"output rise time"
real
1.0e-9
no
yes

rise_delay
"output delay from trigger"
real
1.0e-9
no
yes
fall_delay
"output delay from pw"
real
1.0e-9
no
yes

Description: This function is a controlled oneshot with parametrizable values of low and high
peak output, input trigger value level, delay, and output rise and fall times. It takes an

180

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE


input voltage or current value. This value is used as the independent variable in the
piecewise linear curve described by the coordinate points of the cntl_array and pw_array
pairs. From the curve, a pulse width value is determined. The one-shot will output a
pulse of that width, triggered by the clock signal (rising or falling edge), delayed by the
delay value, and with specified rise and fall times. A positive slope on the clear input will
immediately terminate the pulse, which resets with its fall time.
From the above, it is easy to see that array sizes of 2 for both the cntl_array and the
pw_array will yield a linear variation of the pulse width with respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more
detail, refer to the description of the piecewise linear controlled source, which uses a
similar method to derive an output value given a control input.
Example SPICE Usage:
ain 1 2 3 4 pulse2
.model pulse2 oneshot(cntl_array = [-1 0 10 11]
+
pw_array=[1e-6 1e-6 1e-4 1e-4]
+
clk_trig = 0.9 pos_edge_trig = FALSE
+
out_low = 0.0 out_high = 4.5
+
rise_delay = 20.0-9 fall_delay = 35.0e-9)

12.2.24

Capacitance Meter

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

cm_cmeter
cmeter
"capacitance meter"
in
"input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

gain
"gain"
real
1.0
no
yes

Description: The capacitance meter is a sensing device which is attached to a circuit node
and produces as an output a scaled value equal to the total capacitance seen on its input
multiplied by the gain parameter. This model is primarily intended as a building block for

12.2. ANALOG MODELS

181

other models which must sense a capacitance value and alter their behavior based upon
it.
Example SPICE Usage:
atest1 1 2 ctest
.model ctest cmeter(gain=1.0e12)

12.2.25

Inductance Meter

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

cm_lmeter
lmeter
"inductance meter"
in
"input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
v
[v,vd,i,id]
no
no

gain
"gain"
real
1.0
no
yes

Description: The inductance meter is a sensing device which is attached to a circuit node
and produces as an output a scaled value equal to the total inductance seen on its input
multiplied by the gain parameter. This model is primarily intended as a building block for
other models which must sense an inductance value and alter their behavior based upon
it.
Example SPICE Usage:
atest2 1 2 ltest
.model ltest lmeter(gain=1.0e6)

12.2.26

Memristor

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:

cm_memristor
memristor

182

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

"Memristor Interface"
memris
"memristor terminals"
inout
gd
[gd]
no
no
rmin
"minimum resistance"
real
10.0
no
no

rmax
"maximum resistance"
real
10000.0
no
no

rinit
"initial resistance"
real
7000.0
no
no

vt
"threshold"
real
0.0
no
no

alpha
"model parameter 1"
real
0.0
no
no

beta
"model parameter 2"
real
1.0
no
no

Description: The memristor is a two-terminal resistor with memory, whose resistance depends
on the time integral of the voltage across its terminals. rmin and rmax provide the lower
and upper limits of the resistance, rinit is its starting value (no voltage applied so far).
The voltage has to be above a threshold vt to become effective in changing the resistance.
alpha and beta are two model parameters. The memristor code model is derived from a
SPICE subcircuit published in [23].
Example SPICE Usage:
amen 1 2 memr
.model memr memristor (rmin=1k rmax=10k rinit=7k
+ alpha=0 beta=2e13 vt=1.6)

12.3. HYBRID MODELS

12.3

183

Hybrid Models

The following hybrid models are supplied with XSPICE. The descriptions included below consist of the model Interface Specification File and a description of the models operation. This
is followed by an example of a simulator-deck placement of the model, including the .MODEL
card and the specification of all available parameters.
A note should be made with respect to the use of hybrid models for other than simple digital-toanalog and analog-to-digital translations. The hybrid models represented in this section address
that specific need, but in the development of user-defined nodes you may find a need to translate
not only between digital and analog nodes, but also between real and digital, real and int, etc.
In most cases such translations will not need to be as involved or as detailed as shown in the
following.

12.3.1

Digital-to-Analog Node Bridge

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:

cm_dac_bridge
dac_bridge
"digital-to-analog node bridge"
in
"input"
in
d
[d]
yes
no

out
"output"
out
v
[v,vd,i,id,d]
yes
no

out_low
"0-valued analog output"
real
0.0
no
yes
out.high
"1-valued analog output"
real
1.0
no
yes

184

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

out_undef
"U-valued analog output"
real
0.5
no
yes

input_load
"input load (F)"
real
1.0e-12
no
yes

t_rise
"rise time 0->1"
real
1.0e-9
no
yes

t_fall
"fall time 1->0"
real
1.0e-9
no
yes

Description: The dac_bridge is the first of two node bridge devices designed to allow for the
ready transfer of digital information to analog values and back again. The second device is
the adc_bridge (which takes an analog value and maps it to a digital one).The dac_bridge
takes as input a digital value from a digital node. This value by definition may take on
only one of the values 0, 1 or U. The dac_bridge then outputs the value out_low,
out_high or out_undef, or ramps linearly toward one of these final values from its
current analog output level. The speed at which this ramping occurs depends on the values
of t_rise and t_fall. These parameters are interpreted by the model such that the rise
or fall slope generated is always constant. Note that the dac_bridge includes test code
in its cfunc.mod file for determining the presence of the out_undef parameter. If this
parameter is not specified by you, and if out_high and out_low values are specified,
then out_undef is assigned the value of the arithmetic mean of out_high and out_low.
This simplifies coding of output buffers, where typically a logic family will include an
out_low and out_high voltage, but not an out_undef value. This model also posts an input
load value (in farads) based on the parameter input load.
Example SPICE Usage:
abridge1 [7] [2] dac1
.model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 out_undef = 2.2
+
input_load = 5.0e-12 t_rise = 50e-9
+
t_fall = 20e-9)

12.3.2

Analog-to-Digital Node Bridge

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:

cm_adc_bridge
adc_bridge
"analog-to-digital node bridge"
in

out

12.3. HYBRID MODELS

Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

185

"input"
in
v
[v,vd,i,id,d]
yes
no

"output"
out
d
[d]
yes
no

in_low
"maximum 0-valued analog input"
real
1.0
no
yes
in_high
"minimum 1-valued analog input"
real
2.0
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The adc_bridge is one of two node bridge devices designed to allow for the ready
transfer of analog information to digital values and back again. The second device is the
dac_bridge (which takes a digital value and maps it to an analog one). The adc_bridge
takes as input an analog value from an analog node. This value by definition may be
in the form of a voltage, or a current. If the input value is less than or equal to in_low,
then a digital output value of 0 is generated. If the input is greater than or equal to
in_high, a digital output value of 1 is generated. If neither of these is true, then a digital
UNKNOWN value is output. Note that unlike the case of the dac_bridge, no ramping
time or delay is associated with the adc_bridge. Rather, the continuous ramping of the
input value provides for any associated delays in the digitized signal.
Example SPICE Usage:
abridge2 [1] [8] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 3.5)

186

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

12.3.3

Controlled Digital Oscillator

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

cm_d_osc
d_osc
"controlled digital oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no

out
"output"
out
d
[d]
no
no

cntl_array
"control array"
real
0.0
yes
[2 -]
no

freq_array
"frequency array"
real
1.0e6
[0 -]
yes
cntl_array
no

duty_cycle
"duty cycle"
real
0.5
[1e-6 0.999999]
no
yes

init_phase
"initial phase of output"
real
0
[-180.0 +360.0]
no
yes

rise_delay
"rise delay"
real
1e-9
[0 -]
no
yes

fall_delay
"fall delay"
real
1e-9
[0 -]
no
yes

Description: The digital oscillator is a hybrid model which accepts as input a voltage or current. This input is compared to the voltage-to-frequency transfer characteristic specified
by the cntl_array/freq_array coordinate pairs, and a frequency is obtained which represents a linear interpolation or extrapolation based on those pairs. A digital time-varying
signal is then produced with this fundamental frequency.
The output waveform, which is the equivalent of a digital clock signal, has rise and fall

12.3. HYBRID MODELS

187

delays which can be specified independently. In addition, the duty cycle and the phase of
the waveform are also variable and can be set by you.
Example SPICE Usage:
a5 1 8 var_clock
.model var_clock d_osc(cntl_array
+
freq_array
+
duty_cycle
+
rise_delay

12.3.4

=
=
=
=

[-2 -1 1 2]
[1e3 1e3 10e3 10e3]
0.4 init_phase = 180.0
10e-9 fall_delay=8e-9)

Node bridge from digital to real with enable

NAME_TABLE:
Spice_Model_Name: d_to_real
C_Function_Name: ucm_d_to_real
Description: "Node bridge from digital to real
PORT_TABLE:
Port_Name:
in
enable
out
Description:
"input"
"enable"
"output"
Direction:
in
in
out
Default_Type:
d
d
real
Allowed_Types: [d]
[d]
[real]
Vector:
no
no
no
Vector_Bounds: Null_Allowed:
no
yes
no
PARAMETER_TABLE:
Parameter_Name: zero
one
Description:
"value for 0"
"value for 1"
Data_Type:
real
real
Default_Value: 0.0
1.0
Limits:
Vector:
no
no
Vector_Bounds: Null_Allowed:
yes
yes

12.3.5

with enable"

delay
"delay"
real
1e-9
[1e-15 -]
no
yes

A Z**-1 block working on real data

NAME_TABLE:
Spice_Model_Name: real_delay
C_Function_Name: ucm_real_delay
Description: "A Z ** -1 block working on real data"
PORT_TABLE:
Port_Name:
in
clk
out
Description:
"input"
"clock"
"output"
Direction:
in
in
out
Default_Type:
real
d
real
Allowed_Types:
[real]
[d]
[real]

188

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

12.3.6

no
no

no
no

no
no

delay
"delay from clk to out"
real
1e-9
[1e-15 -]
no
yes

A gain block for event-driven real data

NAME_TABLE:
Spice_Model_Name:
C_Function_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

real_gain
ucm_real_gain
"A gain block for event-driven real data"
in
"input"
in
real
[real]
no
no

out
"output"
out
real
[real]
no
no

in_offset
"input offset"
real
0.0
no
yes

gain
"gain"
real
1.0
no
yes

delay
"delay"
real
1.0e-9
no
yes

ic
"initial condition"
real
0.0
no
yes

out_offset
"output offset"
real
0.0
no
yes

12.4. DIGITAL MODELS

12.3.7

189

Node bridge from real to analog voltage

NAME_TABLE:
Spice_Model_Name:
C_Function_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

12.4

real_to_v
ucm_real_to_v
"Node bridge from real to analog voltage"
in
"input"
in
real
[real]
no
no

out
"output"
out
v
[v, vd, i, id]
no
no

gain
"gain"
real
1.0
no
yes

transition_time
"output transition time"
real
1e-9
[1e-15 -]
no
yes

Digital Models

The following digital models are supplied with XSPICE. The descriptions included below consist of an example model Interface Specification File and a description of the models operation. This is followed by an example of a simulator-deck placement of the model, including the
.MODEL card and the specification of all available parameters. Note that these models have
not been finalized at this time.
Some information common to all digital models and/or digital nodes is included here. The
following are general rules which should make working with digital nodes and models more
straightforward:
1. All digital nodes are initialized to ZERO at the start of a simulation (i.e., when INIT=TRUE).
This means that a model need not post an explicit value to an output node upon initialization if its output would normally be a ZERO (although posting such would certainly
cause no harm).

12.4.1

Buffer

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:

cm_d_buffer
d_buffer
"digital one-bit-wide buffer"

190

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

in
"input"
in
d
[d]
no
no

out
"output"
out
d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The buffer is a single-input, single-output digital buffer which produces as output
a time-delayed copy of its input. The delays associated with an output rise and those associated with an output fall may be different. The model also posts an input load value (in
farads) based on the parameter input load. The output of this model does NOT, however,
respond to the total loading it sees on its output; it will always drive the output strongly
with the specified delays.
Example SPICE Usage:
a6 1 8 buff1
.model buff1 d_buffer(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.2

Inverter

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:

cm_d_inverter
d_inverter
"digital one-bit-wide inverter"
in

out

12.4. DIGITAL MODELS

Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

191

"input"
in
d
[d]
no
no

"output"
out
d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The inverter is a single-input, single-output digital inverter which produces as


output an inverted, time-delayed copy of its input. The delays associated with an output
rise and those associated with an output fall may be specified independently. The model
also posts an input load value (in farads) based on the parameter input load. The output
of this model does NOT, however, respond to the total loading it sees on its output; it will
always drive the output strongly with the specified delays.
Example SPICE Usage:
a6 1 8 inv1
.model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.3

And

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:

cm_d_and
d_and
"digital and gate"
in
"input"
in

out
"output"
out

192

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

d
[d]
yes
[2 -]
no

d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The digital and gate is an n-input, single-output and gate which produces an
active 1 value if, and only if, all of its inputs are also 1 values. If ANY of the inputs is
a 0, the output will also be a 0; if neither of these conditions holds, the output will be
unknown. The delays associated with an output rise and those associated with an output
fall may be specified independently. The model also posts an input load value (in farads)
based on the parameter input load. The output of this model does NOT, however, respond
to the total loading it sees on its output; it will always drive the output strongly with the
specified delays.
Example SPICE Usage:
a6 [1 2] 8 and1
.model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.4

Nand

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:

cm_d_nand
d_nand
"digital nand gate"
in
"input"
in

out
"output"
out

12.4. DIGITAL MODELS

Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

193

d
[d]
yes
[2 -]
no

d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The digital nand gate is an n-input, single-output nand gate which produces
an active 0 value if and only if all of its inputs are 1 values. If ANY of the inputs
is a 0, the output will be a 1; if neither of these conditions holds, the output will be
unknown. The delays associated with an output rise and those associated with an output
fall may be specified independently. The model also posts an input load value (in farads)
based on the parameter input load. The output of this model does NOT, however, respond
to the total loading it sees on its output; it will always drive the output strongly with the
specified delays.
Example SPICE Usage:
a6 [1 2 3] 8 nand1
.model nand1 d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.5

Or

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:

cm_d_or
d_or
"digital or gate"
in
"input"
in

out
"output"
out

194

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

d
[d]
yes
[2 -]
no

d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The digital or gate is an n-input, single-output or gate which produces an


active 1 value if at least one of its inputs is a 1 value. The gate produces a 0 value
if all inputs are 0; if neither of these two conditions holds, the output is unknown.
The delays associated with an output rise and those associated with an output fall may be
specified independently. The model also posts an input load value (in farads) based on the
parameter input load. The output of this model does NOT, however, respond to the total
loading it sees on its output; it will always drive the output strongly with the specified
delays.
Example SPICE Usage:
a6 [1 2 3] 8 or1
.model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.6

Nor

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:

cm_d_nor
d_nor
"digital nor gate"
in
"input"
in

out
"output"
out

12.4. DIGITAL MODELS

Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

195

d
[d]
yes
[2 -]
no

d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The digital nor gate is an n-input, single-output nor gate which produces an
active 0 value if at least one of its inputs is a 1 value. The gate produces a 0 value
if all inputs are 0; if neither of these two conditions holds, the output is unknown.
The delays associated with an output rise and those associated with an output fall may be
specified independently. The model also posts an input load value (in farads) based on the
parameter input load. The output of this model does NOT, however, respond to the total
loading it sees on its output; it will always drive the output strongly with the specified
delays.
Example SPICE Usage:
anor12 [1 2 3 4] 8 nor12
.model nor12 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.7

Xor

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:

cm_d_xor
d_xor
"digital exclusive-or gate"
in
"input"
in

out
"output"
out

196

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

d
[d]
yes
[2 -]
no

d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The digital xor gate is an n-input, single-output xor gate which produces an
active 1 value if an odd number of its inputs are also 1 values. The delays associated
with an output rise and those associated with an output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter input load.
The output of this model does NOT, however, respond to the total loading it sees on its
output; it will always drive the output strongly with the specified delays. Note also that
to maintain the technology-independence of the model, any UNKNOWN input, or any
floating input causes the output to also go UNKNOWN.
Example SPICE Usage:
a9 [1 2] 8 xor3
.model xor3 d_xor(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.8

Xnor

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:

cm_d_xnor
d_xnor
"digital exclusive-nor gate"
in
"input"

out
"output"

12.4. DIGITAL MODELS

Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

197

in
d
[d]
yes
[2 -]
no

out
d
[d]
no
no

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

input_load
"input load value (F)"
real
1.0e-12
no
yes

Description: The digital xnor gate is an n-input, single-output xnor gate which produces an
active 0 value if an odd number of its inputs are also 1 values. It produces a 1 output
when an even number of 1 values occurs on its inputs. The delays associated with
an output rise and those associated with an output fall may be specified independently.
The model also posts an input load value (in farads) based on the parameter input load.
The output of this model does NOT, however, respond to the total loading it sees on its
output; it will always drive the output strongly with the specified delays. Note also that
to maintain the technology-independence of the model, any UNKNOWN input, or any
floating input causes the output to also go UNKNOWN.
Example SPICE Usage:
a9 [1 2] 8 xnor3
.model xnor3 d_xnor(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)

12.4.9

Tristate

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:

cm_d_tristate
d_tristate
"digital tristate buffer"
in

enable

out

198

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

"input"
in
d
[d]
no
no

"enable"
in
d
[d]
no
no

"output"
out
d
[d]
no
no

delay
"delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
enable_load
"enable load value (F)"
real
1.0e-12
no
yes

Description: The digital tristate is a simple tristate gate which can be configured to allow for
open-collector behavior, as well as standard tristate behavior. The state seen on the input
line is reflected in the output. The state seen on the enable line determines the strength of
the output. Thus, a ONE forces the output to its state with a STRONG strength. A ZERO
forces the output to go to a HI_IMPEDANCE strength. The delays associated with an
output state or strength change cannot be specified independently, nor may they be specified independently for rise or fall conditions; other gate models may be used to provide
such delays if needed. The model posts input and enable load values (in farads) based
on the parameters input load and enable.The output of this model does NOT, however,
respond to the total loading it sees on its output; it will always drive the output with the
specified delay. Note also that to maintain the technology-independence of the model,
any UNKNOWN input, or any floating input causes the output to also go UNKNOWN.
Likewise, any UNKNOWN input on the enable line causes the output to go to an UNDETERMINED strength value.

12.4. DIGITAL MODELS

199

Example SPICE Usage:


a9 1 2 8 tri7
.model tri7 d_tristate(delay = 0.5e-9 input_load = 0.5e-12
+
enable_load = 0.5e-12)

12.4.10

Pullup

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

cm_d_pullup
d_pullup
"digital pullup resistor"
out
"output"
out
d
[d]
no
no
load
"load value (F)"
real
1.0e-12
no
yes

Description: The digital pullup resistor is a device which emulates the behavior of an analog
resistance value tied to a high voltage level. The pullup may be used in conjunction
with tristate buffers to provide open-collector wired or constructs, or any other logical
constructs which rely on a resistive pullup common to many tristated output devices. The
model posts an input load value (in farads) based on the parameters load.
Example SPICE Usage:
a2 9 pullup1
.model pullup1 d_pullup(load = 20.0e-12)

12.4.11

Pulldown

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:

cm_d_pulldown
d_pulldown
"digital pulldown resistor"

200

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

out
"output"
out
d
[d]
no
no
load
"load value (F)"
real
1.0e-12
no
yes

Description: The digital pulldown resistor is a device which emulates the behavior of an analog
resistance value tied to a low voltage level. The pulldown may be used in conjunction
with tristate buffers to provide open-collector wired or constructs, or any other logical
constructs which rely on a resistive pulldown common to many tristated output devices.
The model posts an input load value (in farads) based on the parameters load.
Example SPICE Usage:
a4 9 pulldown1
.model pulldown1 d_pulldown(load = 20.0e-12)

12.4.12

D Flip Flop

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:

cm_d_dff
d_dff
"digital d-type flip flop"
data
"input data"
in
d
[d]
no
no
set
"asynch. set"
in
d

clk
"clock"
in
d
[d]
no
no
reset
"asynch. reset"
in
d

12.4. DIGITAL MODELS

Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector.Bounds:

201

[d]
no
yes

[d]
no
yes

out
"data output"
out
d
[d]
no
yes

Nout
"inverted data output"
out
d
[d]
no
yes

clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes

set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes

reset_delay
"delay from reset"
real
1.0
[1.0e-12 -]
no
yes

ic
"output initial state"
int
0
[0 2]
no
yes

data_load
"data load value (F)"
real
1.0e-12
no
yes

clk_load
"clk load value (F)"
real
1.0e-12
no
yes

set_load
"set load value (F)"
real
1.0e-12
no
-

reset_load
"reset load (F)"
real
1.0e-12
no
-

202

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

yes

yes

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The digital d-type flip flop is a one-bit, edge-triggered storage element which will
store data whenever the clk input line transitions from low to high (ZERO to ONE). In
addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_dff have separate load values and delays associated with
them. Additionally, you may specify separate rise and fall delay values that are added to
those specified for the input lines; these allow for more faithful reproduction of the output
characteristics of different IC fabrication technologies.
Note that any UNKNOWN input on the set or reset lines immediately results in an UNKNOWN output.
Example SPICE Usage:
a7 1 2 3 4 5 6 flop1
.model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9)

12.4.13

JK Flip Flop

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:

cm_d_jkff
d_jkff
"digital jk-type flip flop"
j
"j input"
in
d
[d]
no
no
clk
"clock"
in
d
[d]

k
"k input"
in
d
[d]
no
no

12.4. DIGITAL MODELS

Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

203

no
no
set
"asynchronous set"
in
d
[d]
no
yes

reset
"asynchronous reset"
in
d
[d]
no
yes

out
"data output"
out
d
[d]
no
yes

Nout
"inverted data output"
out
d
[d]
no
yes

clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes

set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes

reset_delay
"delay from reset"
real
1.0
[1.0e-12 -]
no
yes

ic
"output initial state"
int
0
[0 2]
no
yes

jk_load
"j,k load values (F)"
real
1.0e-12
no
yes

clk_load
"clk load value (F)"
real
1.0e-12
no
yes

204

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

set_load
"set load value (F)"
real
1.0e-12
no
yes

reset_load
"reset load (F)"
real
1.0e-12
no
yes

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The digital jk-type flip flop is a one-bit, edge-triggered storage element which
will store data whenever the clk input line transitions from low to high (ZERO to ONE).
In addition, asynchronous set and reset signals exist, and each of the three methods of
changing the stored output of the d_jkff have separate load values and delays associated
with them. Additionally, you may specify separate rise and fall delay values that are
added to those specified for the input lines; these allow for more faithful reproduction of
the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than j or k cause the output to go UNKNOWN
automatically.
Example SPICE Usage:
a8 1 2 3 4 5 6 7 flop2
.model flop2 d_jkff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9)

12.4.14

Toggle Flip Flop

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:

cm_d_tff
d_tff
"digital toggle flip flop"
t
"toggle input"
in
d
[d]
no

clk
"clock"
in
d
[d]
no

12.4. DIGITAL MODELS

Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT.TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:

205

no

no

set
"set"
in
d
[d]
no
yes

reset
"reset"
in
d
[d]
no
yes

out
"data output"
out
d
[d]
no
yes

Nout
"inverted data output"
out
d
[d]
no
yes

clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes

set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes

reset_delay
"delay from reset"
real
1.0
[1.0e-12 -]
no
yes

ic
"output initial state"
int
0
[0 2]
no
yes

t_load
clk_load
"toggle load value (F)" "clk load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes

206

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Parameter_Name:
Description:
Data_Type:
Default.Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

set_load
"set load value (F)"
real
1.0e-12
no
yes

reset_load
"reset load (F)"
real
1.0e-12
no
yes

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The digital toggle-type flip flop is a one-bit, edge-triggered storage element which
will toggle its current state whenever the clk input line transitions from low to high (ZERO
to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output of the d_tff have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that
are added to those specified for the input lines; these allow for more faithful reproduction
of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than t immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a8 2 12 4 5 6 3 flop3
.model flop3 d_tff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9 t_load = 0.2e-12)

12.4.15

Set-Reset Flip Flop

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:

cm_d_srff
d_srff
"digital set-reset flip flop"
s
"set input"
in
d
[d]
no
-

r
"reset input"
in
d
[d]
no
-

12.4. DIGITAL MODELS

Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:

207

no

no

clk
"clock"
in
d
[d]
no
no
set
"asynchronous set"
in
d
[d]
no
yes

reset
"asynchronous reset"
in
d
[d]
no
yes

out
"data output"
out
d
[d]
no
yes

Nout
"inverted data output"
out
d
[d]
no
yes

clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes

set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes

reset_delay
"delay from reset"
real
1.0e-9
[1.0e-12 -]
no
yes

ic
"output initial state"
int
0
[0 2]
no
yes

sr_load

clk_load

208

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

"set/reset loads (F)"


real
1.0e-12
no
yes

"clk load value (F)"


real
1.0e-12
no
yes

set_load
"set load value (F)"
real
1.0e-12
no
yes

reset_load
"reset load (F)"
real
1.0e-12
no
yes

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The digital sr-type flip flop is a one-bit, edge-triggered storage element which
will store data whenever the clk input line transitions from low to high (ZERO to ONE).
The value stored (i.e., the out value) will depend on the s and r input pin values, and
will be:
out=ONE
out=ZERO
out=previous value
out=UNKNOWN

if
if
if
if

s=ONE and r=ZERO;


s=ZERO and r=ONE;
s=ZERO and r=ZERO;
s=ONE and r=ONE;

In addition, asynchronous set and reset signals exist, and each of the three methods of changing
the stored output of the d_srff have separate load values and delays associated with them. You
may also specify separate rise and fall delay values that are added to those specified for the
input lines; these allow for more faithful reproduction of the output characteristics of different
IC fabrication technologies.
Note that any UNKNOWN inputs other than s and r immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a8 2 12 4 5 6 3 14 flop7
.model flop7 d_srff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9)

12.4. DIGITAL MODELS

12.4.16

209

D Latch

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

cm_d_dlatch
d_dlatch
"digital d-type latch"
data
"input data"
in
d
[d]
no
no

enable
"enable input"
in
d
[d]
no
no

set
"set"
in
d
[d]
no
yes

reset
"reset"
in
d
[d]
no
yes

out
"data output"
out
d
[d]
no
no

Nout
"inverter data output"
out
d
[d]
no
no

data_delay
"delay from data"
real
1.0e-9
[1.0e-12 -]
no
yes
enable_delay
"delay from enable"
real
1.0e-9
[1.0e-12 -]
no

set_delay
"delay from SET"
real
1.0e-9
[1.0e-12 -]
no

210

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

yes

yes

reset_delay
"delay from RESET"
real
1.0e-9
[1.0e-12 -]
no
yes

ic
"output initial state"
boolean
0
no
yes

data_load
"data load (F)"
real
1.0e-12
no
yes

enable_load
"enable load value (F)"
real
1.0e-12
no
yes

set_load
"set load value (F)"
real
1.0e-12
no
yes

reset_load
"reset load (F)"
real
1.0e-12
no
yes

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The digital d-type latch is a one-bit, level-sensitive storage element which will
output the value on the data line whenever the enable input line is high (ONE). The
value on the data line is stored (i.e., held on the out line) whenever the enable line is low
(ZERO).
In addition, asynchronous set and reset signals exist, and each of the four methods of
changing the stored output of the d_dlatch (i.e., data changing with enable=ONE, enable
changing to ONE from ZERO with a new value on data, raising set and raising reset) have
separate delays associated with them. You may also specify separate rise and fall delay
values that are added to those specified for the input lines; these allow for more faithful

12.4. DIGITAL MODELS

211

reproduction of the output characteristics of different IC fabrication technologies.


Note that any UNKNOWN inputs other than on the data line when enable=ZERO immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a4 12 4 5 6 3 14 latch1
.model latch1 d_dlatch(data_delay = 13.0e-9 enable_delay = 22.0e-9
+
set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2
+
rise_delay = 10.0e-9 fall_delay = 3e-9)

12.4.17

Set-Reset Latch

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:

cm_d_srlatch
d_srlatch
"digital sr-type latch"
s
"set"
in
d
[d]
yes
[2 -]
no

r
"reset"
in
d
[d]
yes
r
no

enable
"enable"
in
d
[d]
no
no
set
"set"
in
d
[d]
no
yes

reset
"reset"
in
d
[d]
no
yes

out
"data output"
out

Nout
"inverted data output"
out

212

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Default_Type:
Allowed_Types:
Vector: no no
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

d
[d]

d
[d]

no

no

sr_delay
"delay from s or r input change"
real
1.0e-9
[1.0e-12 -]
no
yes
enable_delay
"delay from enable"
real
1.0e-9
[1.0e-12 -]
no
yes

set_delay
"delay from SET"
real
1.0e-9
[1.0e-12 -]
no
yes

reset_delay
"delay from RESET"
real
1.0e-9
[1.0e-12 -]
no
yes

ic
"output initial state"
boolean
0
no
yes

sr_load
enable_load
"s & r input loads (F)" "enable load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes
set_load
"set load value (F)"
real
1.0e-12
no

reset_load
"reset load (F)"
real
1.0e-12
no

12.4. DIGITAL MODELS

213

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

yes

yes

rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes

Description: The digital sr-type latch is a one-bit, level-sensitive storage element which will
output the value dictated by the state of the s and r pins whenever the enable input line
is high (ONE). This value is stored (i.e., held on the out line) whenever the enable line is
low (ZERO). The particular value chosen is as shown below:

s=ZERO, r=ZERO =>


s=ZERO, r=ONE
s=ONE, r=ZERO
s=ONE, r=ONE

out=current value (i.e., not change in output)


=> out=ZERO
=> out=ONE
=> out=UNKNOWN

Asynchronous set and reset signals exist, and each of the four methods of changing the stored
output of the d srlatch (i.e., s/r combination changing with enable=ONE, enable changing to
ONE from ZERO with an output-changing combination of s and r, raising set and raising reset) have separate delays associated with them. You may also specify separate rise and fall
delay values that are added to those specified for the input lines; these allow for more faithful
reproduction of the output characteristics of different IC fabrication technologies.
Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a4 12 4 5 6 3 14 16 latch2
.model latch2 d_srlatch(sr_delay = 13.0e-9 enable_delay = 22.0e-9
+
set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2
+
rise_delay = 10.0e-9 fall_delay = 3e-9)

12.4.18

State Machine

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:

cm_d_state
d_state
"digital state machine"
in

clk

214

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:

"input"
in
d
[d]
yes
[1 -]
yes

"clock"
in
d
[d]
no
no

reset
"reset"
in
d
[d]
no
yes

out
"output"
out
d
[d]
yes
[1 -]
no

clk_delay
reset_delay
"delay from CLK"
"delay from RESET"
real
real
1.0e-9
1.0e-9
[1.0e-12 -]
[1.0e-12 -]
no
no
yes
yes
Parameter_Name:
state_file
"state transition specification file name"
string
"state.txt"
no
no
reset_state
"default state on RESET & at DC"
int
0
no
no
input_load
"input loading capacitance (F)"
real
1.0e-12
-

12.4. DIGITAL MODELS

Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

215

no
yes
clk_load
"clock loading capacitance (F)"
real
1.0e-12
no
yes
reset_load
"reset loading capacitance (F)"
real
1.0e-12
no
yes

Description: The digital state machine provides for straightforward descriptions of clocked
combinatorial logic blocks with a variable number of inputs and outputs and with an
unlimited number of possible states. The model can be configured to behave as virtually
any type of counter or clocked combinatorial logic block and can be used to replace very
large digital circuit schematics with an identically functional but faster representation.
The d state model is configured through the use of a state definition file (state.in) which
resides in a directory of your choosing. The file defines all states to be understood by the
model, plus input bit combinations which trigger changes in state. An example state.in
file is shown below:
----------- begin file ------------* This is an example state.in file. This file
* defines a simple 2-bit counter with one input. The
* value of this input determines whether the counter counts
* up (in = 1) or down (in = 0).
0 0s 0s 0 -> 3
1 -> 1
1 0s 1z 0 -> 0
1 -> 2
2 1z 0s 0 -> 1
1 -> 3
3 1z 1z 0 -> 2
3 1z 1z 1 -> 0
------------------ end file --------------Several attributes of the above file structure should be noted. First, ALL LINES IN THE FILE
MUST BE ONE OF FOUR TYPES. These are:

216

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

1. A comment, beginning with a * in the first column.


2. A header line, which is a complete description of the current state, the outputs corresponding to that state, an input value, and the state that the model will assume should that
input be encountered. The first line of a state definition must ALWAYS be a header line.
3. A continuation line, which is a partial description of a state, consisting of an input value
and the state that the model will assume should that input be encountered. Note that
continuation lines may only be used after the initial header line definition for a state.
4. A line containing nothing but white-spaces (space, form-feed, newline, carriage return,
tab, vertical tab).
A line which is not one of the above will cause a file-loading error. Note that in the example
shown, whitespace (any combination of blanks, tabs, commas) is used to separate values, and
that the character "->" is used to underline the state transition implied by the input preceding it.
This particular character is not critical in of itself, and can be replaced with any other character
or non-broken combination of characters that you prefer (e.g. ==>, >>, :, resolves_to,
etc.)
The order of the output and input bits in the file is important; the first column is always interpreted to refer to the zeroth bit of input and output. Thus, in the file above, the output from
state 1 sets out[0] to 0s, and out[1] to 1z.
The state numbers need not be in any particular order, but a state definition (which consists of
the sum total of all lines which define the state, its outputs, and all methods by which a state can
be exited) must be made on contiguous line numbers; a state definition cannot be broken into
sub-blocks and distributed randomly throughout the file. On the other hand, the state definition
can be broken up by as many comment lines as you desire.
Header files may be used throughout the state.in file, and continuation lines can be discarded
completely if you so choose: continuation lines are primarily provided as a convenience.
Example SPICE Usage:
a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state1
.model state1 d_state(clk_delay = 13.0e-9 reset_delay = 27.0e-9
+
state_file = "newstate.txt" reset_state = 2)

12.4.19

Frequency Divider

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:

cm_d_fdiv
d_fdiv
"digital frequency divider"
freq_in
"frequency input"
in
d
[d]

freq_out
"frequency output"
out
d
[d]

12.4. DIGITAL MODELS

Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

217

no
no

no
no

div_factor
"divide factor"
int
2
[1 -]
no
yes

high_cycles
"# of cycles for high out"
int
1
[1 div_factor-1]
no
yes

i_count
"divider initial count value"
int
0
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
yes
in
yes

fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
yes
in
yes

freq_in_load
"freq_in load value (F)"
real
1.0e-12
no
yes

Description: The digital frequency divider is a programmable step-down divider which accepts
an arbitrary divisor (div_factor), a duty-cycle term (high_cycles), and an initial count
value (i_count). The generated output is synchronized to the rising edges of the input
signal. Rise delay and fall delay on the outputs may also be specified independently.
Example SPICE Usage:
a4 3 7 divider
.model divider d_fdiv(div_factor = 5 high_cycles = 3

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CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

+
+

12.4.20

i_count = 4 rise_delay = 23e-9


fall_delay = 9e-9)

RAM

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:

cm_d_ram
d_ram
"digital random-access memory"
data_in
"data input line(s)"
in
d
[d]
yes
[1 -]
no

data_out
"data output line(s)"
out
d
[d]
yes
data_in
no

address
write_en
"address input line(s)" "write enable line"
in
in
d
d
[d]
[d]
yes
no
[1 -]
no
no
select
"chip select line(s)"
in
d
[d]
yes
[1 16]
no
select_value
"decimal active value for select line comparison"
int
1
[0 32767]
no
yes
ic
"initial bit state @ dc"

12.4. DIGITAL MODELS

Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

219

int
2
[0 2]
no
yes
read_delay
"read delay from address/select/write.en active"
real
100.0e-9
[1.0e-12 -]
no
yes
data_load
address_load
"data_in load value (F)" "addr. load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes
select_load
"select load value (F)"
real
1.0e-12
no
yes
enable_load
"enable line load value (F)"
real
1.0e-12
no
yes

Description: The digital RAM is an M-wide, N-deep random access memory element with
programmable select lines, tristated data out lines, and a single write/~read line. The
width of the RAM words (M) is set through the use of the word width parameter. The
depth of the RAM (N) is set by the number of address lines input to the device. The value

220

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE


of N is related to the number of address input lines (P) by the following equation:
2P = N
There is no reset line into the device. However, an initial value for all bits may be specified
by setting the ic parameter to either 0 or 1. In reading a word from the ram, the read delay
value is invoked, and output will not appear until that delay has been satisfied. Separate
rise and fall delays are not supported for this device.
Note that UNKNOWN inputs on the address lines are not allowed during a write. In
the event that an address line does indeed go unknown during a write, THE ENTIRE
CONTENTS OF THE RAM WILL BE SET TO UNKNOWN. This is in contrast to the
data in lines being set to unknown during a write; in that case, only the selected word
will be corrupted, and this is corrected once the data lines settle back to a known value.
Note that protection is added to the write en line such that extended UNKNOWN values
on that line are interpreted as ZERO values. This is the equivalent of a read operation and
will not corrupt the contents of the RAM. A similar mechanism exists for the select lines.
If they are unknown, then it is assumed that the chip is not selected.
Detailed timing-checking routines are not provided in this model, other than for the enable
delay and select delay restrictions on read operations. You are advised, therefore, to
carefully check the timing into and out of the RAM for correct read and write cycle
times, setup and hold times, etc. for the particular device they are attempting to model.
Example SPICE Usage:
a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2
.model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e-9)

12.4.21

Digital Source

NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:

cm_d_source
d_source
"digital signal source"
out
"output"
out
d
[d]
yes
no
input_file
"digital input vector filename"
string
"source.txt"
no

12.4. DIGITAL MODELS

Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:

221

no
input_load
"input loading capacitance (F)"
real
1.0e-12
no
no

Description: The digital source provides for straightforward descriptions of digital signal vectors in a tabular format. The model reads input from the input file and, at the times
specified in the file, generates the inputs along with the strengths listed.
The format of the input file is as shown below. Note that comment lines are delineated through
the use of a single * character in the first column of a line. This is similar to the way
the SPICE program handles comments.
* T
* i
* m
* e
*
0.0000
1.234e-9
1.376e-9
2.5e-7
2.5006e-7
5.0e-7

c
l
o
c
k
Uu
0s
0s
1s
1s
0s

n
o
d
e
a
Uu
1s
0s
0s
1s
1s

n
o
d
e
b
Us
1s
1s
1s
1s
1s

n . . .
o . . .
d . . .
e . . .
c . . .
Uu . . .
0z . . .
0z . . .
0z . . .
0z . . .
0z . . .

Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used
to separate the time and state/strength tokens. The order of the input columns is important; the
first column is always interpreted to mean time. The second through the Nth columns map
to the out[0] through out[N-2] output nodes. A non-commented line which does not contain
enough tokens to completely define all outputs for the digital source will cause an error. Also,
time values must increase monotonically or an error will result in reading the source file.
Errors will also occur if a line exists in source.txt which is neither a comment nor vector line.
The only exception to this is in the case of a line that is completely blank; this is treated as
a comment (note that such lines often occur at the end of text within a file; ignoring these in
particular prevents nuisance errors on the part of the simulator).
Example SPICE Usage:
a3 [2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17] input_vector
.model input_vector d_source(input_file = "source_simple.text")

222

12.5

CHAPTER 12. MIXED-MODE AND BEHAVIORAL MODELING WITH XSPICE

Predefined Node Types for event driven simulation

The following prewritten node types are included with the XSPICE simulator. These should
provide you not only with valuable event-driven modeling capabilities, but also with examples
to use for guidance in creating new UDN (user defined node) types. You may access these node
data by the plot (17.5.43) or eprint (17.5.23) commands.

12.5.1

Digital Node Type

The digital node type is directly built into the simulator. 12 digital node values are available.
They are described by a two character string (the state/strength token). The first character (0,
1, or U) gives the state of the node (logic zero, logic one, or unknown logic state). The second
character (s, r, z, u) gives the "strength" of the logic state (strong, resistive, hi-impedance, or
undetermined). So these are the values we have: 0s, 1s, Us, 0r, 1r, Ur, 0z, 1z, Uz, 0u, 1u, Uu.

12.5.2

Real Node Type

The real node type provides for event-driven simulation with double-precision floating point
data. This type is useful for evaluating sampled-data filters and systems. The type implements
all optional functions for User-Defined Nodes, including inversion and node resolution. For
inversion, the sign of the value is reversed. For node resolution, the resultant value at a node is
the sum of all values output to that node. The node is implemented as a user defined node in
ngspice/src/xspice/icm/xtraevt/real.

12.5.3

Int Node Type

The int node type provides for event-driven simulation with integer data. This type is useful
for evaluating round-off error effects in sampled-data systems. The type implements all optional
functions for User-Defined Nodes, including inversion and node resolution. For inversion, the
sign of the integer value is reversed. For node resolution, the resultant value at a node is the
sum of all values output to that node. The node is implemented as a user defined node in
ngspice/src/xspice/icm/xtraevt/int.

12.5.4

(Digital) Input/Output

The analog code models use the standard (analog) nodes provided by ngspice and thus are using
all the commands for sourcing, storing, printing, and plotting data.
I/O for event nodes (digital, real, int, and UDNs) currently is much more limited to a few tools.
For output you may use the plot (17.5.43) or eprint (17.5.23) commands. For input, you may
create a test bench with existing code models (oscillator (12.3.3), frequency divider (12.4.19),
state machine (12.4.18) etc.). Reading data from a file is offered by d_source (12.4.21). Some
comments and hints have been provided by Sdaau. You may also use the analog input from file,
(filesource 12.2.8) and convert its analog input to the digital type by the adc_bridge (12.3.2). If
you want reading data from a VCD file, you may have a look at ngspice-users forum and apply
a python script provided by Sdaau to translate the VCD data to d_source or filesource input.

Chapter 13
Verilog A Device models
13.1

Introduction

The ngspice-adms interface will implement extra HICUM level0 and level2 (HICUM model
web page), MEXTRAM(MEXTRAM model web page), EKV(EKV model web page) and
PSP(NXP MOS model 9 web page) models written in Verilog-A behavior language.

13.2

adms

To compile Verilog-A compact models into ngspice-ready C models the the program admsXml
is required. Details of this software are described in adms home page.

13.3

How to integrate a Verilog-A model into ngspice

13.3.1

How to setup a *.va model for ngspice

The root entry for new Verilog-A models is \src\spicelib\devices\adms. Below the modelname
entry the Verilog-A code should reside in folder admsva
(e.g.: ngspice\src\spicelib\devices\adms\ekv\admsva\ekv.va). The file extension is fixed to .va.
Certain files must modified to create the interface to ngspice - see the guideline README.adms
in the ngspice root.

13.3.2

Adding admsXml to your build environment

To facilitate the installation of adms, a source code package has been assembled for use with
ngspice, available as a zip file for download. It is based on adms source code from the subversion repository downloaded on August 1st, 2010, and has been slightly modified (see ChangeLog).
Under OS LINUX (tested with SUSE 11.2, 64 bit) you may expand the zip file and run
./autogen_lin.sh, followed by make and make install.

223

224

CHAPTER 13. VERILOG A DEVICE MODELS

Under OS CYGWIN (tested with actual CYGWIN on MS Windows 7, 64 bit), please use
./autogen_cyg.sh, followed by make and make install.
Under OS MINGW, a direct compilation would require the additional installation of perl module
XML-LibXML which is not as straightforward as it should be. However you may start with a
CYGWIN compile as described above. If you then go to your MSYS window, cd to the adms
top directory and start ./mingw-compile.sh, you will obtain admsXml.exe, copied to MSYS
/bin, and you are ready to go. To facilitate installation under MS Windows, a admsXml.exe
zipped binary is available. Just copy it to MSYS /bin directory and start working on your verilog
models.
A short test of a successful installation is:
$ admsXml -v
$ [usage..] release name="admsXml" version="2.3.0" date="Aug 4 2010"
time="10:24:18"
Compilation of admsXml with MS Visual Studio is not possible, because the source code has
variable declarations not only at the top of a block, but deliberately also in the following lines.
This is o.k. by the C99 standard, but not supported by MS Visual Studio.

Chapter 14
Mixed-Level Simulation (ngspice with
TCAD)
14.1

Cider

Ngspice implements mixed-level simulation through the merging of its code with CIDER (details see chapt. 30).
CIDER is a mixed-level circuit and device simulator that provides a direct link between technology parameters and circuit performance. A mixed-level circuit and device simulator can
provide greater simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the critical devices in a circuit. Compact models can be used for noncritical
devices.
CIDER couples the latest version of SPICE3 (version 3F.2) [JOHN92] to a internal C-based
device simulator, DSIM. SPICE3 provides circuit analyses, compact models for semiconductor
devices, and an interactive user interface. DSIM provides accurate, one- and two-dimensional
numerical device models based on the solution of Poissons equation, and the electron and
hole current-continuity equations. DSIM incorporates many of the same basic physical models
found in the the Stanford two-dimensional device simulator PISCES [PINT85]. Input to CIDER
consists of a SPICE-like description of the circuit and its compact models, and PISCES-like
descriptions of the structures of numerically modeled devices. As a result, CIDER should seem
familiar to designers already accustomed to these two tools. For example, SPICE3F.2 input files
should run without modification, producing identical results.
CIDER is based on the mixed-level circuit and device simulator CODECS [MAYA88] and is a
replacement for this program. The basic algorithms of the two programs are the same. Some of
the differences between CIDER and CODECS are described below. The CIDER input format
has greater flexibility and allows increased access to physical model parameters. New physical
models have been added to allow simulation of state-of-the-art devices. These include transverse field mobility degradation [GATE90] that is important in scaled-down MOSFETs and a
polysilicon model for poly-emitter bipolar transistors. Temperature dependence has been included for most physical models over the range from -50C to 150C. The numerical models
can be used to simulate all the basic types of semiconductor devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a
substrate contact. Support has been added for the management of device internal states. Postprocessing of device states can be performed using the NUTMEG user interface of SPICE3.

225

226

CHAPTER 14. MIXED-LEVEL SIMULATION (NGSPICE WITH TCAD)

Previously computed states can be loaded into the program to provide accurate initial guesses
for subsequent analyses. Finally, numerous small bugs have been discovered and fixed, and the
program has been ported to a wider variety of computing platforms.
Berkeley tradition calls for the naming of new versions of programs by affixing a (number,
letter, number) triplet to the end of the program name. Under this scheme, CIDER should
instead be named CODECS2A.l. However, tradition has been broken in this case because major
incompatibilities exist between the two programs and because it was observed that the acronym
CODECS is already used in the analog design community to refer to coder-decoder circuits.
Details of the basic semiconductor equations and the physical models used by CIDER are not
provided in this manual. Unfortunately, no other single source exists which describes all of
the relevant background material. Comprehensive reviews of device simulation can be found
in [PINT90] and the book [SELB84]. CODECS and its inversion-layer mobility model are
described in [MAYA88] and LGATE90], respectively. PISCES and its models are described in
[PINT85]. Temperature dependencies for the PISCES models used by CIDER are available in
[SOLL90].

14.2

GSS, Genius

For LINUX users the cooperation of the TCAD software GSS with ngspice might be of interest,
see http://ngspice.sourceforge.net/gss.html. This project is no longer maintained however, but
has moved into the Genius simulator, still available as open source cogenda genius.

Chapter 15
Analyses and Output Control (batch
mode)
The command lines described in this chapter are specifying analyses and outputs within the
circuit description file. They start with a . (dot commands). Specifying analyses and plots
(or tables) in the input file with dot commands is used with batch runs. Batch mode is entered
when either the -b option is given upon starting ngspice
ngspice -b -r rawfile.raw circuitfile.cir
or when the default input source is redirected from a file (see also chapt. 16.4.1).
ngspice < circuitfile.cir
In batch mode, the analyses specified by the control lines in the input file (e.g. .ac, .tran,
etc.) are immediately executed. If the -r rawfile option is given then all data generated is
written to a ngspice rawfile. The rawfile may later be read by the interactive mode of ngspice
using the load command (see 17.5.36). In this case, the .save line (see 15.5) may be used to
record the value of internal device variables (see Appendix, chapter 31).
If a rawfile is not specified, then output plots (in line-printer form) and tables can be printed
according to the .print, .plot, and .four control lines, described in chapter 15.5.
If ngspice is started in interactive mode (see chapt. 16.4.2), like
ngspice circuitfile.cir
and no control section (.control ... .endc, see 16.4.3) is provided in the circuit file, the dot
commands are not executed immediately, but are waiting for manually receiving the command
run.

15.1

Simulator Variables (.options)

Various parameters of the simulations available in Ngspice can be altered to control the accuracy, speed, or default values for some devices. These parameters may be changed via the
option command (described in chapt. 17.5.42) or via the .options line:

227

228

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

General form:
. options opt1 opt2 . . . ( or opt= optval

...)

Examples:
. o p t i o n s r e l t o l = . 0 0 5 t r t o l =8
The options line allows the user to reset program control and user options for specific simulation
purposes. Options specified to Ngspice via the option command (see chapt. ) are also
passed on as if specified on a .options line. Any combination of the following options may
be included, in any order. x (below) represents some positive number.

15.1.1

General Options

ACCT causes accounting and run time statistics to be printed.


NOACCT no printing of statistics, no printing of the Initial Transient Solution.
NOINIT suppresses only printing of the Initial Transient Solution, maybe combined with
ACCT.
LIST causes the summary listing of the input data to be printed.
NOMOD suppresses the printout of the model parameters.
NOPAGE suppresses page ejects.
NODE causes the printing of the node table.
OPTS causes the option values to be printed.
TEMP=x Resets the operating temperature of the circuit. The default value is 27 C (300K).
TEMP can be overridden per device by a temperature specification on any temperature
dependent instance. May also be generally overridden by a .TEMP card (2.11).
TNOM=x resets the nominal temperature at which device parameters are measured. The default value is 27 C (300 deg K). TNOM can be overridden by a specification on any
temperature dependent device model.

15.1.2

DC Solution Options

The following options controls properties pertaining to DC analysis and algorithms. Since
transient analysis is based on DC many of the options affect the latter one.
ABSTOL=x resets the absolute current error tolerance of the program. The default value is 1
pA.
GMIN=x resets the value of GMIN, the minimum conductance allowed by the program. The
default value is 1.0e-12.
ITL1=x resets the dc iteration limit. The default is 100.

15.1. SIMULATOR VARIABLES (.OPTIONS)

229

ITL2=x resets the dc transfer curve iteration limit. The default is 50.
KEEPOPINFO Retain the operating point information when either an AC, Distortion, or PoleZero analysis is run. This is particularly useful if the circuit is large and you do not want
to run a (redundant) ".OP" analysis.
PIVREL=x resets the relative ratio between the largest column entry and an acceptable pivot
value. The default value is 1.0e-3. In the numerical pivoting algorithm the allowed minimum pivot value is determined by EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL)
where MAXVAL is the maximum element in the column where a pivot is sought (partial
pivoting).
PIVTOL=x resets the absolute minimum value for a matrix entry to be accepted as a pivot.
The default value is 1.0e-13.
RELTOL=x resets the relative error tolerance of the program. The default value is 0.001
(0.1%).
RSHUNT=x introduces a resistor from each analog node to ground. The value of the resistor
should be high enough to not interfere with circuit operations. The XSPICE option has to
be enabled (see 32.1.5) .
VNTOL=x resets the absolute voltage error tolerance of the program. The default value is 1
V .
15.1.2.1

Matrix Conditioning info

In most SPICE-based simulators, problems can arise with certain circuit topologies. One of
the most common problems is the absence of a DC path to ground at some node. This may
happen, for example, when two capacitors are connected in series with no other connection at
the common node or when certain code models are cascaded. The result is an ill-conditioned
or nearly singular matrix that prevents the simulation from completing. The XSPICE option
introduces the rshunt option to help eliminate this problem. When used, this option inserts
resistors to ground at all the analog nodes in the circuit. In general, the value of rshunt should
be set to some very high resistance (e.g. 1000 Meg Ohms or greater) so that the operation of the
circuit is essentially unaffected, but the matrix problems are corrected. If you should encounter
a no DC path to ground or a matrix is nearly singular error message with your circuit, you
should try adding the following .option card to your circuit description deck.
.option rshunt = 1.0e12
Usually a value of 1.0e12 is sufficient to correct the matrix problems. However, if you still have
problems, you may wish to try lowering this value to 1.0e10 or 1.0e9.
Another matrix conditioning problem might occur if you try to place an inductor in parallel to
a voltage source. An ac simulation will fail, because it is preceded by an op analysis. Option
noopac (15.1.3) will help if the circuit is linear. If the circuit is non-linear, you will need the
op analysis. Then adding a small resistor (e.g. 1e-4 Ohms) in series to the inductor will help to
obtain convergence.

230

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

.option rseries = 1.0e-4


will add a series resistor to each inductor in the circuit. Be careful if you use behavioral inductors (see 3.2.12), because the result may become unpredictable.

15.1.3

AC Solution Options

NOOPAC Do not do an operating point (OP) analysis before the AC analysis. To become
valid, this option requires that the circuit is linear, thus consists only of R, L, and C
devices, independent V, I sources and linear dependent E, G, H, and F sources (without
poly statement, non-behavioral). If a non-linear device is detected, the OP analysis will
be executed automatically. This option is of interest for example in nested LC circuits,
where there is no series resistance for the L device given, which during OP analysis may
result in an ill formed matrix, yields an error message and aborts the simulation.

15.1.4

Transient Analysis Options

AUTOSTOP stops a transient analysis after successfully calculating all measure functions
(15.4) specified with the dot command .meas. autostop is not available with meas (17.5.37)
used in control mode.
CHGTOL=x resets the charge tolerance of the program. The default value is 1.0e-14.
CONVSTEP=x relative step limit applied to code models.
CONVABSSTEP=x absolute step limit applied to code models.
GMINSTEPS=x [*] sets number of Gmin steps to be attempted. If the value is set to zero, the
gmin stepping algorithm is disabled. In such case the source stepping algorithm becomes
the standard when the standard procedure fails to converge to a solution.
ITL3=x resets the lower transient analysis iteration limit. the default value is 4. (Note: not
implemented in Spice3).
ITL4=x resets the transient analysis time-point iteration limit. the default is 10.
ITL5=x resets the transient analysis total iteration limit. the default is 5000. Set ITL5=0 to
omit this test. (Note: not implemented in Spice3).
ITL6=x [*] synonym for SRCSTEPS.
MAXEVITER=x sets the number of event iterations that are allowed at an analysis point
MAXOPALTER=x specifies the maximum number of analog/event alternations that the simulator can use in solving a hybrid circuit.
MAXORD=x [*] specifies the maximum order for the numerical integration method used by
SPICE. Possible values for the Gear method are from 2 (the default) to 6. Using the value
1 with the trapezoidal method specifies backward Euler integration.

15.1. SIMULATOR VARIABLES (.OPTIONS)

231

METHOD=name sets the numerical integration method used by SPICE. Possible names are
"Gear" or "trapezoidal" (or just "trap"). The default is trapezoidal.
NOOPALTER=TRUE|FALSE if set to false alternations between analog/event are enabled.
RAMPTIME=x this options sets the rate of change of independent supplies and code model
inductors and capacitors with initial conditions specified.
SRCSTEPS=x [*] a non-zero value causes SPICE to use a source-stepping method to find the
DC operating point. Its value specifies the number of steps.
TRTOL=x resets the transient error tolerance. The default value is 7. This parameter is an estimate of the factor by which ngspice overestimates the actual truncation error. If XSPICE
is enabled and A devices included, the value is internally set to 1 for higher precision.
This will cost a factor of two in CPU time during transient analysis.

15.1.5

MOSFET Specific options

BADMOS3 Use the older version of the MOS3 model with the kappa discontinuity.
DEFAD=x resets the value for MOS drain diffusion area; the default is 0.0.
DEFAS=x resets the value for MOS source diffusion area; the default is 0.0.
DEFL=x resets the value for MOS channel length; the default is 100.0 m.
DEFW=x resets the value for MOS channel width; the default is 100.0 m.

15.1.6

Transmission Lines Specific Options

TRYTOCOMPACT Applicable only to the LTRA model (see 6.2.1). When specified, the
simulator tries to condense LTRA transmission lines past history of input voltages and
currents.

15.1.7

Precedence of option and .options commands

There are various ways to set the above mentioned options in Ngspice. If no option or
.options lines are set by the user, internal default values are given for each of the simulator variables.
You may set options in the init files spinit or .spiceinit via the option command (see chapt.
17.5.42). The values given here will supersede the default values. If you set options via the
.options line in your input file, their values will supersede the default and init file data. Finally
if you set options inside a .control ... .endc section, these values will supersede any values of
the respective simulator variables given so far.

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15.2

Initial Conditions

15.2.1

.NODESET: Specify Initial Node Voltage Guesses

General form:
. NODESET V(NODNUM) =VAL V(NODNUM) =VAL . . .
. NODESET ALL=VAL
Examples:
. NODESET V( 1 2 ) = 4 . 5 V( 4 ) = 2 . 2 3
. NODESET ALL= 1 . 5
The .nodeset line helps the program find the dc or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages. The restriction is then released
and the iteration continues to the true solution. The .nodeset line may be necessary for convergence on bistable or a-stable circuits. .nodeset all=val allows to set all starting node
voltages (except for the ground node) in a single line. In general, the .nodeset line should not
be necessary.

15.2.2

.IC: Set Initial Conditions

General form:
. i c v ( nodnum ) = v a l v ( nodnum ) = v a l

...

Examples:
. i c v ( 1 1 ) = 5 v (4)= 5 v ( 2 ) = 2 . 2
The .ic line is for setting transient initial conditions. It has two different interpretations, depending on whether the uic parameter is specified on the .tran control line. Also, one should
not confuse this line with the .nodeset line. The .nodeset line is only to help dc convergence,
and does not affect final bias solution (except for multi-stable circuits). The two interpretations
of this line are as follows:
1. When the uic parameter is specified on the .tran line, then the node voltages specified
on the .ic control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET
initial conditions. This is equivalent to specifying the ic=... parameter on each device
line, but is much more convenient. The ic=... parameter can still be specified and takes
precedence over the .ic values. Since no dc bias (initial transient) solution is computed
before the transient analysis, one should take care to specify all dc source voltages on the
.ic control line if they are to be used to compute device initial conditions.
2. When the uic parameter is not specified on the .tran control line, the dc bias (initial
transient) solution is computed before the transient analysis. In this case, the node voltages specified on the .ic control line is forced to the desired initial values during the
bias solution. During transient analysis, the constraint on these node voltages is removed.
This is the preferred method since it allows ngspice to compute a consistent dc solution.

15.3. ANALYSES

15.3

Analyses

15.3.1

.AC: Small-Signal AC Analysis

233

General form:
. a c d e c nd f s t a r t f s t o p
. a c o c t no f s t a r t f s t o p
. a c l i n np f s t a r t f s t o p
Examples:
. a c d e c 10 1 10K
. a c d e c 10 1K 100MEG
. a c l i n 100 1 100HZ

dec stands for decade variation, and nd is the number of points per decade. oct stands for
octave variation, and no is the number of points per octave. lin stands for linear variation, and
np is the number of points. fstart is the starting frequency, and fstop is the final frequency.
If this line is included in the input file, ngspice performs an AC analysis of the circuit over the
specified frequency range. Note that in order for this analysis to be meaningful, at least one
independent source must have been specified with an ac value. Typically it does not make much
sense to specify more than one ac source. If you do, the result will be a superposition of all
sources, thus difficult to interpret.

Example:
B a s i c RC c i r c u i t
r 1 2 1.0
c 2 0 1.0
v i n 1 0 dc 0 a c 1 $ < t h e a c s o u r c e
. options noacct
. a c d e c 10 . 0 1 10
. p l o t a c vdb ( 2 ) x l o g
. end

In this ac (or small signal) analysis all non-linear devices are linearized around their actual dc
operating point. All Ls and Cs get their imaginary value, depending on the actual frequency
step. Each output vector will be calculated relative to the input voltage (current) given by the ac
value (Vin equals to 1 in the example above). The resulting node voltages (and branch currents)
are complex vectors. Therefore you have to be careful using the plot command. Especially you
may use the variants of vxx(node) described in chapter 15.5.2 like vdb(2) (see example above).

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CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

15.3.2

.DC: DC Transfer Function

General form:
. dc s r c n a m v s t a r t v s t o p v i n c r [ s r c 2 s t a r t 2 s t o p 2 i n c r 2 ]
Examples:
. dc
. dc
. dc
. dc
. dc

VIN 0 . 2 5
VDS 0 10
VCE 0 10
RLoad 1k
TEMP 15

5.0 0.25
. 5 VGS 0 5 1
. 2 5 IB 0 10U 1U
2k 100
75 5

The .dc line defines the dc transfer curve source and sweep limits (again with capacitors open
and inductors shorted). srcnam is the name of an independent voltage or current source, a
resistor or the circuit temperature. vstart, vstop, and vincr are the starting, final, and incrementing values respectively. The first example causes the value of the voltage source VIN
to be swept from 0.25 Volts to 5.0 Volts in increments of 0.25 Volts. A second source (src2)
may optionally be specified with associated sweep parameters. In this case, the first source is
swept over its range for each value of the second source. This option can be useful for obtaining
semiconductor device output characteristics. See the example circuit description on transistor
characteristics (21.3).

15.3.3

.DISTO: Distortion Analysis

General form:
. d i s t o d e c nd f s t a r t f s t o p < f 2 o v e r f 1 >
. d i s t o o c t no f s t a r t f s t o p < f 2 o v e r f 1 >
. d i s t o l i n np f s t a r t f s t o p < f 2 o v e r f 1 >
Examples:
. d i s t o d e c 10 1kHz 100Mhz
. d i s t o d e c 10 1kHz 100Mhz 0 . 9
The .disto line does a small-signal distortion analysis of the circuit. A multi-dimensional
Volterra series analysis is done using multi-dimensional Taylor series to represent the nonlinearities at the operating point. Terms of up to third order are used in the series expansions.
If the optional parameter f2overf1 is not specified, .disto does a harmonic analysis - i.e.,
it analyses distortion in the circuit using only a single input frequency F1 , which is swept as
specified by arguments of the .disto command exactly as in the .ac command. Inputs at this
frequency may be present at more than one input source, and their magnitudes and phases are
specified by the arguments of the distof1 keyword in the input file lines for the input sources
(see the description for independent sources). (The arguments of the distof2 keyword are not
relevant in this case).
The analysis produces information about the AC values of all node voltages and branch currents
at the harmonic frequencies 2F1 and , vs. the input frequency F1 as it is swept. (A value of 1
(as a complex distortion output) signifies cos(2(2F1 )t) at 2F1 and cos(2(3F1 )t) at 3F1 , using

15.3. ANALYSES

235

the convention that 1 at the input fundamental frequency is equivalent to cos(2F1t).) The
distortion component desired (2F1 or 3F1 ) can be selected using commands in ngnutmeg, and
then printed or plotted. (Normally, one is interested primarily in the magnitude of the harmonic
components, so the magnitude of the AC distortion value is looked at). It should be noted that
these are the AC values of the actual harmonic components, and are not equal to HD2 and HD3.
To obtain HD2 and HD3, one must divide by the corresponding AC values at F1 , obtained from
an .ac line. This division can be done using ngnutmeg commands.
If the optional f2overf1 parameter is specified, it should be a real number between (and not
equal to) 0.0 and 1.0; in this case, .disto does a spectral analysis. It considers the circuit with
sinusoidal inputs at two different frequencies F1 and F2 . F1 is swept according to the .disto
control line options exactly as in the .ac control line. F2 is kept fixed at a single frequency
as F1 sweeps - the value at which it is kept fixed is equal to f2overf1 times fstart. Each
independent source in the circuit may potentially have two (superimposed) sinusoidal inputs
for distortion, at the frequencies F1 and F2 . The magnitude and phase of the F1 component are
specified by the arguments of the distof1 keyword in the sources input line (see the description of independent sources); the magnitude and phase of the F2 component are specified by the
arguments of the distof2 keyword. The analysis produces plots of all node voltages/branch
currents at the intermodulation product frequencies F1 + F2 , F1 F2 , and (2F1 ) F2 , vs the
swept frequency F1 . The IM product of interest may be selected using the setplot command,
and displayed with the print and plot commands. It is to be noted as in the harmonic analysis
case, the results are the actual AC voltages and currents at the intermodulation frequencies, and
need to be normalized with respect to .ac values to obtain the IM parameters.
If the distof1 or distof2 keywords are missing from the description of an independent
source, then that source is assumed to have no input at the corresponding frequency. The default
values of the magnitude and phase are 1.0 and 0.0 respectively. The phase should be specified
in degrees.
It should be carefully noted that the number f2overf1 should ideally be an irrational number,
and that since this is not possible in practice, efforts should be made to keep the denominator
in its fractional representation as large as possible, certainly above 3, for accurate results (i.e.,
if f2overf1 is represented as a fraction A/B, where A and B are integers with no common
factors, B should be as large as possible; note that A < B because f2overf1 is constrained
to be < 1). To illustrate why, consider the cases where f2overf1 is 49/100 and 1/2. In a
spectral analysis, the outputs produced are at F1 + F2 , F1 F2 and 2F1 F2 . In the latter case,
F1 F2 = F2 , so the result at the F1 F2 component is erroneous because there is the strong
fundamental F2 component at the same frequency. Also, F1 + F2 = 2F1 F2 in the latter case,
and each result is erroneous individually. This problem is not there in the case where f2overf1
= 49/100, because F1 F2 = 51/100 F1 <> 49/100 F1 = F2 . In this case, there are two very
closely spaced frequency components at F2 and F1 F2 . One of the advantages of the Volterra
series technique is that it computes distortions at mix frequencies expressed symbolically (i.e.
nF1 + mF2 ), therefore one is able to obtain the strengths of distortion components accurately
even if the separation between them is very small, as opposed to transient analysis for example.
The disadvantage is of course that if two of the mix frequencies coincide, the results are not
merged together and presented (though this could presumably be done as a postprocessing step).
Currently, the interested user should keep track of the mix frequencies himself or herself and
add the distortions at coinciding mix frequencies together should it be necessary.
Only a subset of the ngspice nonlinear device models supports distortion analysis. These are

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CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)


Diodes (DIO),
BJT,
JFET (level 1),
MOSFETs (levels 1, 2, 3, 9, and BSIM1),
MESFET (level 1).

15.3.4

.NOISE: Noise Analysis

General form:
. n o i s e v ( o u t p u t < , r e f >) s r c ( dec | l i n | o c t ) p t s f s t a r t f s t o p
+ <pts_per_summary >
Examples:
. n o i s e v ( 5 ) VIN d e c 10 1kHZ 100Mhz
. n o i s e v ( 5 , 3 ) V1 o c t 8 1 . 0 1 . 0 e6 1
The .noise line does a noise analysis of the circuit. output is the node at which the total
output noise is desired; if ref is specified, then the noise voltage v(output) - v(ref) is
calculated. By default, ref is assumed to be ground. src is the name of an independent source
to which input noise is referred. pts, fstart and fstop are .ac type parameters that specify
the frequency range over which plots are desired. pts_per_summary is an optional integer; if
specified, the noise contributions of each noise generator is produced every pts_per_summary
frequency points. The .noise control line produces two plots:
1. one for the Noise Spectral Density curves and
2. one for the total Integrated Noise over the specified frequency range.
All noise voltages/currents are in squared units (V 2/Hz and A2/Hz for spectral density, V 2 and A2
for integrated noise).

15.3.5

.OP: Operating Point Analysis

General form:
. op
The inclusion of this line in an input file directs ngspice to determine the dc operating point of
the circuit with inductors shorted and capacitors opened.
Note: a DC analysis is automatically performed prior to a transient analysis to determine the
transient initial conditions, and prior to an AC small-signal, Noise, and Pole-Zero analysis to
determine the linearized, small-signal models for nonlinear devices (see the KEEPOPINFO
variable 15.1.2).

15.3. ANALYSES

15.3.6

237

.PZ: Pole-Zero Analysis

General form:
. pz
. pz
. pz
. pz
. pz
. pz

node1
node1
node1
node1
node1
node1

node2
node2
node2
node2
node2
node2

node3
node3
node3
node3
NODE3
node3

node4
node4
node4
node4
node4
node4

cur
cur
cur
vol
vol
vol

pol
zer
pz
pol
zer
pz

Examples:
. pz 1 0 3 0 c u r p o l
. pz 2 3 5 0 v o l z e r
. pz 4 1 4 1 c u r pz
cur stands for a transfer function of the type (output voltage)/(input current) while vol stands
for a transfer function of the type (output voltage)/(input voltage). pol stands for pole analysis
only, zer for zero analysis only and pz for both. This feature is provided mainly because
if there is a nonconvergence in finding poles or zeros, then, at least the other can be found.
Finally, node1 and node2 are the two input nodes and node3 and node4 are the two output
nodes. Thus, there is complete freedom regarding the output and input ports and the type of
transfer function.
In interactive mode, the command syntax is the same except that the first field is pz instead of
.pz. To print the results, one should use the command print all.

15.3.7

.SENS: DC or Small-Signal AC Sensitivity Analysis

General form:
. SENS
. SENS
. SENS
. SENS

OUTVAR
OUTVAR AC DEC ND FSTART FSTOP
OUTVAR AC OCT NO FSTART FSTOP
OUTVAR AC LIN NP FSTART FSTOP

Examples:
. SENS V( 1 ,OUT)
. SENS V(OUT) AC DEC 10 100 100 k
. SENS I ( VTEST )
The sensitivity of OUTVAR to all non-zero device parameters is calculated when the SENS
analysis is specified. OUTVAR is a circuit variable (node voltage or voltage-source branch
current). The first form calculates sensitivity of the DC operating-point value of OUTVAR.
The second form calculates sensitivity of the AC values of OUTVAR. The parameters listed for
AC sensitivity are the same as in an AC analysis (see ".AC" above). The output values are in
dimensions of change in output per unit change of input (as opposed to percent change in output
or per percent change of input).

238

15.3.8

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

.TF: Transfer Function Analysis

General form:
. t f outvar insrc
Examples:
. t f v ( 5 , 3 ) VIN
. t f i (VLOAD) VIN
The .tf line defines the small-signal output and input for the dc small-signal analysis. outvar
is the small signal output variable and insrc is the small-signal input source. If this line is
included, ngspice computes the dc small-signal value of the transfer function (output/input),
input resistance, and output resistance. For the first example, ngspice would compute the ratio
of V(5, 3) to VIN, the small-signal input resistance at VIN, and the small signal output resistance
measured across nodes 5 and 3.

15.3.9

.TRAN: Transient Analysis

General form:
. t r a n t s t e p t s t o p < t s t a r t <tmax >> < u i c >
Examples:
. t r a n 1 n s 100 n s
. t r a n 1 n s 1000 n s 500 n s
. t r a n 10 n s 1 u s
tstep is the printing or plotting increment for line-printer output. For use with the postprocessor, tstep is the suggested computing increment. tstop is the final time, and tstart
is the initial time. If tstart is omitted, it is assumed to be zero. The transient analysis always
begins at time zero. In the interval <zero, tstart>, the circuit is analyzed (to reach a steady
state), but no outputs are stored. In the interval <tstart, tstop>, the circuit is analyzed and
outputs are stored. tmax is the maximum stepsize that ngspice uses; for default, the program
chooses either tstep or (tstop-tstart)/50.0, whichever is smaller. tmax is useful when one
wishes to guarantee a computing interval which is smaller than the printer increment, tstep.
An initial transient operating point at time zero is calculated according to the following procedure: all independent voltages and currents are applied with their time zero values, all capacitances are opened, inductances are shorted, the non linear device equations are solved iteratively.
uic (use initial conditions) is an optional keyword which indicates that the user does not want
ngspice to solve for the quiescent operating point before beginning the transient analysis. If this
keyword is specified, ngspice uses the values specified using IC=... on the various elements as
the initial transient condition and proceeds with the analysis. If the .ic control line has been
specified (see 15.2.2), then the node voltages on the .ic line are used to compute the initial
conditions for the devices. IC=... will take precedence over the values given in the .ic control
line. If neither IC=... nor the .ic control line is given for a specific node, node voltage zero is
assumed.
Look at the description on the .ic control line (15.2.2) for its interpretation when uic is not
specified.

15.3. ANALYSES

15.3.10

239

Transient noise analysis (at low frequency)

In contrast to the analysis types described above the transient noise simulation (noise current or
voltage versus time) is not implemented as a dot command, but is integrated with the independent voltage source vsrc (isrc still not yet available) (see 4.1.7) and used in combination with
the .tran transient analysis (15.3.9).

Transient noise analysis deals with noise currents or voltages added to your circuits as a time
dependent signal of randomly generated voltage excursion on top of a fixed dc voltage. The
sequence of voltage values has random amplitude, but equidistant time intervals, selectable by
the user (parameter NT). The resulting voltage waveform is differentiable and thus does not
require any modifications of the matrix solving algorithms.

White noise is generated by the ngspice random number generator, applying the Box-Muller
transform. Values are generated on the fly, each time when a breakpoint is hit.

The 1/f noise is generated with an algorithm provided by N. J. Kasdin (Discrete simulation of
colored noise and stochastic processes and 1/ f a power law noise generation, Proceedings of
the IEEE, Volume 83, Issue 5, May 1995 Page(s):802 827). The noise sequence (one for each
voltage/current source with 1/f selected) is generated upon start up of the simulator and stored
for later use. The number of point is determined by the total simulation time divided by NT,
rounded up the the nearest power of 2. Each time a breakpoint (n ? NT , relevant to the noise
signal) is hit, the next value is retrieved from the sequence.

If you want a random, but reproducible sequence, you may select a seed value for the random
number generator by adding

set rndseed=nn

to the spinit or .spiceinit file, nn being a positive integer number.

The transient noise analysis will allow the simulation of the three most important noise sources.
Thermal noise is described by the Gaussian white noise. Flicker noise (pink noise or 1 over
f noise) with an exponent between 0 and 2 is provided as well. Shot noise is dependent on
the current flowing through a device and may be simulated by applying a non-linear source as
demonstrated in the following example:

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CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

Example:
* Shot n o i s e t e s t with B source , diode
* v o l t a g e on d e v i c e ( d i o d e , f o r w a r d )
Vdev o u t 0 DC 0 PULSE ( 0 . 4 0 . 4 5 10 u )
* d i o d e , f o r w a r d d i r e c t i o n , t o be modeled w i t h n o i s e
D1 mess 0 DMOD
. model DMOD D I S =1e 14 N=1
X1 0 mess o u t i s h o t
* d e v i c e b e t w e e n 1 and 2
* new o u t p u t t e r m i n a l s o f d e v i c e i n c l u d i n g n o i s e : 1 and 3
. subckt ishot 1 2 3
* w h i t e n o i s e s o u r c e w i t h rms 1V
* 20000 s a m p l e p o i n t s
VNG 0 11 DC 0 TRNOISE ( 1 1n 0 0 )
* m e a s u r e t h e c u r r e n t i ( v1 )
V1 2 3 DC 0
* calculate the shot noise
* s q r t (2* c u r r e n t *q* bandwidth )
BI 1 3 I = s q r t ( 2 * a b s ( i ( v1 ) ) * 1 . 6 e 19 * 1 e7 ) * v ( 1 1 )
. ends i s h o t
. t r a n 1 n 20 u
. control
run
p l o t ( 1) * i ( vdev )
. endc
. end
The selection of the delta time step (NT) is worth discussing. Gaussian white noise has unlimited bandwidth and thus unlimited energy content. This is unrealistic. The bandwidth of real
noise is limited, but it is still called "White" if it is the same level throughout the frequency
range of interest, e.g. the bandwidth of your system. Thus you may select NT to be a factor of
10 smaller than the frequency limit of your circuit. A thorough analysis is still needed to clarify the appropriate factor! The transient method is probably most suited for circuits including
switches, which are not amenable to the small signal .NOISE analysis (chapter 15.3.4).
This is the price you have to pay for transient noise analysis: the number of required time steps
for simulation will increase, and thus the simulation time. But modern computers deliver a lot
of speed, and it may be well worth of trying and experimenting.
In addition to white and 1/f noise the independent voltage and current sources offer a random
telegraph signal (RTS) noise source, also known as burst noise or popcorn noise, again for
transient analysis. For each voltage (current) source offering RTS noise an individual noise
amplitude is required for input, as well as a mean capture time and a mean emission time.
The amplitude resembles the influence of a single trap on the current or voltage. The capture
and emission times emulate the filling and emptying of the trap, typically following a Poisson
process. They are generated from an random exponential distribution with their respective mean
values given by the user. To simulate an ensemble of traps, you may combine several current or
voltage sources with different parameters.

15.3. ANALYSES

241

All three sources (white, 1/f, and RTS) may be combined in a single command line.
RTS noise example:
* w h i t e n o i s e , 1 / f n o i s e , RTS n o i s e
* voltage source
VRTS2 13 12 DC 0 t r n o i s e ( 0 0 0 0 5m 18 u 30 u )
VRTS3 11 0 DC 0 t r n o i s e ( 0 0 0 0 10m 20 u 40 u )
VALL 12 11 DC 0 t r n o i s e ( 1m 1u 1 . 0 0 . 1m 15m 22 u 50 u )
VW1of 21 0 DC

t r n o i s e ( 1m 1u 1 . 0 0 . 1m)

* current source
IRTS2 10 0 DC 0 t r n o i s e ( 0 0 0 0 5m 18 u 30 u )
IRTS3 10 0 DC 0 t r n o i s e ( 0 0 0 0 10m 20 u 40 u )
IALL 10 0 DC 0 t r n o i s e ( 1m 1u 1 . 0 0 . 1m 15m 22 u 50 u )
R10 10 0 1
IW1of 9 0 DC
Rall 9 0 1

t r n o i s e ( 1m 1u 1 . 0 0 . 1m)

* sample p o i n t s
. t r a n 1 u 500 u
. control
run
plot v (13) v (21)
plot v (10) v (9)
. endc
. end
Some details on RTS noise modeling are available in a recent article [20], available here.
Anyhow this transient noise feature is still experimental!
The following questions (among others) are to be solved:
clarify the theoretical background
noise limit of plain ngspice (numerical solver, fft etc.)
time step (NT) selection
calibration of noise spectral density
how to generate noise from a transistor model
application benefits and limits

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CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

15.3.11

.PSS: Periodic Steady State Analysis

(Experimental code, not yet made publicly available!)


General form:
. p s s g f r e q t s t a b o s c n o b p s s p o i n t s harms s c i t e r s t e a d y c o e f f < u i c >
Examples:
. p s s 150 200 e3 2 1024 11 50 5 e3 u i c
. p s s 624 e6 1u v _ p l u s 1024 10 150 5 e3 u i c
. p s s 624 e6 500 n b o u t 1024 10 100 5 e3 u i c
gfreq is guessed frequency of fundamental suggested by user. When performing transient
analysis the PSS algorithm tries to infer a new rough guess rgfreq on the fundamental. If
gfreq is out of 10% with respect to rgfreq then gfreq is discarded.
tstab is stabilization time before the shooting begin to search for the PSS. It has to be noticed
that this parameter heavily influence the possibility to reach the PSS. Thus is a good practice to
ensure a circuit to have a right tstab, e.g. performing a separate TRAN analysis before to run
PSS analysis.
oscnob is the node or branch where the oscillation dynamic is expected. PSS analysis will give
a brief report of harmonic content at this node or branch.
psspoints is number of step in evaluating predicted period after convergence is reached. It
is useful only in Time Domain plots. However this number should be higher than 2 times the
requested harms. Otherwise the PSS analysis will properly adjust it.
harms number of harmonics to be calculated as requested by the user.
sciter number of allowed shooting cycle iterations. Default is 50.
steady_coeff is the weighting coefficient for calculating the Global Convergence Error (GCE)
which is the reference value in order to infer is convergence is reached. The lower steady_coeff
is set, the higher the accuracy of predicted frequency can be reached but at longer analysis time
and sciter number. Default is 1e-3.
uic (use initial conditions) is an optional keyword which indicates that the user does not want
ngspice to solve for the quiescent operating point before beginning the transient analysis. If this
keyword is specified, ngspice uses the values specified using IC=... on the various elements as
the initial transient condition and proceeds with the analysis. If the .ic control line has been
specified, then the node voltages on the .ic line are used to compute the initial conditions for
the devices. Look at the description on the .ic control line for its interpretation when uic is
not specified.

15.4

Measurements after Op, Ac, and Transient Analysis

15.4.1

.meas(ure)

The .meas or .measure statement (and its equivalent meas command, see chapt. 17.5.37) are
used to analyze the output data of a tran, ac, or dc simulation. The command is executed
immediately after the simulation has finished.

15.4. MEASUREMENTS AFTER OP, AC, AND TRANSIENT ANALYSIS

15.4.2

243

batch versus interactive mode

.meas analysis may not be used in batch mode (-b command line option), if an output file
(rawfile) is given at the same time (-r rawfile command line option). In this batch mode
ngspice will write its simulation output data directly to the output file. The data is not kept in
memory, thus is no longer available for further analysis. This is made to allow a very large
output stream with only a relatively small memory usage. For .meas to be active you need to
run the batch mode with a .plot or .print command. A better alternative may be to start
ngspice in interactive mode.
If you need batch like operation, you may add a .control ...
file:

.endc section to the input

Example:
* input f i l e
...
. t r a n 1 n s 1000 n s
...
*********************************
. control
run
write o u t p u t f i l e data
. endc
*********************************
. end
and start ngspice in interactive mode, e.g. by running the command
ngspice inputfile .
.meas<ure> then prints its user-defined data analysis to the standard output. The analysis includes propagation, delay, rise time, fall time, peak-to-peak voltage, minimum or maximum
voltage, the integral or derivative over a specified period and several other user defined values.

15.4.3

General remarks

The measure type {DC|AC|TRAN|SP} depends on the data which are to be evaluated, either
originating from a dc analysis, an ac analysis, a transient simulation. SP to analyze a spectrum
from the spec or fft commands is only available when executed in a meas command, see
17.5.37.
result will be a vector containing the result of the measurement. trig_variable, targ_variable,
and out_variable are vectors stemming from the simulation, e.g. a voltage vector v(out).
VAL=val expects a real number val. It may be as well a parameter in or {} expanding to a
real number.
TD=td and AT=time expect a time value if measure type is tran. For ac and sp AT will be a
frequency value, TD is ignored. For dc analysis AT is a voltage (or current), TD is ignored as
well.
CROSS=# requires an integer number #. CROSS=LAST is possible as well. The same is
expected by RISE and FALL.

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CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

Frequency and time values may start at 0 and extend to positive real numbers. Voltage (or
current) inputs for the independent (scale) axis in a dc analysis may start or end at arbitrary real
valued numbers.
*
************
Be careful because not all of the .measure commands have been implemented so far!
deriv and error is missing
************
*

15.4.4

Input

In the following lines you will get some explanation on the .measure commands. A simple
simulation file with two sines of different frequencies may serve as an example. The transient
simulation delivers time as the independent variable and two voltages as output (dependent
variables).
Input file:
F i l e : s i m p l e meast r a n . s p
* Simple . measurement examples
* t r a n s i e n t s i m u l a t i o n o f two s i n e s i g n a l s w i t h d i f f e r e n t
frequencies
v a c 1 1 0 DC 0 s i n ( 0 1 1k 0 0 )
v a c 2 2 0 DC 0 s i n ( 0 1 . 2 0 . 9 k 0 0 )
. t r a n 10 u 5m
*
. m e a s u r e t r a n . . . $ f o r t h e d i f f e r e n t i n p u t s s e e below !
*
. control
run
plot v (1) v (2)
. endc
. end
After displaying the general syntax of the .measurement statement, some examples are posted,
referring to the input file given above.

15.4.5

Trig Targ

.measure according to general form 1 measures the difference in dc voltage, frequency or time
between two points selected from one or two output vectors. The current examples all are using
transient simulation. Measurements for tran analysis start after a delay time td. If you run other
examples with ac simulation or spectrum analysis, time may be replaced by frequency, after a
dc simulation the independent variable may become a voltage or current.

15.4. MEASUREMENTS AFTER OP, AC, AND TRANSIENT ANALYSIS

245

General form 1:
. MEASURE {DC | AC | TRAN | SP} r e s u l t TRIG t r i g _ v a r i a b l e VAL= v a l <TD=
t d > <CROSS=# | CROSS=LAST> <RISE=# | RISE=LAST> <FALL=# |
FALL=LAST> <TRIG AT= t i m e > TARG t a r g _ v a r i a b l e VAL= v a l <TD= t d >
<CROSS=# | CROSS=LAST> <RISE=# | RISE=LAST> <FALL=# | FALL=
LAST> <TARG AT= t i m e >
Measure statement example (for use in the input file given above):
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2
measures the time difference between v(1) reaching 0.5 V for the first time on its first rising
slope (TRIG) versus reaching 0.5 V again on its second rising slope (TARG). I.e. it measures
the signal period.
Output:
tdiff = 1.000000e-003 targ= 1.083343e-003 trig= 8.334295e-005
Measure statement example:
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3
measures the time difference between v(1) reaching 0.5 V for the first time on its rising slope
versus reaching 0.5 V on its rising slope for the third time (i.e. two periods).
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1
measures the time difference between v(1) reaching 0.5V for the first time on its rising slope
versus reaching 0.5 V on its first falling slope.
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3
measures the time difference between v(1) reaching 0V its third falling slope versus v(2) reaching 0 V on its third falling slope.
Measure statement:
.measure tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1
measures the time difference between v(1) crossing -0.6 V for the first time (any slope) versus
v(2) crossing -0.8 V for the first time (any slope).
Measure statement:
.measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3
measures the time difference between the time point 1ms versus the time when v(2) crosses -0.8
V for the third time (any slope).

15.4.6

Find ... When

The FIND and WHEN functions allow to measure any dependent or independent time, frequency, or dc parameter, when two signals cross each other or a signal crosses a given value.
Measurements start after a delay TD and may be restricted to a range between FROM and TO.

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CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

General form 2:
. MEASURE {DC | AC | TRAN | SP} r e s u l t WHEN o u t _ v a r i a b l e = v a l <TD= t d > <
FROM= v a l > <TO= v a l > <CROSS=# | CROSS=LAST> <RISE=# | RISE=
LAST> <FALL=# | FALL=LAST>
Measure statement:
.measure tran teval WHEN v(2)=0.7 CROSS=LAST
measures the time point when v(2) crosses 0.7 V for the last time (any slope).
General form 3:
. MEASURE {DC | AC | TRAN | SP} r e s u l t WHEN o u t _ v a r i a b l e = o u t _ v a r i a b l e 2
<TD= t d > <FROM= v a l > <TO= v a l > <CROSS=# | CROSS=LAST> <RISE=#
| RISE=LAST> <FALL=# | FALL=LAST>
Measure statement:
.measure tran teval WHEN v(2)=v(1) RISE=LAST
measures the time point when v(2) and v(1) are equal, v(2) rising for the last time.
General form 4:
. MEASURE {DC | AC | TRAN | SP} r e s u l t FIND o u t _ v a r i a b l e WHEN
o u t _ v a r i a b l e 2 = v a l <TD= t d > <FROM= v a l > <TO= v a l > <CROSS=# |
CROSS=LAST> <RISE=# | RISE=LAST> <FALL=# | FALL=LAST>
Measure statement:
.measure tran yeval FIND v(2) WHEN v(1)=-0.4 FALL=LAST
returns the dependent (y) variable drawn from v(2) at the time point when v(1) equals a value
of -0.4, v(1) falling for the last time.
General form 5:
. MEASURE {DC | AC | TRAN | SP} r e s u l t FIND o u t _ v a r i a b l e WHEN
o u t _ v a r i a b l e 2 = o u t _ v a r i a b l e 3 <TD= t d > <CROSS=# | CROSS=LAST>
<RISE = # | RISE=LAST> <FALL = # | FALL=LAST>
Measure statement:
.measure tran yeval FIND v(2) WHEN v(1)=v(3) FALL=2
returns the dependent (y) variable drawn from v(2) at the time point when v(1) crosses v(3),
v(1) falling for the second time.
General form 6:
. MEASURE {DC | AC | TRAN | SP} r e s u l t FIND o u t _ v a r i a b l e AT= v a l
Measure statement:
.measure tran yeval FIND v(2) AT=2m
returns the dependent (y) variable drawn from v(2) at the time point 2 ms (given by AT=time).

15.4. MEASUREMENTS AFTER OP, AC, AND TRANSIENT ANALYSIS

15.4.7

247

AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT

General form 7:
. MEASURE {DC | AC | TRAN | SP} r e s u l t {AVG | MIN |MAX| PP | RMS | MIN_AT |
MAX_AT} o u t _ v a r i a b l e <TD= t d > <FROM= v a l > <TO= v a l >
Measure statements:
.measure tran ymax MAX v(2) from=2m to=3m
returns the maximum value of v(2) inside the time interval between 2 ms and 3 ms.
.measure tran tymax MAX_AT v(2) from=2m to=3m
returns the time point of the maximum value of v(2) inside the time interval between 2 ms and
3 ms.
.measure tran ypp PP v(1) from=2m to=4m
returns the peak to peak value of v(1) inside the time interval between 2 ms and 4 ms.
.measure tran yrms RMS v(1) from=2m to=4m
returns the root mean square value of v(1) inside the time interval between 2 ms and 4 ms.
.measure tran yavg AVG v(1) from=2m to=4m
returns the average value of v(1) inside the time interval between 2 ms and 4 ms.

15.4.8

Integ

General form 8:
. MEASURE {DC | AC | TRAN | SP} r e s u l t INTEG<RAL> o u t _ v a r i a b l e <TD= t d >
<FROM= v a l > <TO= v a l >
Measure statement:
.measure tran yint INTEG v(2) from=2m to=3m
returns the area under v(2) inside the time interval between 2 ms and 3 ms.

15.4.9

param

General form 9:
. MEASURE {DC | AC | TRAN | SP} r e s u l t

param = e x p r e s s i o n

Measure statement:
.param fval=5
.measure tran yadd param=fval + 7
will evaluate the given expression fval + 7 and return the value 12.
Expression is evaluated according to the rules given in chapt. 2.8.5 during start up of ngspice.
It may contain parameters defined with the .param statement. It may also contain parameters
resulting from preceding .meas statements.

248

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

.param vout_diff=50u
...
.measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3
.meas tran bw_chk param=(tdiff < vout_diff) ?

1 :

will evaluate the given ternary function and return the value 1 in bw_chk, if tdiff measured is
smaller than parameter vout_diff.
The expression may not contain vectors like v(10), e.g. anything resulting directly from a
simulation. This may be handled with the following .meas command option.

15.4.10

par(expression)

The par(expression) option (15.5.6) allows to use algebraic expressions in the .measure
lines. Every out_variable may be replaced by par(expression) within the general forms 1-9
described above. Internally par(expression) will be substituted by a vector according to the
rules of the B source (chapt. 5.1). A typical example of the general form is shown below:
General form 10:
. MEASURE {DC | AC | TRAN | SP} r e s u l t

FIND p a r ( e x p r e s s i o n ) AT= v a l

Measure statement:
.measure tran vtest find par((v(2)*v(1))) AT=2.3m
will return the product of the two voltages at time point 2.3 ms.

15.4.11

Deriv

General form:
. MEASURE {DC | AC | TRAN | SP} r e s u l t DERIV<ATIVE> o u t _ v a r i a b l e AT=
val
. MEASURE {DC | AC | TRAN | SP} r e s u l t DERIV<ATIVE> o u t _ v a r i a b l e WHEN
out_variable2=val
+ <TD= t d >
+ <CROSS=# | CROSS=LAST> <RISE = # | RISE=LAST> <FALL = # | FALL=LAST>
. MEASURE {DC | AC | TRAN | SP} r e s u l t DERIV<ATIVE> o u t _ v a r i a b l e
+ WHEN o u t _ v a r i a b l e 2 = o u t _ v a r i a b l e 3
+ <TD= t d >
+ <CROSS=# | CROSS=LAST> <RISE = # | RISE=LAST> <FALL = # | FALL=LAST>
.MEASURE {DC|AC|TRAN|SP} result DERIV<ATIVE> ... is not yet available.

15.4.12

More examples

Some other examples, also showing the use of parameters, are given below. Corresponding
demonstration input files are distributed with ngspice in folder /examples/measure.

15.5. BATCH OUTPUT

249

Other examples:
. meas t r a n i n v _ d e l a y 2 t r i g v ( i n ) v a l = vp / 2 t d =1n f a l l =1 t a r g v
( out )
+ v a l = vp / 2 r i s e =1
. meas t r a n t e s t _ d a t a 1 t r i g AT = 1n t a r g v ( o u t ) v a l = vp / 2 r i s e
=3
. meas t r a n o u t _ s l e w t r i g v ( o u t ) v a l = 0 . 2 * vp r i s e =2 t a r g v ( o u t )
+ v a l = 0 . 8 * vp r i s e =2
. meas t r a n d e l a y _ c h k param = ( i n v _ d e l a y < 100 p s ) ? 1 : 0
. meas t r a n skew when v ( o u t ) = 0 . 6
. meas t r a n skew2 when v ( o u t ) =skew_meas
. meas t r a n skew3 when v ( o u t ) =skew_meas f a l l =2
. meas t r a n skew4 when v ( o u t ) =skew_meas f a l l =LAST
. meas t r a n skew5 FIND v ( o u t ) AT=2n
. meas t r a n v0_min min i ( v0 ) from = d f a l l t o = d f a l l + p e r i o d
. meas t r a n v0_avg avg i ( v0 ) from = d f a l l t o = d f a l l + p e r i o d
. meas t r a n v 0 _ i n t e g i n t e g i ( v0 ) from = d f a l l t o = d f a l l + p e r i o d
. meas t r a n v0_rms rms i ( v0 ) from = d f a l l t o = d f a l l + p e r i o d
. meas dc i s _ a t FIND i ( v s ) AT=1
. meas dc i s _ m a x max i ( v s ) from =0 t o = 3 . 5
. meas dc v d s _ a t when i ( v s ) = 0 . 0 1
. meas a c v o u t _ a t FIND v ( o u t ) AT=1MEG
. meas a c v o u t _ a t d FIND vdb ( o u t ) AT=1MEG
. meas a c vout_max max v ( o u t ) from =1k t o =10MEG
. meas a c f r e q _ a t when v ( o u t ) = 0 . 1
. meas a c v o u t _ d i f f t r i g v ( o u t ) v a l = 0 . 1 r i s e =1 t a r g v ( o u t ) v a l
= 0 . 1 f a l l =1
. meas a c f i x e d _ d i f f t r i g AT = 10 k t a r g v ( o u t ) v a l = 0 . 1 r i s e =1
. meas a c v o u t _ a v g avg
v ( o u t ) from =10 k t o =1MEG
. meas a c v o u t _ i n t e g i n t e g v ( o u t ) from =20 k t o =500 k
. meas a c f r e q _ a t 2 when v ( o u t ) = 0 . 1 f a l l =LAST
. meas a c bw_chk param = ( v o u t _ d i f f < 100 k ) ? 1 : 0
. meas a c v o u t _ r m s rms v ( o u t ) from =10 t o =1G

15.5

Batch Output

15.5.1

.SAVE: Name vector(s) to be saved in raw file

General form:
. save vector vector vector

...

Examples:
. s a v e i ( v i n ) node1 v ( node2 )
. s a v e @m1[ i d ] v s o u r c e # b r a n c h
. s a v e a l l @m2[ v d s a t ]

250

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

The vectors listed on the .SAVE line are recorded in the rawfile for use later with ngspice or
ngnutmeg (ngnutmeg is just the data-analysis half of ngspice, without the ability to simulate).
The standard vector names are accepted. Node voltages may be saved by giving the nodename
or v(nodename). Currents through an independent voltage source are given by i(sourcename)
or sourcename#branch. Internal device data are accepted as @dev[param].
If no .SAVE line is given, then the default set of vectors is saved (node voltages and voltage
source branch currents). If .SAVE lines are given, only those vectors specified are saved. For
more discussion on internal device data, e.g. @m1[id], see Appendix, chapt. 31.1. If you want
to save internal data in addition to the default vector set, add the parameter all to the additional
vectors to be saved. If the command .save vm(out) is given, and you store the data in a
rawfile, only the original data v(out) are stored. The request for storing the magnitude is ignored,
because this may be added later during rawfile data evaluation with ngnutmeg or ngspice. See
also the section on the interactive command interpreter (chapter 17.5) for information on how
to use the rawfile.

15.5.2

.PRINT Lines

General form:
. p r i n t p r t y p e ov1 <ov2 . . . ov8 >
Examples:
. p r i n t tran v (4) i ( vin )
. p r i n t dc v ( 2 ) i ( v s r c ) v ( 2 3 , 1 7 )
. p r i n t a c vm ( 4 , 2 ) v r ( 7 ) vp ( 8 , 3 )
The .print line defines the contents of a tabular listing of one to eight output variables. prtype
is the type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs
are desired. The form for voltage or current output variables is the same as given in the previous section for the print command; Spice2 restricts the output variable to the following forms
(though this restriction is not enforced by ngspice):
V(N1<,N2>)

I(VXXXXXXX)

specifies the voltage difference between nodes N1 and N2.


If N2 (and the preceding comma) is omitted, ground (0) is
assumed. See the print command in the previous section
for more details. For compatibility with SPICE2, the
following five additional values can be accessed for the ac
analysis by replacing the "V" in V(N1,N2) with:
VR
Real part
VI
Imaginary part
VM
Magnitude
VP
Phase
VDB 20log10(magnitude)
specifies the current flowing in the independent voltage
source named VXXXXXXX. Positive current flows from
the positive node, through the source, to the negative node.
(Not yet implemented: For the ac analysis, the
corresponding replacements for the letter I may be made in
the same way as described for voltage outputs.)

15.5. BATCH OUTPUT

251

Output variables for the noise and distortion analyses have a different general form from that of
the other analyses. There is no limit on the number of .print lines for each type of analysis.
The par(expression) option (15.5.6) allows to use algebraic expressions in the .print
lines. .width (15.5.7) selects the maximum number of characters per line.

15.5.3

.PLOT Lines

General form:
. p l o t p l t y p e ov1 <( p l o 1 , p h i 1 ) > <ov2 <( p l o 2 , p h i 2 ) > . . . ov8 >
Examples:
.
.
.
.
.

plot
plot
plot
plot
plot

dc v ( 4 ) v ( 5 ) v ( 1 )
t r a n v (17 , 5) (2 , 5) i ( vin ) v (17) (1 , 9)
a c vm ( 5 ) vm ( 3 1 , 2 4 ) vdb ( 5 ) vp ( 5 )
d i s t o hd2 hd3 (R) sim2
t r a n v (5 , 3) v ( 4 ) (0 , 5) v ( 7 ) (0 , 10)

The .plot line defines the contents of one plot of from one to eight output variables. pltype
is the type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are
desired. The syntax for the ovi is identical to that for the .print line and for the plot command
in the interactive mode.
The overlap of two or more traces on any plot is indicated by the letter X. When more than
one output variable appears on the same plot, the first variable specified is printed as well
as plotted. If a printout of all variables is desired, then a companion .print line should be
included. There is no limit on the number of .plot lines specified for each type of analysis.
The par(expression) option (15.5.6) allows to use algebraic expressions in the .plot
lines.

15.5.4

.FOUR: Fourier Analysis of Transient Analysis Output

General form:
. f o u r f r e q ov1 <ov2 ov3 . . . >
Examples:
. f o u r 100K v ( 5 )
The .four (or Fourier) line controls whether ngspice performs a Fourier analysis as a part of
the transient analysis. freq is the fundamental frequency, and ov1 is the desired vector to be
analyzed. The Fourier analysis is performed over the interval <TSTOP-period, TSTOP>, where
TSTOP is the final time specified for the transient analysis, and period is one period of the
fundamental frequency. The dc component and the first nine harmonics are determined. For
maximum accuracy, TMAX (see the .tran line) should be set to period/100.0 (or less for very
high-Q circuits). The par(expression) option (15.5.6) allows to use algebraic expressions
in the .four lines.

252

15.5.5

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

.PROBE: Name vector(s) to be saved in raw file

General form:
. probe v e c t o r < v e c t o r v e c t o r . . . >
Examples:
. probe i ( vin ) i n p u t output
. p r o b e @m1[ i d ]
Same as .SAVE (see chapt. 15.5.1).

15.5.6

par(expression): Algebraic expressions for output

General form:
par ( expression )
output=par ( expression )

$ not in . measure

Examples:
. f o u r 1001 s q 1 = p a r ( v ( 1 ) * v ( 1 ) )
. m e a s u r e t r a n v t e s t f i n d p a r ( ( v ( 2 ) * v ( 1 ) ) ) AT= 2 . 3m
. p r i n t tran output=par ( v ( 1 ) / v (2) ) v (1) v (2)
. p l o t dc v ( 1 ) d i f f = p a r ( ( v (4) v ( 2 ) ) / 0 . 0 1 ) o u t 2 2 2
In the output lines .four, .plot, .print, .save and in the .measure evaluation it is possible to add algebraic expression for output, in addition to vectors. All of these output lines
accept par(expression), where expression is any expression as has already been defined
for the B source (see chapter 5.1). Thus expression may contain predefined functions, numerical values, constants, simulator output like v(n1) or i(vdb), parameters predefined by a .param
statement, and the variables hertz, temper, and time.
Internally expression is replaced by an internally generated voltage node, which is the output
of a B source, one node and B source per par(...). Several par(...) are allowed in each line,
up to 99 per input file. The internal nodes are named pa_00 to pa_99. If your input file already
contains such node names, an error will occur, unless you rename these nodes.
In .four, .plot, .print, .save, but not in .measure, an alternative syntax
output=par(expression) is possible. par(expression) may be used as described
above. output is the name of the new node to replace the expression. So output has to be
unique and a valid node name.
The syntax of output=par(expression) is strict, no spaces between par and (, or between
( and are allowed, ( and ) both are required. Also there is not much error checking on your
input, if there is a typo, for example, an error may pop up at an unexpected place.

15.5.7

.width

Set the width of a print-out or plot with the following card:


.with out = 256

15.5. BATCH OUTPUT

253

Parameter out yields the maximum number of characters plotted in a row, if printing in columns
or an ASCII-plot is selected.

254

CHAPTER 15. ANALYSES AND OUTPUT CONTROL (BATCH MODE)

Chapter 16
Starting ngspice
16.1

Introduction

Ngspice consists of the simulator and a front-end for data analysis and plotting. Input to the
simulator is a netlist file, including commands for circuit analysis and output control. Interactive
ngspice can plot data from a simulation on a PC or a workstation display.
Ngspice on LINUX (and OSs like Cygwin, BCD, Solaris ...) uses the X Window System for
plotting (see chapter 18.3) if the environment variable DISPLAY is available. Otherwise, a console mode (non-graphical) interface is used. If you are using X on a workstation, the DISPLAY
variable should already be set; if you want to display graphics on a system different from the
one you are running ngspice or ngutmeg on, DISPLAY should be of the form "machine:0.0".
See the appropriate documentation on the X Window System for more details.
The MS Windows versions of ngspice and ngnutmeg will have a native graphics interface (see
chapter 18.1).
The front-end may be run as a separate "stand-alone" program under the name ngnutmeg. ngnutmeg is a subset of ngspice dedicated to data evaluation, still made available for historical reasons. Ngnutmeg will read in the "raw" data output file created by ngspice -r or by the write
command during an interactive ngspice session.

16.2

Where to obtain ngspice

The actual distribution of ngspice may be downloaded from the ngspice download web page.
The installation for LINUX or MS Windows is described in the file INSTALL to be found in
the top level directory. You may also have a look at chapter 32 of this manual for compiling
instructions.
If you want to check out the source code which is actually under development, you may have
a look at the ngspice source code repository, which is stored using the Git Source Code Management (SCM) tool. The Git repository may be browsed on the Git web page, also useful for
downloading individual files. You may however download (or clone) the complete repository including all source code trees from the console window (LINUX, CYGWIN or MSYS/MINGW)
by issuing the command (in a single line)

255

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CHAPTER 16. STARTING NGSPICE

git clone git://ngspice.git.sourceforge.net/gitroot/ngspice/ngspice

You need to have Git installed, which is available for all three OSs. The whole source tree
is then available in <current directory>/ngspice. Compilation and local installation is again
described in INSTALL (or chapter 32). If you later want to update your files and download the
recent changes from sourceforge into your local repository, cd into the ngspice directory and
just type

git pull

git pull will deny to overwrite modified files in your working directory. To drop your local
changes first, you can run

git reset --hard

To learn more about git, which can be both powerful and difficult to master, please consult
http://git-scm.com/, especially: http://git-scm.com/documentation which has pointers to documentation and tutorials.

16.3

Command line options for starting ngspice and ngnutmeg

Command Synopsis:
n g s p i c e [ o l o g f i l e ] [ r r a w f i l e ] [ b ] [ i ] [ i n p u t f i l e
ngnutmeg [ ] [ d a t a f i l e . . . ]

Options are:

... ]

16.3. COMMAND LINE OPTIONS FOR STARTING NGSPICE AND NGNUTMEG


Option
-

Long option

-n

no-spiceinit

-t TERM

terminal=TERM

-b

batch

-s

server

-i

interactive

-r FILE

rawfile=FILE

-p

pipe

-o FILE

output=FILE

-h
-v
-a

help
version
autorun

257

Meaning
Dont try to load the default data file ("rawspice.raw") if no
other files are given (ngnutmeg only).
Dont try to source the file ".spiceinit" upon start-up.
Normally ngspice and ngnutmeg try to find the file in the
current directory, and if it is not found then in the users
home directory (obsolete).
The program is being run on a terminal with mfb name
term (obsolete).
Run in batch mode. Ngspice reads the default input source
(e.g. keyboard) or reads the given input file and performs
the analyses specified; output is either Spice2-like
line-printer plots ("ascii plots") or a ngspice rawfile. See
the following section for details. Note that if the input
source is not a terminal (e.g. using the IO redirection
notation of "<") ngspice defaults to batch mode (-i
overrides). This option is valid for ngspice only.
Run in server mode. This is like batch mode, except that a
temporary rawfile is used and then written to the standard
output, preceded by a line with a single "@", after the
simulation is done. This mode is used by the ngspice
daemon. This option is valid for ngspice only.
Example for using pipes from the console window:
cat adder.cir|ngspice -s|more
Run in interactive mode. This is useful if the standard input
is not a terminal but interactive mode is desired. Command
completion is not available unless the standard input is a
terminal, however. This option is valid for ngspice only.
Use rawfile as the default file into which the results of the
simulation are saved. This option is valid for ngspice only.
Allow a program (e.g., xcircuit) to act as a GUI frontend
for ngspice through a pipe. Thus ngspice will assume that
the input pipe is a tty and allows to run in interactive mode.
All logs generated during a batch run (-b) will be saved in
outfile.
A short help statement of the command line syntax.
Prints a version information.
Start simulation immediately, as if a control section
.control
run
.endc
had been added to the input file.

Further arguments to ngspice are taken to be ngspice input files, which are read and saved (if
running in batch mode then they are run immediately). Ngspice accepts Spice3 (and also most
Spice2) input files, and outputs ASCII plots, Fourier analyses, and node printouts as specified
in .plot, .four, and .print cards. If an out parameter is given on a .width card (15.5.7),
the effect is the same as set width = .... Since ngspice ASCII plots do not use multiple ranges,
however, if vectors together on a .plot card have different ranges they do not provide as much

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CHAPTER 16. STARTING NGSPICE

information as they do in a scalable graphics plot.


For ngnutmeg, further arguments are taken to be data files in binary or ASCII raw file format
(generated with -r in batch mode or the write (see 17.5.86) command) which are loaded into
ngnutmeg. If the file is in binary format, it may be only partially completed (useful for examining output before the simulation is finished). One file may contain any number of data sets
from different analyses.

16.4

Starting options

16.4.1

Batch mode

Lets take as an example the Four-Bit binary adder MOS circuit shown in chapter 21.6, stored
in a file adder-mos.cir. You may start the simulation immediately by calling
ngspice -b -r adder.raw -o adder.log adder-mos.cir
ngspice will start, simulate according to the .tran command and store the output data in a rawfile
adder.raw. Comments, warnings and infos go to log file adder.log. Commands for batch mode
operation are described in chapt. 15.

16.4.2

Interactive mode

If you call
ngspice
ngspice will start, load spinit (16.5) and .spiceinit (16.6, if available), and then waits for your
manual input. Any of the commands described in 17.5 may be chosen, but many of them are
useful only after a circuit has been loaded by
ngspice 1 -> source adder-mos.cir
others require the simulation being done already (e.g. plot):
ngspice 2 ->run
ngspice 3 ->plot allv
If you call ngspice from the command line with a circuit file as parameter:
ngspice adder-mos.cir
ngspice will start, load the circuit file, parse the circuit (same circuit file as above, containing
only dot commands (see chapt. 15) for analysis and output control). ngspice then just waits for
your input. You may start the simulation by issuing the run command. Following completion
of the simulation you may analyze the data by any of the commands given in chapter 17.5.

16.4.3

Control mode (Interactive mode with control file or control section)

If you add the following control section to your input file adder-mos.cir, you may call

16.4. STARTING OPTIONS

259

ngspice adder-mos.cir
from the command line and see ngspice starting, simulating and then plotting immediately.
Control section:
* ADDER 4 BIT ALLNANDGATE BINARY ADDER
. control
set noaskquit
save vcc # branch
run
p l o t vcc # branch
rusage a l l
. endc
Any suitable command listed in chapter 17.5 may be added to the control section, as well as
control structures described in chapter 17.6. Batch-like behavior may be obtained by changing
the control section to
Control section with batch-like behavior:
* ADDER 4 BIT ALLNANDGATE BINARY ADDER
. control
set noaskquit
save vcc # branch
run
w r i t e a d d e r . raw v c c # b r a n c h
quit
. endc
If you put this control section into a file, say adder-start.sp, you may just add the line
.include adder-start.sp
to your input file adder-mos.cir to obtain the batch-like behavior. In the following example the
line .tran ... from the input file is overridden by the tran command given in the control
section.
Control section overriding the .tran command:
* ADDER 4 BIT ALLNANDGATE BINARY ADDER
. control
set noaskquit
save vcc # branch
t r a n 1 n 500 n
p l o t vcc # branch
rusage a l l
. endc
The commands within the .control section are executed in the order they are listed and only
after the circuit has been read in and parsed. If you want to have a command being executed
before circuit parsing, you may use the prefix pre_ (17.5.44) to the command.
A warning is due however: If your circuit file contains such a control section (.control ... .endc),
you should not start ngspice in batch mode (with -b as parameter). The outcome may be unpredictable!

260

16.5

CHAPTER 16. STARTING NGSPICE

Standard configuration file spinit

Upon start up ngspice reads its configuration file spinit. spinit may be found in
C:\Spice\share\ngspice\scripts (Windows) or /usr/local/share/ngspice/scripts (LINUX). The path
may be overridden by setting the environmental variable SPICE_LIB_DIR to a path where
/scripts will be added. ngspice for Windows will also search for spinit in the directory where
ngspice.exe resides. If spinit is not found, a warning message is issued, but ngspice will
continue (but of course without code models etc.).
Standard spinit contents:
* Standard ngspice i n i t
alias exit quit
a l i a s acct rusage a l l
set x11lineararcs
* s e t r n d s e e d =12
*set filetype=ascii
* s e t ngdebug

file

* unset brief
strcmp _ _ f l a g $program " n g s p i c e "
i f $__flag = 0
* F o r SPICE2 POLYs , e d i t t h e below l i n e t o p o i n t t o t h e l o c a t i o n
* of your codemodel .
c o d e m o d e l C : / S p i c e / l i b / s p i c e / s p i c e 2 p o l y . cm
* The o t h e r c o d e m o d e l s
codemodel C : / Spice / l i b
codemodel C : / Spice / l i b
codemodel C : / Spice / l i b
codemodel C : / Spice / l i b

/
/
/
/

spice
spice
spice
spice

/ a n a l o g . cm
/ d i g i t a l . cm
/ x t r a d e v . cm
/ x t r a e v t . cm

end
unset __flag
spinit contains a script which is run upon start up of ngspice. You may find details of scripting in
the next chapter. Aliases (name equivalences) are set. set filetype=ascii will yield ASCII
output in the output data file (rawfile), a more compact binary format is used otherwise. The
asterisk * will comment out this line. If used by ngspice, spinit will then load the XSPICE code
models from their absolute paths. You may also define relative paths here. set ngdebug will
yield a lot of additional debug output. Any other contents of the script. e.g. plotting preferences,
may be included here and started automatically by ngspice. The compatibility mode of ngspice
has to be set in spinit by set ngbehavior=all.
If the standard path for the libraries (see standard spinit above or /usr/local/lib/spice under CYGWIN and LINUX) is not adequate, you may add for example the ./configure options
--prefix=/usr --libdir=/usr/lib64 to set the codemodel search path to /usr/lib64/spice.
Besides the standard lib only lib64 is acknowledged.

16.6. USER DEFINED CONFIGURATION FILE .SPICEINIT

16.6

261

User defined configuration file .spiceinit

In addition to spinit you may define a file .spiceinit and put it into the current directory
or in your home directory. This file will be read in and executed after spinit, but before any
other input file is read. It may contain any script and override the commands given in spinit.
If the command line option -n is used upon ngspice start up, this file will be ignored.

16.7

Environmental variables

16.7.1

Ngspice specific variables

SPICE_LIB_DIR default: /usr/local/share/ngspice (LINUX, CYGWIN), C:\Spice\share\ngspice


(Windows)
SPICE_EXEC_DIR default: /usr/local/bin (LINUX, CYGWIN), C:\Spice\bin (Windows)
SPICE_BUGADDR default: http://ngspice.sourceforge.net/bugrep.html
Where to send bug reports on ngspice.
SPICE_EDITOR default: vi (LINUX, CYGWIN), notepad.exe (MINGW, Visual Studio)
Set the editor called in the edit command. Always overrides the EDITOR env. variable.
SPICE_ASCIIRAWFILE default: 0
Format of the rawfile. 0 for binary, and 1 for ascii.
SPICE_NEWS default: $SPICE_LIB_DIR/news
A file which is copied verbatim to stdout when ngspice starts in interactive mode.
SPICE_HELP_DIR default: $SPICE_LIB_DIR/helpdir
Help directory, not used in Windows mode
SPICE_HOST default: empty string
Used in the rspice command (probably obsolete, to be documented)
SPICE_SCRIPTS default: $SPICE_LIB_DIR/scripts
In this directory the spinit file will be searched.
SPICE_PATH default: $SPICE_EXEC_DIR/ngspice
Used in the aspice command (probably obsolete, to be documented)
NGSPICE_MEAS_PRECISION default: 5
Sets the number of digits if output values are printed by the meas(ure) command.
SPICE_NO_DATASEG_CHECK default: undefined
If defined, will suppress memory resource info (probably obsolete, not used on Windows
or where the /proc information system is available.)
NGSPICE_INPUT_DIR default: undefined
If defined, using a valid directory name will add the given directory to the search path
when looking for input files (*.cir, *.inc, *.lib).

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16.7.2

CHAPTER 16. STARTING NGSPICE

Common environment variables

TERM LINES COLS DISPLAY HOME PATH EDITOR SHELL POSIXLY_CORRECT

16.8

Memory usage

Ngspice started with batch option (-b) and rawfile output (-r rawfile) will store all simulation
data immediately into the rawfile without keeping them in memory. Thus very large circuits
may be simulated, the memory requested upon ngspice start up will depend on the circuit size,
but will not increase during simulation.
If you start ngspice in interactive mode or interactively with control section, all data will be kept
in memory, to be available for later evaluation. A large circuit may outgrow even Gigabytes of
memory. The same may happen after a very long simulation run with many vectors and many
time steps to be stored. Issuing the save <nodes> command will help to reduce memory
requirements by saving only the data defined by the command.

16.9

Simulation time

Simulating large circuits may take an considerable amount of CPU time. If this is of importance,
you should compile ngspice with the flags for optimum speed, set during configuring ngspice
compilation. Under LINUX, MINGW, and CYGWIN you should select the following option to
disable the debug mode, which slows down ngspice:
./configure --disable-debug
Adding --disable-debug will set the -O2 optimization flag for compiling and linking.
Under MS Visual Studio, you will have to select the release version which includes optimization
for speed.
If you have selected XSPICE (see chapters 12 and II) as part of your compilation configuration
(by adding the option --enable-xspice to your ./configure command), the value of trtol
(see 15.1.4) is set internally to 1 (instead of default 7) for higher precision if XSPICE code
model A devices included in the circuit. This may double or even triple the CPU time needed
for any transient simulation, because the amount of time steps and thus iteration steps is more
than doubled. For MS Visual Studio compilation there is currently no simple way to exclude
XSPICE during compilation.
You may enforce higher speed during XSPICE usage by setting the variable xtrtol in your
.spiceinit initialization file or in the .control section in front of the tran command (via set
xtrtol=2 using the set command 17.5.57) and override the above trtol reduction. Beware
however of precision or convergence issues if you use XSPICE A devices, especially if xtrtol
is set to values larger than 2.
If your circuit comprises mostly of MOS transistors, and you have a multi-core processor at
hand, you may benefit from OpenMP parallel processing, as described next (16.10).

16.10. NGSPICE ON MULTI-CORE PROCESSORS USING OPENMP

16.10

Ngspice on multi-core processors using OpenMP

16.10.1

Introduction

263

Todays computers typically come with CPUs having more than one core. It will thus be useful
to enhance ngspice to make use of such multi-core processors.
Using circuits comprising mostly of transistors and e.g. the BSIM3 model, around 2/3 of the
CPU time is spent in evaluating the model equations (e.g. in the BSIM3Load() function). The
same happens with other advanced transistor models. Thus this function should be paralleled, if
possible. Resulting from that the parallel processing has to be within a dedicated device model.
Interestingly solving the matrix takes only about 10% of the CPU time, so paralleling the matrix
solver is of secondary interest here!
A recent publication [1] has described a way to exactly do that using OpenMP, which is available
on many platforms and is easy to use, especially if you want to parallel processing of a for-loop.
I have chosen the BSIM3 version 3.3.0 model, located in the BSIM3 directory, as the first
example. The BSIM3load() function in b3ld.c contains two nested for-loops using linked lists
(models and instances, e.g. individual transistors). Unfortunately OpenMP requires a loop with
an integer index. So in file B3set.c an array is defined, filled with pointers to all instances of
BSIM3 and stored in model->BSIM3InstanceArray.
BSIM3load() is now a wrapper function, calling the for-loop, which runs through functions
BSIM3LoadOMP(), once per instance. Inside BSIM3LoadOMP() the model equations are calculated.
Typically you now need to synchronize the activities, in that storing the results into the matrix
has to be guarded. The trick offered by the authors now is that the storage is moved out of the
BSIM3LoadOMP() function. Inside BSIM3LoadOMP() the updated data are stored in extra
locations locally per instance, defined in bsim3def.h. Only after the complete for-loop is exercised, the update to the matrix is done in an extra function BSIM3LoadRhsMat() in the main
thread after the paralleled loop. No extra synchronization is required.
Then the thread programming needed is only a single line!!
#pragma omp parallel for num_threads(nthreads) private(here)
introducing the for-loop.
This of course is made possible only thanks to the OpenMP guys and the clever trick on no
synchronization introduced by the above cited authors.
The time-measuring function getrusage() used with LINUX or Cygwin to determine the CPU
time usage (with the rusage option enabled) counts tics from every core, adds them up, and
thus reports a CPU time value enlarged by a factor of 8 if 8 threads have been chosen. So now
ngspice is forced to use ftime for time measuring if OpenMP is selected.

16.10.2

Some results

Some results on an inverter chain with 627 CMOS inverters, running for 200ns, compiled with
Visual Studio professional 2008 on Windows 7 (full optimization) or gcc 4.4, SUSE LINUX
11.2, -O2, on a i7 860 machine with four real cores (and 4 virtuals using hyperthreading) are
shown in table 16.1.

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CHAPTER 16. STARTING NGSPICE

Table 16.1: OpenMP performance


Threads
CPU time [s] CPU time [s]
Windows
LINUX
1 (standard)
167
165
1 (OpenMP)
174
167
2
110
110
3
95
94-120
4
83
107
6
94
90
8
93
91
So we see a ngspice speed up of nearly a factor of two! Even on an older notebook with dual
core processor, I have got more than 1.5x improvement using two threads. Similar results are to
be expected from BSIM4.

16.10.3

Usage

To state it clearly: OpenMP is installed inside the model equations of a particular model. So for
the moment it is available only in BSIM3 version 3.3.0, not in version 3.2.4 nor in any other
BSIM3 model, in BSIM4 versions 4.6.5 or 4.7, not in any other BSIM4 model, and in B4SOI,
version 4.3.1, not in any other SOI model. Older parameter files of version 4.6.x (x any number
up to 5) are accepted, you have to check for compatibility.
Under LINUX you may run
./autogen.sh
./configure ...

--enable-openmp

make install
The same has been tested under MS Windows with CYGWIN and MINGW as well and delivers similar results.
Under MS Windows with Visual Studio Professional you have to place an additional preprocessor flag USE_OMP, and then enable /openmp. Visual Studio Express is not sufficient
due to lack of OpenMP support. Even Visual Studio Professional lacks debugging support
for OpenMP. There are local preprocessor flags (USE_OMP3 in bsim3def.h, USE_OMP4 in
bsim4def.h, and USE_OMP4SOI in b4soidef.h) which you may modify individually if you
want to switch off OpenMP in only one of the models BSIM3, BSIM4, or B4SOI.
The number of threads has to be set manually by placing
set num_threads=4
into spinit or .spiceinit. If OpenMP is enabled, but num_threads not set, a default value num_threads=2
is set internally.
If you run a circuit, please keep in mind to select BSIM3 (levels 8, 49) version 3.3.0 (11.2.9),
by placing this version number into your parameter files, BSIM4 (levels 14, 54) version 4.6.5
or 4.7 (11.2.10), or B4SOI (levels 10, 58) version 4.3.1 (11.2.12).
If you run ./configure without --enable-openmp (or without USE_OMP preprocessor flag
under MS Windows), you will get the standard, not paralleled BSIM3 and BSIM4 model, as

16.11. SERVER MODE OPTION -S

265

has been available from Berkeley. If OpenMP is selected and the number of threads set to 1,
there will be only a very slight CPU time disadvantage (typ. 3%) compared to the standard, non
OpenMP build.

16.10.4

Literature

[1] R.K. Perng, T.-H. Weng, and K.-C. Li: "On Performance Enhancement of Circuit Simulation
Using Multithreaded Techniques", IEEE International Conference on Computational Science
and Engineering, 2009, pp. 158-165

16.11

Server mode option -s

A program may write the spice input to the console. This output is redirected to ngspice via |.
ngspice called with the -s option writes its output to the console, which again is redirected to a
receiving program by |. In the following simple example cat reads the input file and prints it
content to the console, which is redirected to ngspice by a first pipe, ngspice transfers its output
(similar to a raw file, see below) to less via another pipe.
Example command line:
c a t i n p u t . c i r | n g s p i c e s | l e s s
Under MS Windows you will need to compile ngspice as a console application (see chapt.
32.2.5) for this server mode usage.
Example input file:
t e s t s
v1 1 0 1
r 1 1 0 2k
. options filetype = ascii
. s a v e i ( v1 )
. dc v1 1 1 0 . 5
. end
If you start ngspice console with
ngspice -s
you may type in the above circuit line by line (not to forget the first line, which is a title and
will be ignored). If you close your input with ctrl Z, and return, you will get the following
output (this is valid for MINGW only) on the console, like a raw file:
Circuit: test -s
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
Title: test -s

266

CHAPTER 16. STARTING NGSPICE

Date: Sun Jan 15 18:57:13 2012


Plotname: DC transfer characteristic
Flags: real
No. Variables: 2
No. Points: 0
Variables:
No. of Data Columns : 2
0 v(v-sweep) voltage
1 i(v1) current
Values:
0
-1.000000000000000e+000
5.000000000000000e-004
1
-5.000000000000000e-001
2.500000000000000e-004
2
0.000000000000000e+000
0.000000000000000e+000
3
5.000000000000000e-001
-2.500000000000000e-004
4
1.000000000000000e+000
-5.000000000000000e-004
@@@ 122 5

The number 5 of the last line @@@ 122 5 shows the number of data points, which is missing in
the above line No. Points: 0 because at the time of writing to the console it has not yet
been available.
ctrl Z is not usable here in LINUX, a patch to install ctrl D instead is being evaluated.

16.12

Ngspice control via input, output fifos

The following bash script (under LINUX)


- launches ngspice in another thread.
- writes some commands in ngspice input
- reads the output and prints them on the console.

16.12. NGSPICE CONTROL VIA INPUT, OUTPUT FIFOS


Example:
# ! / u s r / b i n / env b a s h
NGSPICE_COMMAND=" n g s p i c e "
rm i n p u t . f i f o
rm o u t p u t . f i f o
mkfifo input . f i f o
mkfifo output . f i f o
$NGSPICE_COMMAND

p i < i n p u t . f i f o > o u t p u t . f i f o &

e x e c 3> i n p u t . f i f o
echo " I can w r i t e t o i n p u t . f i f o "
echo " S t a r t p r o c e s s i n g . . . "
echo ""
echo
echo
echo
echo
echo
echo

" s o u r c e c i r c u i t . c i r " >&3


" s e t n o a s k q u i t " >&3
" s e t n o b r e a k " >&3
" t r a n 0 . 0 1 ms 0 . 1 ms">&3
" p r i n t n0 " >&3
" q u i t " >&3

e c h o " Try t o open o u t p u t . f i f o . . . "


e x e c 4< o u t p u t . f i f o
e c h o " I c a n r e a d from o u t p u t . f i f o "
e c h o " Ready t o r e a d . . . "
while read output
do
echo $ o u t p u t
done <&4
e x e c 3>&
e x e c 4>&
e c h o " End p r o c e s s i n g "

The input file for spice is:

267

268

CHAPTER 16. STARTING NGSPICE

Circuit.cir:
* Circuit . cir
V1 n0 0 SIN ( 0 10 1kHz )
C1 n1 n0 3 . 3 nF
R1 0 n1 1k
. end

16.13

Compatibility

ngspice is a direct derivative of spice3f5 from UC Berkeley and thus inherits all of the commands available in its predecessor. Thanks to the open source policy of UCB (original spice3
from 1994 is still available here), several commercial variants have sprung off, either being more
dedicated to IC design or more concentrating on simulating discrete and board level electronics.
None of the commercial and almost none of the freely downloadable spice providers publishes
the source code. All of them have proceeded with the development, by adding functionality, or
by adding a more dedicated user interface. Some have kept the original spice syntax for their
netlist description, others have quickly changed some if not many of the commands, functions
and procedures. Thus it is difficult, if not impossible, to offer a simulator which acknowledges
all of these netlist dialects. ngspice includes some features which enhance compatibility which
are included automatically. This selection may be controlled to some extend by setting the compatibility mode. Others may be invoked by the user by small additions to the netlist input file.
Some of them are listed in this chapter, some will be integrated into ngspice at a later stage,
others will be added if they are reported by users.

16.13.1

Compatibility mode

The variable (17.7) ngbehavior sets the compatibility mode. all is set as the default value.
spice3 as invoked by the command
set ngbehavior=spice3
in spinit or .spiceinit will disable some of the advanced ngspice features. ps will enable
including a library by a simple .lib <lib_filename> statement which is not compatible to
the more comfortable library handling described in chapt. 2.7.

16.13.2

Missing functions

You may add one or more function definitions to your input file, as listed below.
.func
.func
.func
.func

LIMIT(x,a,b) {min(max(x, a), b)}


PWR(x,a) {abs(x) ** a}
PWRS(x,a) {sgn(x) * PWR(x,a)}
stp(x) {u(x)}

16.13. COMPATIBILITY

16.13.3

Devices

16.13.3.1

E Source with LAPLACE

269

see chapt. 5.2.5.

16.13.3.2

VSwitch

The VSwitch
S1 2 3 11 0 SW
.MODEL SW VSWITCH(VON=5V VOFF=0V RON=0.1 ROFF=100K)
may become
a1 11 (2 3) sw
.MODEL SW aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e5
+ r_on=0.1 log=TRUE)
The XSPICE option has to be enabled.

16.13.4

Controls and commands

16.13.4.1

.lib

The ngspice .lib command (see 2.7) requires two parameters, a file name followed by a library
name. If no library name is given, the line
.lib filename
should be replaced by
.inc filename
Alternatively, the compatibility mode (16.13.1) may be set to ps.

16.13.4.2

.step

Repeated analysis in ngspice if offered by a short script inside of a .control section (see chapt.
17.8.7) added to the input file. A simple application (multiple dc sweeps) is shown below.

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Input file with parameter sweep


p a r a m e t e r sweep
* r e s i s t i v e d i v i d e r , R1 s w e p t from s t a r t _ r t o s t o p _ r
* r e p l a c e s . STEP R1 1k 10 k 1k
R1 1 2 1k
R2 2 0 1k
VDD 1 0 DC 1
. dc VDD 0 1 . 1
. control
l e t s t a r t _ r = 1k
l e t s t o p _ r = 10 k
l e t d e l t a _ r = 1k
let r_act = start_r
* loop
while r_act le stop_r
a l t e r r1 r _ a c t
run
w r i t e dcsweep . o u t v ( 2 )
set appendwrite
let r_act = r_act + delta_r
end
p l o t dc1 . v ( 2 ) dc2 . v ( 2 ) dc3 . v ( 2 ) dc4 . v ( 2 ) dc5 . v ( 2 )
+ dc6 . v ( 2 ) dc7 . v ( 2 ) dc8 . v ( 2 ) dc9 . v ( 2 ) dc10 . v ( 2 )
. endc
. end

16.14

Tests

The ngspice distribution is accompanied by a suite of test input and output files, located in the
directory ngspice/tests. Originally this suite was meant to see if ngspice with all models
was made and installed properly. It is started by
$ make check
from within your compilation and development shell. A sequence of simulations is thus started,
its outputs compared to given output files by comparisons string by string. This feature is
momentarily used only to check for the BSIM3 model (11.2.9) and the XSPICE extension (12).
Several other input files located in directory ngspice/tests may serve as light-weight examples
for invoking devices and simple circuits.
Todays very complex device models (BSIM4 (see 11.2.10), HiSIM (see 11.2.14) and others)
require a different strategy for verification. Under development for ngspice is the CMC Regression test by Colin McAndrew, which accompanies every new model. A major advantage is the
scalability of the diff comparisons, which check for equality within a given tolerance. A set of

16.15. REPORTING BUGS AND ERRORS

271

Perl modules cares for input, output and comparisons of the models. Currently BSIM4, BSIMSOI4, HiSIM, and HiSIMHV models implement the new test. You may invoke it by running
the command given above or by
$ make -i check 2>&1 | tee results
-i will make make to ignore any errors, tee will provide console output as well as printing to
file results. Be aware that under MS Windows you will need the console binary (see 32.2.5)
to run the CMC tests, and you have to have Perl installed!

16.15

Reporting bugs and errors

Ngspice is a complex piece of software. The source code contains over 1500 files. Various
models and simulation procedures are provided, some of them not used and tested intensively.
Therefore errors may be found, some still evolving from the original spice3f5 code, others
introduced during the ongoing code enhancements.
If you happen to experience an error during the usage of ngspice, please send a report to the
development team. Ngspice is hosted on sourceforge, the preferred place to post a bug report is
the ngspice bug tracker. We would prefer to have your bug tested against the actual source code
available at Git, but of course a report using the most recent ngspice release is welcome! Please
provide the following information with your report:
Ngspice version
Operating system
Small input file to reproduce the bug
Actual output versus the expected output

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Chapter 17
Interactive Interpreter
17.1

Introduction

The simulation flow in ngspice (input, simulation, output) may be controlled by dot commands
(see chapt. 15 and 16.4.1) in batch mode. There is, however, a much more powerful control
scheme available in ngspice, traditionally coined Interactive Interpreter, but being much more
than just that. In fact there are several ways to use this feature, truly interactively by typing
commands to the input, but also running command sequences as scripts or as part of your input
deck in a quasi batch mode.
You may type in expressions, functions (17.2) or commands (17.5) into the input console to
elaborate on data already achieved from the interactive simulation session.
Sequences of commands, functions and control structures (17.6) may be assembled as a script
(17.8) into a file, and then activated by just typing the file name into the console input of an
interactive ngspice session.
Finally, and most useful, is it to add a script to the input file, in addition the the netlist and dot
commands. This is achieved by enclosing the script into .control ... .endc (see 16.4.3,
and 17.8.7 for an example). This feature enables a wealth of control options. You may set
internal (17.7) and other variables, start a simulation, evaluate the simulation output, start a new
simulation based on these data, and finally make use of many options for outputting the data
(graphically or into output files).

17.2

Expressions, Functions, and Constants

Ngspice and ngnutmeg store data in the form of vectors: time, voltage, etc. Each vector has a
type, and vectors can be operated on and combined algebraically in ways consistent with their
types. Vectors are normally created as the output of a simulation, or when a data file (output raw
file) is read in again (ngspice, ngnutmeg, see the load command 17.5.36), or when the initial
data-file is loaded directly into ngnutmeg. They can also be created with the let command
817.5.33).
An expression is an algebraic formula involving vectors and scalars (a scalar is a vector of
length 1) and the following operations:

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+ * / ^ % ,

% is the modulo operator, and the comma operator has two meanings: if it is present in the
argument list of a user definable function, it serves to separate the arguments. Otherwise, the
term x , y is synonymous with x + j(y). Also available are the logical operations & (and),
| (or), ! (not), and the relational operations <, >, >=, <=, =, and <> (not equal). If used in an
algebraic expression they work like they would in C, producing values of 0 or 1. The relational
operators have the following synonyms:

Operator
gt
lt
ge
le
ne
and
or
not
eq

Synonym
>
<
>=
<=
<>
&
|
!
=

The operators are useful when < and > might be confused with the internal IO redirection (see
17.4, which is almost always happening). It is however safe to use < and > with the define
command (17.5.14).

The following functions are available:

17.2. EXPRESSIONS, FUNCTIONS, AND CONSTANTS


Name
mag(vector)
ph(vector)
cph(vector)
unwrap(vector)
j(vector)
real(vector
imag(vector)
db(vector)
log(vector)
ln(vector)
exp(vector)
abs(vector)
sqrt(vector)
sin(vector)
cos(vector)
tan(vector)
atan(vector)
sinh(vector)
cosh(vector)
tanh(vector)
floor(vector)
ceil(vector)
norm(vector)
mean(vector)

avg(vector)

group_delay(vector)

vector(number)

unitvec(number)

Function
Magnitude of vector (same as abs(vector)).
Phase of vector.
Phase of vector. Continuous values, no discontinuity at
PI.
Phase of vector. Continuous values, no discontinuity at
PI. Real phase vector in degrees as input.
i(sqrt(-1)) times vector.
The real component of vector.
The imaginary part of vector.
20 log10(mag(vector)).
The logarithm (base 10) of vector.
The natural logarithm (base e) of vector.
e to the vector power.
The absolute value of vector (same as mag).
The square root of vector.
The sine of vector.
The cosine of vector.
The tangent of vector.
The inverse tangent of vector.
The hyperbolic sine of vector.
The hyperbolic cosine of vector.
The hyperbolic tangent of vector.
Largest integer that is less than or equal to vector.
Smallest integer that is greater than or equal to vector.
The vector normalized to 1 (i.e, the largest magnitude of
any component is 1).
The result is a scalar (a length 1 vector) that is the mean of
the elements of vector (elements values added, divided by
number of elements).
The average of a vector.
Returns a vector where each element is the mean of the
preceding elements of the input vector (including the
actual element).
Calculates the group delay -dphase[rad]/dw[rad/s]. Input is
the complex vector of a system transfer function versus
frequency, resembling damping and phase per frequency
value. Output is a vector of group delay values (real values
of delay times) versus frequency.
The result is a vector of length number, with elements 0, 1,
... number - 1. If number is a vector then just the first
element is taken, and if it isnt an integer then the floor of
the magnitude is used.
The result is a vector of length number, all elements having
a value 1.

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Name
length(vector)
interpolate(plot.vector)

deriv(vector)

vecd(vector)
vecmin(vector)
minimum(vector)
vecmax(vector)
maximum(vector)
fft(vector)
ifft(vector)
sortorder(vector)

Function
The length of vector.
The result of interpolating the named vector onto the scale
of the current plot. This function uses the variable
polydegree to determine the degree of interpolation.
Calculates the derivative of the given vector. This uses
numeric differentiation by interpolating a polynomial and
may not produce satisfactory results (particularly with
iterated differentiation). The implementation only
calculates the derivative with respect to the real component
of that vectors scale.
Compute the differential of a vector.
Returns the value of the vector element with minimum
value. Same as minimum.
Returns the value of the vector element with minimum
value. Same as vecmin.
Returns the value of the vector element with maximum
value. Same as maximum.
Returns the value of the vector element with maximum
value. Same as vecmax.
fast fourier transform
inverse fast fourier transform
Returns a vector with the positions of the elements in a real
vector after they have been sorted into increasing order
using a stable method (qsort).

Several functions offering statistical procedures are listed in the following table:

17.2. EXPRESSIONS, FUNCTIONS, AND CONSTANTS


Name
rnd(vector)

sgauss(vector)

sunif(vector)

poisson(vector)

exponential(vector)

277

Function
A vector with each component a random integer between 0
and the absolute value of the input vectors corresponding
integer element value.
Returns a vector of random numbers drawn from a
Gaussian distribution (real value, mean = 0 , standard
deviation = 1). The length of the vector returned is
determined by the input vector. The contents of the input
vector will not be used. A call to sgauss(0) will return a
single value of a random number as a vector of length 1..
Returns a vector of random real numbers uniformly
distributed in the interval [-1 .. 1[. The length of the vector
returned is determined by the input vector. The contents of
the input vector will not be used. A call to sunif(0) will
return a single value of a random number as a vector of
length 1.
Returns a vector with its elements being integers drawn
from a Poisson distribution. The elements of the input
vector (real numbers) are the expected numbers l.
Complex vectors are allowed, real and imaginary values
are treated separately.
Returns a vector with its elements (real numbers) drawn
from an exponential distribution. The elements of the input
vector are the respective mean values (real numbers).
Complex vectors are allowed, real and imaginary values
are treated separately.

An input vector may be either the name of a vector already defined or a floating-point number
(a scalar). A scalar will result in an output vector of length 1. A number may be written in
any format acceptable to ngspice, such as 14.6Meg or -1.231e-4. Note that you can either use
scientific notation or one of the abbreviations like MEG or G, but not both. As with ngspice, a
number may have trailing alphabetic characters.
The notation expr [num] denotes the numth element of expr. For multi-dimensional vectors,
a vector of one less dimension is returned. Also for multi-dimensional vectors, the notation
expr[m][n] will return the nth element of the mth subvector. To get a subrange of a vector, use
the form expr[lower, upper]. To reference vectors in a plot that is not the current plot (see the
setplot command, below), the notation plotname.vecname can be used. Either a plotname or
a vector name may be the wildcard all. If the plotname is all, matching vectors from all plots
are specified, and if the vector name is all, all vectors in the specified plots are referenced. Note
that you may not use binary operations on expressions involving wildcards - it is not obvious
what all + all should denote, for instance. Thus some (contrived) examples of expressions are:
Expressions examples:
c o s ( TIME ) + db ( v ( 3 ) )
s i n ( cos ( log ( [ 1 2 3 4 5 6 7 8 9 1 0 ] ) ) )
TIME * r n d ( v ( 9 ) ) 15 * c o s ( v i n # b r a n c h ) ^ [ 7 . 9 e5 8 ]
n o t ( ( a c 3 . FREQ [ 3 2 ] & t r a n 1 . TIME [ 1 0 ] ) g t 3 )
( s u n i f ( 0 ) ge 0 ) ? 1 . 0 : 2 . 0
mag ( f f t ( v ( 1 8 ) ) )

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Vector names in ngspice may have look like @dname[param], where dname is either the name
of a device instance or of a device model. This vector contains the value of the param parameter
of the device or model. See Appendix, chapt. 31 for details of which parameters are available.
The value is a vector of length 1. This function is also available with the show command, and
is available with variables for convenience for command scripts.
There are a number of pre-defined constants in ngspice, which you may use by their name. They
are stored in plot (17.3) const and are listed in the table below:
Name
pi
e
c
i
kelvin
echarge
boltz
planck
yes
no
TRUE
FALSE

Description

e (the base of natural logarithms)


c (the speed of light)
i (the square root of -1)
(absolute zero in centigrade)
q (the charge of an electron)
k (Boltzmanns constant)
h (Plancks constant)
boolean
boolean
boolean
boolean

Value
3.14159...
2.71828...
m/sec
299,792,500

1
-273.15C
1.60219e-19 C
1.38062e-23J/K
6.62620e-34
1
0
1
0

These constants are all given in MKS units. If you define another variable with a name that
conflicts with one of these then it takes precedence.
Additional constants may be generated during circuit setup (see .csparam, 2.10).

17.3

Plots

The output vectors of any analysis are stored in plots, a traditional SPICE notion. A plot is a
group of vectors. A first tran command will generate several vectors within a plot tran1. A
subsequent tran command will store their vectors in tran2. Then a linearize command will
linearize all vectors from tran2 and store them in tran3, which then becomes the current plot. A
fft will generate a plot spec1, again now the current plot. The display command always will
show all vectors in the current plot. Echo $plots followed by Return lists all plots generated
so far. Setplot followed by Return will show all plots and ask for a (new) plot to become
current. A simple Return will end the command. Setplot name will change the current plot
to name (e.g. setplot tran2 will make tran2 the current plot). A sequence name.vector
may be used to access the vector from a foreign plot.
You may generate plots by yourself: setplot new will generate a new plot named unknown1,
set curplottitle=a new plot will set a title, set curplotname=myplot will set its
name as a short description, set curplotdate=Sat Aug 28 10:49:42 2010 will set its
date. Note that strings with spaces have to be given with double quotes.
Of course the notion plot will be used by this manual also in its more common meaning,
denoting a graphics plot or being a plot command. Be careful to get the correct meaning.

17.4. COMMAND INTERPRETATION

17.4

Command Interpretation

17.4.1

On the console

279

On the ngspice console window (or into the Windows GUI) you may directly type in any command from 17.5. Within a command sequence Input/output redirection is available (see chapt.
17.8.8 for an example) - the symbols >, >>, >&, >>&, and < have the same effects as in the
C-shell. This I/O-redirection is internal to ngspice commands, and should not be mixed up with
the external I/O-redirection offered by the usual shells (LINUX, MSYS etc.), see 17.5.62.
You may type multiple commands on one line, separated by semicolons.

17.4.2

Scripts

If a word is typed as a command, and there is no built-in command with that name, the directories in the sourcepath list are searched in order for a file with the name given by the word. If
it is found, it is read in as a command file (as if it were sourced). Before it is read, however, the
variables argc and argv are set to the number of words following the file-name on the command line, and a list of those words respectively. After the file is finished, these variables are
unset. Note that if a command file calls another, it must save its argv and argc since they are
altered. Also, command files may not be re-entrant since there are no local variables. Of course,
the procedures may explicitly manipulate a stack.... This way one can write scripts analogous
to shell scripts for ngnutmeg and ngspice.
Note that for the script to work with ngspice, it must begin with a blank line (or whatever else,
since it is thrown away) and then a line with .control on it. This is an unfortunate result
of the source command being used for both circuit input and command file execution. Note
also that this allows the user to merely type the name of a circuit file as a command and it is
automatically run. The commands are executed immediately, without running any analyses that
may be specified in the circuit (to execute the analyses before the script executes, include a
run command in the script).
There are various command scripts installed in /usr/local/lib/spice/scripts (or whatever the path is on your machine), and the default sourcepath includes this directory, so you
can use these command files (almost) like built-in commands.

17.4.3

Add-on to circuit file

The problably most common way to invoke the commands described in the following chapter
17.5 is to add a .control ... .endc section to the circuit input file (see 16.4.3).

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Example:
. control
pre_set strict_errorhandling
u n s e t ngdebug
* s a v e o u t p u t s and s p e c i a l s
s a v e x1 . x1 . x1 . 7 V( 9 ) V( 1 0 ) V( 1 1 ) V( 1 2 ) V( 1 3 )
run
display
* p l o t t h e i n p u t s , u s e o f f s e t t o p l o t on t o p o f e a c h o t h e r
p l o t v (1) v (2)+4 v (3)+8 v (4)+12 v (5)+16 v (6)+20 v (7)+24 v (8)+28
* p l o t t h e o u t p u t s , u s e o f f s e t t o p l o t on t o p o f e a c h o t h e r
p l o t v ( 9 ) v (10)+4 v (11)+8 v (12)+12 v (13)+16
. endc

17.5

Commands

Commands marked with a * are only available in ngspice, not in ngnutmeg.

17.5.1

Ac*: Perform an AC, small-signal frequency response analysis

General Form:
a c ( DEC | OCT | LIN ) N F s t a r t F s t o p
Do an small signal ac analysis (see also chapter 15.3.1) over the specified frequency range.
DEC decade variation, and N is the number of points per decade.
OCT stands for octave variation, and N is the number of points per octave.
LIN stands for linear variation, and N is the number of points.
fstart is the starting frequency, and fstop is the final frequency.
Note that in order for this analysis to be meaningful, at least one independent source must have
been specified with an ac value.
In this ac analysis all non-linear devices are linearized around their actual dc operating point.
All Ls and Cs get their imaginary value, depending on the actual frequency step. Each output
vector will be calculated relative to the input voltage (current) given by the ac value (Iin equals
to 1 in the example below). The resulting node voltages (and branch currents) are complex
vectors. Therefore you have to be careful using the plot command.

17.5. COMMANDS

281

Example:
* AC t e s t
I i n 1 0 AC 1
R1 1 2 100
L1 2 0 1
. control
AC LIN 101 10 10K
plot v (2)
$ real part !
p l o t mag ( v ( 2 ) ) $ m a g n i t u d e
p l o t db ( v ( 2 ) )
$ same a s vdb ( 2 )
p l o t imag ( v ( 2 ) ) $ i m a g i n a r y p a r t o f v ( 2 )
p l o t r e a l ( v ( 2 ) ) $ same a s p l o t v ( 2 )
p l o t phase ( v ( 2 ) ) $ phase in rad
p l o t cph ( v ( 2 ) ) $ p h a s e i n r a d , c o n t i n u o u s beyond p i
p l o t 1 8 0 / P I * p h a s e ( v ( 2 ) ) $ p h a s e i n deg
. endc
. end
In addition to the plot examples given above you may use the variants of vxx(node) described in
chapter 15.5.2 like vdb(2). An option to suppress OP analysis before AC may be set for linear
circuits (15.1.3).

17.5.2

Alias: Create an alias for a command

General Form:
a l i a s [ word ] [ t e x t

...]

Causes word to be aliased to text. History substitutions may be used, as in C-shell aliases.

17.5.3

Alter*: Change a device or model parameter

Alter changes the value for a device or a specified parameter of a device or model.
General Form:
a l t e r dev = < e x p r e s s i o n >
a l t e r dev param = < e x p r e s s i o n >
a l t e r @dev [ param ] = < e x p r e s s i o n >
<expression> must be real (complex isnt handled right now, integer is fine though, but no
strings. For booleans, use 0/1.
Old style (pre 3f4):
a l t e r device value
a l t e r device parameter value [ parameter value ]
Using the old style, its first form is used by simple devices which have one principal value (resistors, capacitors, etc.) where the second form is for more complex devices (bjts, etc.). Model

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CHAPTER 17. INTERACTIVE INTERPRETER

parameters can be changed with the second form if the name contains a "#". For specifying a
list of parameters as values, start it with "[", followed by the values in the list, and end with "]".
Be sure to place a space between each of the values and before and after the "[" and "]".
Some examples are given below:
Examples (Spice3f4 style):
alter
alter
alter
alter
alter

vd = 0 . 1
vg dc = 0 . 6
@m1[w] = 15 e 06
@vg [ s i n ] [ 1 1 . 5 2MEG ]
@Vi [ pwl ] = [ 0 1 . 2 100 p 0 ]

alter may have vectors (17.8.2) or variables (17.8.1) as parameters.


Examples (vector or variable in parameter list):
a l t e r @vg [ s i n ] [ 1 1 . 5 $&n e w f r e q ]
a l t e r @Vi [ pwl ] = [ 0 1 . 2 $ n e w p e r i o d 0 ]
You may change a parameter of a device residing in a subcircuit, e.g. of MOS transistor msub1
in subcircuit xm1 (see also chapt. 31.1).
Examples (parameter of device in subcircuit):
a l t e r m. xm1 . msub1 w = 20 u
a l t e r @m. xm1 . msub1 [w] = 20 u

17.5.4

Altermod*: Change model parameter(s)

General form:
a l t e r m o d mod param = < e x p r e s s i o n >
a l t e r m o d @mod[ param ] = < e x p r e s s i o n >
Example:
a l t e r m o d nc1 t o x = 10 e9
a l t e r m o d @nc1 [ t o x ] = 10 e9
Altermod operates on models and is used to change model parameters. The above example
will change the parameter tox in all devices using the model nc1, which is defined as
*** BSIM3v3 model
.MODEL nc1 nmos LEVEL=8 version = 3.2.2
+ acm = 2 mobmod = 1 capmod = 1 noimod = 1
+ rs = 2.84E+03 rd = 2.84E+03 rsh = 45
+ tox = 20E-9 xj = 0.25E-6 nch = 1.7E+17
+ ...
If you invoke the model by the MOS device
M1 d g s b nc1 w=10u l=1u

17.5. COMMANDS

283

you might also insert the device name M1 for mod as in


altermod M1 tox = 10e-9
The model parameter tox will be modified, however not only for device M1, but for all devices
using the associated MOS model nc1!
If you want to run corner simulations within a single simulation flow, the following option of
altermod may be of help. The parameter set with name modn may be overrun by the altermod
command specifying a model file. All parameter values fitting to the existing model which
is defined as modn will be modified. As usual the reset command (see 17.5.49) restores the
original values. The model file (see 2.3) has to use the standard specifications for an input file,
the .model section is the relevant part. However the first line in the model file will be ignored by
the input parser, so it should contain only some title information. The .model statement should
appear then in the second or any later line. More than one .model section may reside in the file.
General form:
a l t e r m o d mod1 [ mod2 . . mod15 ] f i l e = <model f i l e name>
a l t e r m o d mod1 [ mod2 . . mod15 ] f i l e <model f i l e name>
Example:
a l t e r m o d nch f i l e = BSIM3_nmos . mod
a l t e r m o d pch nch f i l e BSIM4_mos . mod
Be careful that the new model file corresponds to the existing model selected by modn. The existing models are defined during circuit setup at start up of ngspice. Models have been included
by .model statements (2.3) in your input file or included by the .include command. In the
example given above, the models nch (or nch and pch) have to be already available before calling altermod. If they are not found in the active circuit, ngspice will terminate with an error
message. There is no checking however of the version and level parameters! So you have to
be responsible for offering model data of the same model level (e.g. level 8 for BSIM3). Thus
no new model is selectable by altermod, but the parameters of the existing model(s) may be
changed (partially, completely, temporarily).

17.5.5

Asciiplot: Plot values using old-style character plots

General Form:
asciiplot plotargs
Produce a line printer plot of the vectors. The plot is sent to the standard output, so you can put
it into a file with asciiplot args ... > file. The set options width, height, and nobreak determine
the width and height of the plot, and whether there are page breaks, respectively. Note that you
will have problems if you try to asciiplot something with an X-scale that isnt monotonic (i.e,
something like sin(TIME) ), because asciiplot uses a simple-minded linear interpolation. The
asciiplot command doesnt deal with log scales or the delta keywords.

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CHAPTER 17. INTERACTIVE INTERPRETER

Aspice*: Asynchronous ngspice run

General Form:
aspice input f i l e [ output f i l e ]
Start an ngspice run, and when it is finished load the resulting data. The raw data is kept in
a temporary file. If output-file is specified then the diagnostic output is directed into that file,
otherwise it is thrown away.

17.5.7

Bug: Mail a bug report

General Form:
bug
Send a bug report. Please include a short summary of the problem, the version number and
name of the operating system that you are running, the version of ngspice that you are running,
and the relevant ngspice input file. (If you have defined BUGADDR, the mail is delivered to there.)

17.5.8

Cd: Change directory

General Form:
cd [ d i r e c t o r y ]
Change the current working directory to directory, or to the users home directory if none is
given.

17.5.9

Cdump: Dump the control flow to the screen

General Form:
cdump
Dumps the control sequence to the screen (all statements inside the .control ... .endc structure
before the line with cdump). Indentations show the structure of the sequence. The example
below is printed if you add cdump to /examples/Monte_Carlo/MonteCarlo.sp.

17.5. COMMANDS

285

Example (abbreviated):
l e t mc_runs =5
l e t r u n =0
...
d e f i n e a g a u s s ( nom , a v a r , s i g ) ( nom + a v a r / s i g * s g a u s s ( 0 ) )
d e f i n e l i m i t ( nom , a v a r ) ( nom + ( ( s g a u s s ( 0 ) >=0) ? a v a r : a v a r ) )
d o w h i l e r u n < mc_runs
a l t e r c1 = u n i f ( 1 e 09 , 0 . 1 )
...
a c o c t 100 250 k 10meg
meas a c bw t r i g vdb ( o u t ) v a l =10 r i s e =1 t a r g vdb ( o u t ) v a l =10 f a l l =1
s e t r u n =" $&r u n "
...
l e t run=run + 1
end
p l o t db ( { $ s c r a t c h } . a l l v )
echo
p r i n t { $ s c r a t c h } . bwh
cdump

17.5.10

Circbyline*: Enter a circuit line by line

General Form:
circbyline line
Enter a circuit line by line. line is any circuit line, as found in the *.cir ngspice input files.
The first line is a title line. The entry will be finished by entering .end. Circuit parsing is then
started automatically.
Example:
circbyline
circbyline
circbyline
circbyline
circbyline
run
p l o t i ( v1 )

17.5.11

test circuit
v1 1 0 1
r1 1 0 1
. dc v1 0 . 5 1 . 5 0 . 1
. end

Codemodel*: Load an XSPICE code model library

General Form:
codemodel [ l i b r a r y

file ]

Load a XSPICE code model shared library file (e.g. analog.cm ...). Only available if ngspice is
compiled with the XSPICE option (enable-xspice) or with the Windows executable distributed
since ngspice21. This command has to be called from spinit (see chapt. 16.5) (or .spiceinit for
personal code models, 16.6).

286

17.5.12

CHAPTER 17. INTERACTIVE INTERPRETER

Compose: Compose a vector

General Form:
compose name v a l u e s v a l u e 1 [ v a l u e 2 . . . ]
compose name parm = v a l [ parm = v a l . . . ]
The first form takes the values and creates a new vector, the values may be arbitrary expressions.
The second form has the following possible parameters:
start The value at which the vector should start.
stop The value at which the vector should end.
step The difference between successive elements.
lin The number of points, linearly spaced..

17.5.13

Dc*: Perform a DC-sweep analysis

General Form:
dc S o u r c e Name V s t a r t V s t o p V i n c r [ S o u r c e 2 V s t a r t 2 V s t o p 2 V i n c r 2 ]
Do a dc transfer curve analysis. See the previous chapter 15.3.2 for more details. Several
options may be set (15.1.2).

17.5.14

Define: Define a function

General Form:
d e f i n e f u n c t i o n ( arg1 , arg2 ,

...)

expression

Define the user-definable function with the name function and arguments arg1, arg2, ... to be
expression, which may involve the arguments. When the function is later used, the arguments it
is given are substituted for the formal arguments when it is parsed. If expression is not present,
any definition for function is printed, and if there are no arguments to define then all currently
active definitions are printed. Note that you may have different functions defined with the same
name but different arities. Some useful definitions are:
Example:
d e f i n e max ( x , y ) ( x > y ) * x + ( x <= y ) * y
d e f i n e min ( x , y ) ( x < y ) * x + ( x >= y ) * y
d e f i n e l i m i t ( nom , a v a r ) ( nom + ( ( s g a u s s ( 0 ) >= 0 ) ? a v a r : a v a r ) )

17.5.15

Deftype: Define a new type for a vector or plot

General Form:
d e f t y p e [ v | p ] typename abbrev

17.5. COMMANDS

287

defines types for vectors and plots. abbrev will be used to parse things like abbrev(name) and
to label axes with M<abbrev>, instead of numbers. It may be omitted. Also, the command
"deftype p plottype pattern ..." will assign plottype as the name to any plot with one of the
patterns in its Name: field.
Example:
deftype v capacitance F
s e t t y p e c a p a c i t a n c e moscap
p l o t moscap v s v ( c c )

17.5.16

Delete*: Remove a trace or breakpoint

General Form:
d e l e t e [ debugnumber . . . ]
Delete the specified saved nodes and parameters, breakpoints and traces. The debug numbers
are those shown by the status command (unless you do status > file, in which case the debug
numbers are not printed).

17.5.17

Destroy: Delete an output data set

General Form:
destroy [ plotnames |

all ]

Release the memory holding the output data (the given plot or all plots) for the specified runs.

17.5.18

Devhelp: information on available devices

General Form:
d e v h e l p [[ c s v ] d e v i c e _ n a m e [ p a r a m e t e r ] ]
Devhelp command shows the user information about the devices available in the simulator. If
called without arguments, it simply displays the list of available devices in the simulator. The
name of the device is the name used inside the simulator to access that device. If the user specifies a device name, then all the parameters of that device (model and instance parameters) will
be printed. Parameter description includes the internal ID of the parameter (id#), the name used
in the model card or on the instance line (Name), the direction (Dir) and the description of the
parameter (Description). All the fields are self-explanatory, except the direction. Direction
can be in, out or inout and corresponds to a write-only, read-only or a read/write
parameter. Read-only parameters can be read but not set, write only can be set but not read and
read/write can be both set and read by the user.
The -csv option prints the fields separated by a comma, for direct import into a spreadsheet.
This option is used to generate the simulator documentation.

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CHAPTER 17. INTERACTIVE INTERPRETER

Example:
devhelp
devhelp r e s i s t o r
devhelp c a p a c i t o r ic

17.5.19

Diff: Compare vectors

General Form:
d i f f p l o t 1 p l o t 2 [ vec . . . ]
Compare all the vectors in the specified plots, or only the named vectors if any are given. If
there are different vectors in the two plots, or any values in the vectors differ significantly,
the difference is reported. The variables diff_abstol, diff_reltol, and diff_vntol are used to
determine a significant difference.

17.5.20

Display: List known vectors and types

General Form:
d i s p l a y [ varname . . . ]
Prints a summary of currently defined vectors, or of the names specified. The vectors are sorted
by name unless the variable nosort is set. The information given is the name of the vector, the
length, the type of the vector, and whether it is real or complex data. Additionally, one vector
is labeled [scale]. When a command such as plot is given without a vs argument, this scale is
used for the X-axis. It is always the first vector in a rawfile, or the first vector defined in a new
plot. If you undefine the scale (i.e, let TIME = []), one of the remaining vectors becomes the
new scale (which one is unpredictable). You may set the scale to another vector of the plot with
the command setscale (17.5.60).

17.5.21

Echo: Print text

General Form:
e c h o [ t e x t . . . ] [ $ v a r i a b l e ] [ " $&v e c t o r " ]
Echos the given text, variable or vector to the screen. echo without parameters issues a blank
line.

17.5.22

Edit*: Edit the current circuit

General Form:
edit [ file ]
Print the current ngspice input file into a file, call up the editor on that file and allow the user to
modify it, and then read it back in, replacing the original file. If a file-name is given, then edit

17.5. COMMANDS

289

that file and load it, making the circuit the current one. The editor may be defined in .spiceinit
or spinit by a command line like
set editor=emacs
Using MS Windows, to allow the edit command calling an editor, you will have to add the
editors path to the PATH variable of the command prompt windows (see here). edit then calls
cmd.exe with e.g. notepad++ and file as parameter, if you have set
set editor=notepad++.exe
to .spiceinit or spinit.

17.5.23

Eprint*: Print an event driven node (only used with XSPICE option)

General Form:
e p r i n t node [ node ]
e p r i n t node [ node ] > n o d e o u t . t x t ; o u t p u t r e d i r e c t e d
Print an event driven node generated or used by an XSPICE A device. These nodes are vectors
not organized in plots. See chapt. 27.2.2 for an example. Output redirection into a file is
available.

17.5.24

FFT: fast Fourier transform of vectors

General Form:
f f t vector1 [ vector2 ] . . .
This analysis provides a fast Fourier transform of the input vector(s). fft is much faster than
spec (17.5.69) (about a factor of 50 to 100 for larger vectors) !
The fft command will create a new plot consisting of the Fourier transforms of the vectors given
on the command line. Each vector given should be a transient analysis result, i.e. it should
have time as a scale. You will have got these vectors by the tran Tstep Tstop Tstart
command.
The vector should have a linear equidistant time scale. Therefore linearization using the linearize
command is recommended before running fft. Be careful selecting a Tstep value small enough
for good interpolation, e.g. much smaller than any signal period to be resolved by fft (see
linearize command). The Fast Fourier Transform will be computed using a window function as given with the specwindow variable. Its code is based on the FFT function provided at
http://local.wasp.uwa.edu.au/~pbourke/other/dft/, downloaded April 5th, 2008, now to be found
here. A new plot named specx will be generated with a new vector (having the same name as
the input vector, see command above) containing the transformed data.

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CHAPTER 17. INTERACTIVE INTERPRETER

How to compute the fft from a transient simulation output:


ngspice
ngspice
ngspice
ngspice
ngspice

8 > s e t p l o t t r a n 1
9 > l i n e a r i z e V( 2 )
9 > s e t specwindow = b l a c k m a n
10 > f f t V( 2 )
11 > p l o t mag (V ( 2 ) )

Linearize will create a new vector V(2) in a new plot tran2. The command fft V(2) will
create a new plot spec1 with vector V(2) holding the resulting data.
The variables listed in the following table control operation of the fft command. Each can be
set with the set command before calling fft.
specwindow: This variable is set to one of the following strings, which will determine the
type of windowing used for the Fourier transform in the spec command. If not set, the default
is "hanning".
none No windowing
rectangular Rectangular window
bartlet Bartlett (also triangle) window
blackman Blackman window
hanning Hanning (also hann or cosine) window
hamming Hamming window
gaussian Gaussian window
flattop Flat top window

Figure 17.1: Spec and FFT window functions (Gaussian order = 4)

17.5. COMMANDS

291

specwindoworder: This can be set to an integer in the range 2-8. This sets the order when
the Gaussian window is used in the spec command. If not set, order 2 is used.

17.5.25

Fourier: Perform a Fourier transform

General Form:
f o u r i e r fundamental_frequency [ expression

...]

Fourier is used to analyse the output vector(s) of a preceeding transient analysis (see 17.5.77).
It does a Fourier analysis of each of the given values, using the first 10 multiples of the fundamental frequency (or the first nfreqs multiples, if that variable is set - see 17.7). The printed
output is like that of the .four ngspice line (chapter 15.5.4). The expressions may be any valid
expression (see 17.2), e.g. v(2). The evaluated expression values are interpolated onto a fixedspace grid with the number of points given by the fourgridsize variable, or 200 if it is not set.
The interpolation is of degree polydegree if that variable is set, or 1. If polydegree is 0, then no
interpolation is done. This is likely to give erroneous results if the time scale is not monotonic,
though.
The fourier command not only issues a printout, but also generates vectors, one per expression.
The size of the vector is 3 x nfreqs (per default 3 x 10). The name of the new vector is fouriermn,
where m is set by the mth call to the fourier command, n is the nth expression given in the actual
fourier command. fouriermn[0] is the vector of the 10 (nfreqs) frequency values, fouriermn[1]
contains the 10 (nfreqs) magnitude values, fouriermn[2] the 10 (nfreqs) phase values of the
result.
Example:
* do t h e t r a n s i e n t a n a l y s i s
t r a n 1 n 1m
* do t h e f o u r i e r a n a l y s i s
f o u r i e r 3 . 3 4 e6 v ( 2 ) v ( 3 ) ; f i r s t c a l l
f o u r i e r 100 e6 v ( 2 ) v ( 3 )
; second c a l l
g
e
t
i
n
d
i
v
i
d
u
a
l
v
a
l
u
e
s
*
l e t newt1 = f o u r i e r 1 1 [ 0 ] [ 1 ]
l e t newt2 = f o u r i e r 1 1 [ 1 ] [ 1 ]
l e t newt3 = f o u r i e r 1 1 [ 2 ] [ 1 ]
l e t newt4 = f o u r i e r 1 2 [ 0 ] [ 4 ]
l e t newt5 = f o u r i e r 1 2 [ 1 ] [ 4 ]
l e t newt6 = f o u r i e r 1 2 [ 2 ] [ 4 ]
* p l o t magnitude of seccond e x p r e s s i o n ( v ( 3 ) )
* from f i r s t c a l l v e r s u s f r e q u e n c y
p l o t f o u r i e r 1 2 [ 1 ] vs f o u r i e r 1 2 [ 0 ]
The plot command from the example plots the vector of the magnitude values, obtained by
the first call to fourier and evaluating the first expression in this call, against the vector of the
frequency values.

292

17.5.26

CHAPTER 17. INTERACTIVE INTERPRETER

Gnuplot: Graphics output via Gnuplot

General Form:
gnuplot f i l e plotargs
Like plot, but using gnuplot for graphics output and further data manipulation. ngspice creates
a file called file.plt containing the gnuplot command sequence, a file called file.data containing the data to be plotted, and a file called file.eps containing a postscript hard-copy of
the plot. On LINUX gnuplot is called via xterm, which offers a gnuplot console to manipulate
the data. On Windows a gnuplot command console window is opened as well as the plot window. Of course you have to have gnuplot installed properly on your system. This option will
work with Gnuplot version 4.2.6, not with version 4.4, but again with 4.5 (as of August 2011).
By setting the variable gnuplot_terminal inside the control section to png, gnuplot will
generate a file file.png containing a compressed bitmap ready to include in text-processing
programs like Word etc.

17.5.27

Hardcopy: Save a plot to a file for printing

General Form:
hardcopy f i l e p l o t a r g s
Just like plot, except that it creates a file called file containing the plot. The file is a postscript
image. As an alternative the plot(5) format is available by setting the hcopydevtype variable to
plot5, and can be printed by either the plot(1) program or lpr with the -g flag.

17.5.28

Help: Print summaries of Ngspice commands

Prints help. This help information, however, is spice3f5-like, stemming from 1991 and thus
is outdated. If commands are given, descriptions of those commands are printed. Otherwise
help for only a few major commands is printed. On Windows this help command is no longer
available. Spice3f5 compatible help may be found in the Spice 3 User manual. For ngspice
please use this manual.

17.5.29

History: Review previous commands

General Form:
h i s t o r y [ number ]
Print out the history, or the last number commands typed at the keyboard.

17.5.30

Inventory: Print circuit inventory

General Form:
inventory

17.5. COMMANDS

293

This commands accepts no argument and simply prints the number of instances of a particular
device in a loaded netlist.

17.5.31

Iplot*: Incremental plot

General Form:
i p l o t [ node . . . ]
Incrementally plot the values of the nodes while ngspice runs. The iplot command can be used
with the where command to find trouble spots in a transient simulation.
The @name[param] notation (31.1) might not work yet.

17.5.32

Jobs*: List active asynchronous ngspice runs

General Form:
jobs
Report on the asynchronous ngspice jobs currently running. Ngnutmeg checks to see if the
jobs are finished every time you execute a command. If it is done then the data is loaded and
becomes available.

17.5.33

Let: Assign a value to a vector

General Form:
l e t name = e x p r
Creates a new vector called name with the value specified by expr, an expression as described
above. If expr is [] (a zero-length vector) then the vector becomes undefined. Individual elements of a vector may be modified by appending a subscript to name (ex. name[0]). If there are
no arguments, let is the same as display.
The command let creates a vector in the current plot, use setplot (17.5.59) to create a new plot.
See also unlet (17.5.81), compose (17.5.12).

17.5.34

Linearize*: Interpolate to a linear scale

General Form:
l i n e a r i z e vec . . .
Create a new plot with all of the vectors in the current plot, or only those mentioned as arguments to the command, all data linearized onto an equidistant time scale.

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CHAPTER 17. INTERACTIVE INTERPRETER

How to compute the fft from a transient simulation output:


ngspice
ngspice
ngspice
ngspice
ngspice

8 > s e t p l o t t r a n 1
9 > l i n e a r i z e V( 2 )
9 > s e t specwindow = b l a c k m a n
10 > f f t V( 2 )
11 > p l o t mag (V ( 2 ) ) t s t e p

Linearize will redo the vectors vec or renew all vectors of the current plot (e.g. tran3) if no
arguments are given and store them into a new plot (e.g. tran4). The new vectors are interpolated
onto a linear time scale, which is determined by the values of tstep, tstart, and tstop in
the currently active transient analysis. The currently loaded input file must include a transient
analysis (a tran command may be run interactively before the last reset, alternately), and the
current plot must be from this transient analysis. The length of the new vector is (tstop
- tstart) / tstep + 1.5. This command is needed for example if you want to do a fft
analysis (17.5.24). Please note that the parameter tstep of your transient analysis (see chapter
15.3.9) has to be small enough to get adequate resolution, otherwise the command linearize
will do sub-sampling of your signal.

17.5.35

Listing*: Print a listing of the current circuit

General Form:
l i s t i n g [ l o g i c a l ] [ p h y s i c a l ] [ d e c k ] [ e x p a n d ] [ param ]
If the logical argument is given, the listing is with all continuation lines collapsed into one line,
and if the physical argument is given the lines are printed out as they were found in the file. The
default is logical. A deck listing is just like the physical listing, except without the line numbers
it recreates the input file verbatim (except that it does not preserve case). If the word expand is
present, the circuit is printed with all subcircuits expanded. The option param allows to print
all parameters and their actual values.

17.5.36

Load: Load rawfile data

General Form:
load [ filename ] . . .
Loads either binary or ascii format rawfile data from the files named. The default file-name is
rawspice.raw, or the argument to the -r flag if there was one.

17.5.37

Meas*: Measurements on simulation data

General Form (example):


MEAS {DC | AC | TRAN | SP} r e s u l t TRIG t r i g _ v a r i a b l e VAL= v a l <TD= t d >
<CROSS=# | CROSS=LAST> <RISE = # | RISE=LAST> <FALL = # | FALL=LAST>
<TRIG AT= t i m e > TARG t a r g _ v a r i a b l e VAL= v a l <TD= t d > <CROSS=# | CROSS=LAST>
<RISE = # | RISE=LAST> <FALL = # | FALL=LAST> <TRIG AT= t i m e >

17.5. COMMANDS

295

Most of the input forms found in 15.4 may be used here with the command meas instead of
.meas(ure). Using meas inside the .control ... .endc section offers additional features compared to the .meas use. meas will print the results as usual, but in addition will store its measurement result (typically the token result given in the command line) in a vector. This vector
may be used in following command lines of the script as an input value of another command.
For details of the command see chapt. 15.4. The measurement type SP is only available here,
because a fft command will prepare the data for SP measurement. Option autostop (15.1.4)
is not available.
Unfortunately par(expression) (15.5.6) will not work here, i.e. inside the .control section.
You may use an expression by the let command instead, giving let vec_new = expression.
Replacement for par(expression) in meas inside the .control section
l e t v d i f f = v ( n1)v ( n0 )
meas t r a n v t e s t f i n d v d i f f a t = 0 . 0 4 e3
* t h e f o l l o w i n g w i l l n o t do h e r e :
* meas t r a n v t e s t f i n d p a r ( v ( n1)v ( n0 ) ) a t = 0 . 0 4 e3

17.5.38

Mdump*: Dump the matrix values to a file (or to console)

General Form:
mdump < f i l e n a m e >
If <filename> is given, the output will be stored in file <filename>, otherwise dumped to
your console.

17.5.39

Mrdump*: Dump the matrix right hand side values to a file (or
to console)

General Form:
mrdump < f i l e n a m e >
If <filename> is given, the output will be appended to file <filename>, otherwise dumped to
your console.
Example usage after ngspice has started:
* Dump m a t r i x and RHS v a l u e s a f t e r 10 and 20 s t e p s
* of a t r a n s i e n t s i m u l a t i o n
source rc . c i r
s t e p 10
mdump m1 . t x t
mrdump mr1 . t x t
s t e p 10
mdump m2 . t x t
mrdump mr2 . t x t
* j u s t t o c o n t i n u e t o t h e end
s t e p 10000

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CHAPTER 17. INTERACTIVE INTERPRETER

You may create a loop using the control structures (chapt. 17.6).

17.5.40

Noise*: Noise analysis

See the .NOISE analysis (15.3.4) for details.


The noise command will generate two plots (typically named noise1 and noise2) with Noise
Spectral Density Curves and Integrated Noise data. To write these data into output file(s), you
may use the following command sequence:
Command sequence for writing noise data to file(s):
. control
t r a n 1 e6 1 e3
w r i t e t e s t _ t r a n . raw
n o i s e V( o u t ) v i n p d e c 333 1 1 e8 16
print inoise_total onoise_total
* f i r s t o p t i o n t o g e t a l l o f t h e o u t p u t ( two f i l e s )
s e t p l o t noise1
w r i t e t e s t _ n o i s e 1 . raw a l l
s e t p l o t noise2
w r i t e t e s t _ n o i s e 2 . raw a l l
* s e c o n d o p t i o n ( a l l i n one raw f i l e )
w r i t e t e s t a l l . raw n o i s e 1 . a l l n o i s e 2 . a l l
. endc

17.5.41

Op*: Perform an operating point analysis

General Form:
op
Do an operating point analysis. See chapter 15.3.5 for more details.

17.5.42

Option*: Set a ngspice option

General Form:
option [ option=val ] [ option=val ] . . .
Set any of the simulator variables as listed in chapt. 15.1. See this chapter also for more
information on the available options. The option command without any argument lists the
actual options set in the simulator (to be verified). Multiple options may be set in a single line.
The following example demonstrates a control section, which may be added to your circuit file
to test the influence of variable trtol on the number of iterations and on the simulation time.

17.5. COMMANDS

297

Command sequence for testing option trtol:


. control
set noinit
o p t i o n t r t o l =1
echo
e c h o t r t o l =1
run
rusage t r a n i t e r trantime
reset
o p t i o n t r t o l =3
echo
e c h o t r t o l =3
run
rusage t r a n i t e r trantime
reset
o p t i o n t r t o l =5
echo
e c h o t r t o l =5
run
rusage t r a n i t e r trantime
reset
o p t i o n t r t o l =7
echo
e c h o t r t o l =7
run
rusage t r a n i t e r trantime
p l o t t r a n 1 . v ( out25 ) t r a n 1 . v ( out50 ) v ( out25 )
. endc

17.5.43

v ( out50 )

Plot: Plot values on the display

General Form:
p l ot exprs [ y l i m i t ylo yhi ] [ x l i m i t xlo xhi ] [ xindices x i l o x i h i ]
[ x c o m p r e s s comp ] [ x d e l t a x d e l ] [ y d e l t a y d e l ] [ x l o g ] [ y l o g ] [ l o g l o g ]
[ v s xname ] [ x l a b e l word ] [ y l a b e l word ] [ t i t l e word ] [ samep ]
[ linear ]
Plot the given vectors or exprs on the screen (if you are on a graphics terminal). The xlimit
and ylimit arguments determine the high and low x- and y-limits of the axes, respectively. The
xindices arguments determine what range of points are to be plotted - everything between the
xiloth point and the xihith point is plotted. The xcompress argument specifies that only one
out of every comp points should be plotted. If an xdelta or a ydelta parameter is present, it
specifies the spacing between grid lines on the X- and Y-axis. These parameter names may be
abbreviated to xl, yl, xind, xcomp, xdel, and ydel respectively.
The xname argument is an expression to use as the scale on the x-axis. If xlog or ylog are
present then the X or Y scale, respectively, is logarithmic (loglog is the same as specifying

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both). The xlabel and ylabel arguments cause the specified labels to be used for the X and Y
axes, respectively.
If samep is given, the values of the other parameters (other than xname) from the previous plot,
hardcopy, or asciiplot command is used unless re-defined on the command line.
The title argument is used in the place of the plot name at the bottom of the graph.
The linear keyword is used to override a default logscale plot (as in the output for an AC analysis).
Finally, the keyword polar generates a polar plot. To produce a smith plot, use the keyword
smith. Note that the data is transformed, so for smith plots you will see the data transformed
by the function (x-1)/(x+1). To produce a polar plot with a smith grid but without performing
the smith transform, use the keyword smithgrid.
If you specify plot all, all vectors (including the scale vector) are plotted versus the scale
vector (see commands display (17.5.20) or setscale (17.5.60) on viewing the vectors of the
current plot). The command plot ally will not plot the scale vector, but all other real y
values. The command plot alli will yield all current vectors, the command plot allv all
voltage vectors.
If the vector name to be plotted contains -, or / or other tokens which may be taken for operators of an expression, and plotting fails, try enclosing the name in double quotes, e.g. plot
/vout.
Plotting of complex vectors, as may occur after an ac simulation, require some special considerations. Please see chapter 17.5.1 for details.

17.5.44

Pre_<command>: execute commands prior to parsing the circuit

General Form:
p r e _ <command>
All commands in a .control ... .endc section are executed after the circuit has been parsed. If you
need command execution before circuit parsing, you may add these commands to the general
spinit or local .spiceinit files. Another possibility is adding a leading pre_ to a command within
the .control section of an ordinary input file, which forces the command to be executed before
circuit parsing. Basically <command> may be any command listed in chapter 17.5, however
only a few commands are indeed useful here. Some examples are given below:
Examples:
p r e _ u n s e t ngdebug
pre_set strict_errorhandling
p r e _ c o d e m o d e l mymod . cm
pre_<command> is available only in the .control mode (see 16.4.3), not in interactive mode,
where the user may determine herself when a circuit is to be parsed, using the source command
(17.5.68) .

17.5. COMMANDS

17.5.45

299

Print: Print values

General Form:
p r i n t [ col ] [ l i n e ] expr . . .
Prints the vector(s) described by the expression expr. If the col argument is present, print the
vectors named side by side. If line is given, the vectors are printed horizontally. col is the
default, unless all the vectors named have a length of one, in which case line is the default.
The options width, length, and nobreak are effective for this command (see asciiplot). If the
expression is all, all of the vectors available are printed. Thus print col all > file prints everything
in the file in SPICE2 format. The scale vector (time, frequency) is always in the first column
unless the variable noprintscale is true. You may use the vectors alli, allv, ally with the print
command, but then the scale vector will not be printed.
Examples:
s e t w i d t h =300
print all
s e t l e n g t h =500

17.5.46

Quit: Leave Ngspice or Nutmeg

General Form:
quit
quit [ exitcode ]
Quit ngnutmeg or ngspice. Ngspice will ask for an acknowledgment if parameters have not
been saved. If set noaskquit is specified, ngspice will terminate immediately.
The optional parameter exitcode is an integer which set the exit code for ngspice, useful to
return a success/fail value to the operating system.

17.5.47

Rehash: Reset internal hash tables

General Form:
rehash
Recalculate the internal hash tables used when looking up UNIX commands, and make all
UNIX commands in the users PATH available for command completion. This is useless unless
you have set unixcom first (see above).

17.5.48

Remcirc*: Remove the current circuit

General Form:
remcirc

300

CHAPTER 17. INTERACTIVE INTERPRETER

This command removes the current circuit from the list of circuits sourced into ngspice. To
select a specific circuit, use setcirc (17.5.58). To load another circuit, refer to source (17.5.68).
The new actual circuit will be the circuit on top of the list of the remaining circuits.

17.5.49

Reset*: Reset an analysis

General Form:
reset
Throw out any intermediate data in the circuit (e.g, after a breakpoint or after one or more
analyses have been done already), and re-parse the input file. The circuit can then be re-run
from its initial state, overriding the affect of any set or alter commands.
Reset may be required in simulation loops preceding any run (or tran ...) command.

17.5.50

Reshape: Alter the dimensionality or dimensions of a vector

General Form:
reshape vector vector
or
reshape vector vector
or
reshape vector vector

...
. . . [ dimension , dimension ,

... ]

. . . [ dimension ] [ dimension ] . . .

This command changes the dimensions of a vector or a set of vectors. The final dimension
may be left off and it will be filled in automatically. If no dimensions are specified, then the
dimensions of the first vector are copied to the other vectors. An error message of the form
dimensions of x were inconsistent can be ignored.
Example:
* g e n e r a t e v e c t o r with a l l ( here 30) elements
l e t newvec= v e c t o r ( 3 0 )
* r e s h a p e v e c t o r t o f o r m a t 3 x 10
r e s h a p e newvec [ 3 ] [ 1 0 ]
* access elements of the reshaped vector
p r i n t newvec [ 0 ] [ 9 ]
p r i n t newvec [ 1 ] [ 5 ]
l e t newt = newvec [ 2 ] [ 4 ]

17.5.51

Resume*: Continue a simulation after a stop

General Form:
resume
Resume a simulation after a stop or interruption (control-C).

17.5. COMMANDS

17.5.52

301

Rspice*: Remote ngspice submission

General Form:
rspice input f i l e
Runs a ngspice remotely taking the input file as a ngspice input file, or the current circuit if no
argument is given. Ngnutmeg or ngspice waits for the job to complete, and passes output from
the remote job to the users standard output. When the job is finished the data is loaded in as
with aspice. If the variable rhost is set, ngnutmeg connects to this host instead of the default
remote ngspice server machine. This command uses the rsh command and thereby requires
authentication via a .rhosts file or other equivalent method. Note that rsh refers to the
remote shell program, which may be remsh on your system; to override the default name
of rsh, set the variable remote_shell. If the variable rprogram is set, then rspice uses this
as the pathname to the program to run on the remote system.
Note: rspice will not acknowledge elements that have been changed via the alter or altermod
commands.

17.5.53

Run*: Run analysis from the input file

General Form:
run [ r a w f i l e ]
Run the simulation as specified in the input file. If there were any of the control lines .ac, .op,
.tran, or .dc, they are executed. The output is put in rawfile if it was given, in addition to being
available interactively.

17.5.54

Rusage: Resource usage

General Form:
rusage [ resource

...]

Print resource usage statistics. If any resources are given, just print the usage of that resource.
Most resources require that a circuit be loaded. Currently valid resources are:
decklineno Number of lines in deck
netloadtime Nelist loading time
netparsetime Netlist parsing time
elapsed The amount of time elapsed since the last rusage elapsed call.
faults Number of page faults and context switches (BSD only).
space Data space used.
time CPU time used so far.

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CHAPTER 17. INTERACTIVE INTERPRETER

temp Operating temperature.


tnom Temperature at which device parameters were measured.
equations Circuit Equations
time Total Analysis Time
totiter Total iterations
accept Accepted time-points
rejected Rejected time-points
loadtime Time spent loading the circuit matrix and RHS.
reordertime Matrix reordering time
lutime L-U decomposition time
solvetime Matrix solve time
trantime Transient analysis time
tranpoints Transient time-points
traniter Transient iterations
trancuriters Transient iterations for the last time point*
tranlutime Transient L-U decomposition time
transolvetime Transient matrix solve time
everything All of the above.
* listed incorrectly as "Transient iterations per point".

17.5.55

Save*: Save a set of outputs

General Form:
save [ a l l

| outvec . . . ]

Save a set of outputs, discarding the rest (if not keyword all is given). Maybe used to dramatically reduce memory (RAM) requirements if only a few useful node voltages or branch currents
are saved.
Node voltages may be saved by giving the nodename or v(nodename). Currents through an
independent voltage source are given by i(sourcename) or sourcename#branch. Internal device
data (31.1) are accepted as @dev[param]. The syntax is identical to the .save command (15.5.1).
Note: In the .control ....
mand to become effective.

.endc section save must occur before the run or tran com-

17.5. COMMANDS

303

If a node has been mentioned in a save command, it appears in the working plot after a run has
completed, or in the rawfile written by the write (17.5.86) command. For backward compatibility, if there are no save commands given, all outputs are saved. If you want to trace (17.5.76) or
plot (17.5.43) a node, you have to save it explicitly, except for all given or no save command
at all.
When the keyword all appears in the save command, all node voltages, voltage source currents
and inductor currents are saved in addition to any other vectors listed.
Save voltage and current:
s a v e vd_node v s # b r a n c h v ( v s _ n o d e ) i ( v s 2 )
Save allows to store and later access internal device parameters. e.g. in a command like
Save internal parameters:
s a v e a l l @mn1[ gm ]
which saves all standard analysis output data plus gm of transistor mn1 to the internal memory
(see also 31.1).
save may store data from nodes or devices residing inside of a subcircuit:
Save voltage on node 3 (top level), node 8 (from inside subcircuit x2) and current through vmeas
(from subcircuit x1):
s a v e 3 x1 . x2 . x1 . x2 . 8 v . x1 . x1 . x1 . vmeas # b r a n c h
Save internal parameters within subcircuit:
s a v e @m. xmos3 . mn1 [ gm ]
Use commands listing expand (17.5.35, before the simulation) or display (17.5.20, after
simulation) to obtain a list of all nodes and currents available. Please see chapter 31 for an
explanation of the syntax for internal parameters.
Entering several save lines in a single .control section will accumulate the nodes and parameters
to be saved. If you want to exclude a node, you have to get its number by calling status
(17.5.70) and then calling delete number (17.5.16).

17.5.56

Sens*: Run a sensitivity analysis

General Form:
sens output_variable
s e n s o u t p u t _ v a r i a b l e a c ( DEC | OCT | LIN ) N F s t a r t F s t o p
Perform a Sensitivity analysis. output_variable is either a node voltage (ex. v(1) or
v(A,out)) or a current through a voltage source (ex. i(vtest)). The first form calculates
DC sensitivities, the second form calculates AC sensitivities. The output values are in dimensions of change in output per unit change of input (as opposed to percent change in output or
per percent change of input).

304

17.5.57

CHAPTER 17. INTERACTIVE INTERPRETER

Set: Set the value of a variable

General Form:
s e t [ word ]
s e t [ word = v a l u e ] . . .
Set the value of word to be value, if it is present. You can set any word to be any value, numeric
or string. If no value is given then the value is the Boolean true. If you enter a string containing
spaces, you have to enclose it with double quotes.
The value of word may be inserted into a command by writing $word. If a variable is set to
a list of values that are enclosed in parentheses (which must be separated from their values by
white space), the value of the variable is the list.
The variables used by ngspice are listed in section 17.7.
Set entered without any parameter will list all variables set, and their values, if applicable.

17.5.58

Setcirc*: Change the current circuit

General Form:
s e t c i r c [ c i r c u i t name ]
The current circuit is the one that is used for the simulation commands below. When a circuit
is loaded with the source command (see below, 17.5.68) it becomes the current circuit.
Setcirc followed by return without any parameter will list all circuits loaded.

17.5.59

Setplot: Switch the current set of vectors

General Form:
s e t p l o t [ plotname ]
Set the current plot to the plot with the given name, or if no name is given, prompt the user
with a menu. (Note that the plots are named as they are loaded, with names like tran1 or op2.
These names are shown by the setplot and display commands and are used by diff, below.) If
the New plot item is selected, the current plot becomes one with no vectors defined.
Note that here the word plot refers to a group of vectors that are the result of one ngspice run.
When more than one file is loaded in, or more than one plot is present in one file, ngspice keeps
them separate and only shows you the vectors in the current plot.

17.5.60

Setscale: Set the scale vector for the current plot

General Form:
setscale [ vector ]
Defines the scale vector for the current plot. If no argument is given, the current scale vector is
printed. The scale vector delivers the values for the x-axis in a 2D plot.

17.5. COMMANDS

17.5.61

305

Settype: Set the type of a vector

General Form:
settype type vector

...

Change the type of the named vectors to type. Type names can be found in the following table.
Type
notype
time
frequency
voltage
current
onoise-spectrum
onoise-integrated
inoise-spectrum
inoise-integrated

17.5.62

Unit
s
Hz
V
A
(V or A)^2/Hz
V or A
(V or A)^2/Hz
V or A

Type
pole
zero
s-param
temp-sweep
res-sweep
impedance
admittance
power
phase
decibel

Unit

Celsius
Ohms
Ohms
Mhos
W
Degree
dB

Shell: Call the command interpreter

General Form:
s h e l l [ command ]
Call the operating systems command interpreter; execute the specified command or call for
interactive use.

17.5.63

Shift: Alter a list variable

General Form:
s h i f t [ varname ] [ number ]
If varname is the name of a list variable, it is shifted to the left by number elements (i.e, the
number leftmost elements are removed). The default varname is argv, and the default number
is 1.

17.5.64

Show*: List device state

General Form:
show d e v i c e s [ : p a r a m e t e r s ] , . . .
The show command prints out tables summarizing the operating condition of selected devices.
If devices is missing, a default set of devices are listed, if devices is a single letter, devices
of that type are listed. A devices full name may be specified to list only that device. Finally,
devices may be selected by model by using the form #modelname.

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CHAPTER 17. INTERACTIVE INTERPRETER

If no parameters are specified, the values for a standard set of parameters are listed. If the list of
parameters contains a +, the default set of parameters is listed along with any other specified
parameters.
For both devices and parameters, the word all has the obvious meaning.
Note: there must be spaces separating the : that divides the device list from the parameter list.

17.5.65

Showmod*: List model parameter values

General Form:
showmod m o d e l s [ : p a r a m e t e r s ] , . . .
The showmod command operates like the show command (above) but prints out model parameter values. The applicable forms for models are a single letter specifying the device type letter
(e.g. m, or c), a device name (e.g. m.xbuf22.m4b), or #modelname (e.g. #p1).

17.5.66

Snload*: Load the snapshot file

General Form:
snload c i r c u i t f i l e

file

snload reads the snapshot file generated by snsave (17.5.67). circuit-file is the original circuit
input file. After reading the simulation may be continued by resume (17.5.51).
An input script for loading circuit and intermediate data, resuming simulation and plotting is
shown below:
Typical usage:
* SCRIPT : ADDER 4 BIT BINARY
* s c r i p t t o r e l o a d c i r c u i t and c o n t i n u e t h e s i m u l a t i o n
* begin with e d i t i n g the f i l e l o c a t i o n
* t o be s t a r t e d w i t h n g s p i c e a d d e r _ s n l o a d . s c r i p t
. control
* cd t o where a l l f i l e s a r e l o c a t e d
cd D : \ S p i c e _ g e n e r a l \ n g s p i c e \ e x a m p l e s \ s n a p s h o t
* l o a d c i r c u i t and s n p a s h o t f i l e
snload adder_mos_circ . c i r adder500 . snap
* continue simulation
resume
* p l o t some node v o l t a g e s
plot v (10) v (11) v (12)
. endc
Due to bug we currently need the term script in the title line (first line) of the script.

17.5. COMMANDS

17.5.67

307

Snsave*: Save a snapshot file

General Form:
snsave f i l e
If you run a transient simulation and interrupt it by e.g. a stop breakpoint (17.5.72), you may
resume simulation immediately (17.5.51) or store the intermediate status in a snapshot file by
snsave for resuming simulation later (using snload (17.5.66)), even with a new instance of
ngspice.
Typical usage:
Example i n p u t f i l e f o r s n s a v e
* l o a d a c i r c u i t ( i n c l u d i n g t r a n s i s t o r m o d e l s and . t r a n command )
* s t a r t s t r a n s i e n t simulation u n t i l stop point
* store intermediate data to f i l e
* begin with e d i t i n g the f i l e l o c a t i o n
* t o be r u n w i t h n g s p i c e a d d e r _ m o s . c i r
. include adder_mos_circ . c i r
. control
* cd t o where a l l f i l e s a r e l o c a t e d
cd D : \ S p i c e _ g e n e r a l \ n g s p i c e \ e x a m p l e s \ s n a p s h o t
set noaskquit
set noinit
* i n t e r r u p t condition for the simulation
s t o p when t i m e > 500 n
* simulate
run
* store snapshot to f i l e
snsave adder500 . snap
quit
. endc
. END
adder_mos_circ.cir is a circuit input file, including the netlist, .model and .tran statements.
Unfortunately snsave/snload will not work if you have XSPICE devices (or V/I sources with
polynomial statement) in your input deck.

17.5.68

Source: Read a ngspice input file

General Form:
source i n f i l e
For ngspice: read the ngspice input file infile, containing a circuit netlist. Ngnutmeg and ngspice
commands may be included in the file, and must be enclosed between the lines .control and

308

CHAPTER 17. INTERACTIVE INTERPRETER

.endc. These commands are executed immediately after the circuit is loaded, so a control
line of ac ... works the same as the corresponding .ac card. The first line in any input file
is considered a title line and not parsed but kept as the name of the circuit. Thus, a ngspice
command script in infile must begin with a blank line and then with a .control line. Also, any
line starting with the characters *# is considered as a control line (.control and .endc is placed
around this line automatically.). The exception to these rules are the files spinit (16.5) and
.spiceinit (16.6).
For ngutmeg: reads commands from the file infile. Lines beginning with the character * are
considered comments and are ignored.

17.5.69

Spec: Create a frequency domain plot

General Form:
spec s t a r t _ f r e q s t o p _ f r e q s t e p _ f r e q vector [ vector

...]

Calculates a new complex vector containing the Fourier transform of the input vector (typically
the linearized result of a transient analysis). The default behavior is to use a Hanning window,
but this can be changed by setting the variables specwindow and specwindoworder appropriately.
Typical usage:
ngspice
ngspice
ngspice
ngspice

13
14
15
16

>
>
>
>

linearize
s e t specwindow = " b l a c k m a n "
s p e c 10 1000000 1000 v ( o u t )
p l o t mag ( v ( o u t ) )

Possible values for specwindow are: none, hanning, cosine, rectangular, hamming, triangle,
bartlet, blackman, gaussian and flattop. In the case of a gaussian window specwindoworder is a
number specifying its order. For a list of window functions see 17.5.24.

17.5.70

Status*: Display breakpoint information

General Form:
status
Display all of the saved nodes and parameters, traces and breakpoints currently in effect.

17.5.71

Step*: Run a fixed number of time-points

General Form:
s t e p [ number ]
Iterate number times, or once, and then stop.

17.5. COMMANDS

17.5.72

309

Stop*: Set a breakpoint

General Form:
s t o p [ a f t e r n ] [ when v a l u e cond v a l u e ] . . .
Set a breakpoint. The argument after n means stop after iteration number n, and the argument
when value cond value means stop when the first value is in the given relation with the
second value, the possible relations being
Symbol
=
<>
>
<
>=
<=

Alias
eq
ne
gt
lt
ge
le

Meaning
equal to
not equal
greater than
less than
greater than or equal to
less than or equal to

Symbol or alias may be used alternatively. All stop commands have to be given in the control
flow before the run command. The values above may be node names in the running circuit, or
real values. If more than one condition is given, e.g.
stop after 4 when v(1) > 4 when v(2) < 2,
the conjunction of the conditions is implied. If the condition is met, the simulation and control
flow are interrupted, and ngspice waits for user input.
In a transient simulation the = or eq will only work with vector time in commands like
stop when time = 200n.
Internally a breakpoint will be set at the time requested. Multiple breakpoints may be set. If
the first stop condition is met, the simulation is interrupted, the commands following run or
tran (e.g. alter or altermod) are executed, then the simulation may continue at the first resume
command. The next breakpoint requires another resume to continue automatically. Otherwise
the simulation stops and ngspice waits for user input.
If you try to stop at
stop when V(1) eq 1
(or similar) during a transient simulation, you probably will miss this point, because it is not
very likely that at any time step the vector v(1) will have the exact value of 1. Then ngspice
simply will not stop.

17.5.73

Strcmp: Compare two strings

General Form:
strcmp _flag $ s t r i n g 1 " s t r i n g 2 "
The command compares two strings, either given by a variable (string1) or as a string in quotes
(string2). _flag is set as an output variable to 0, if both strings are equal. A value greater
than zero indicates that the first character that does not match has a greater value in str1 than in
str2; and a value less than zero indicates the opposite (like the C strcmp function).

310

CHAPTER 17. INTERACTIVE INTERPRETER

17.5.74

Sysinfo*: Print system information

General Form:
sysinfo
The command prints system information useful for sending bug report to developers. Information consists of:
Name of the operating system,
CPU type,
Number of physical processors (not available under Windows OS), number of logical
processors,
Total amount of DRAM available,
DRAM currently available.
The example below shows the use of this command.
n g s p i c e 1 > s y s i n f o
OS : CYGWIN_NT5.1 1 . 5 . 2 5 ( 0 . 1 5 6 / 4 / 2 ) 20080612 1 9 : 3 4
CPU : I n t e l (R) P e n t i u m (R) 4 CPU 3 . 4 0 GHz
Logical processors : 2
T o t a l DRAM a v a i l a b l e = 1 5 3 5 . 4 8 0 4 6 9 MB.
DRAM c u r r e n t l y a v a i l a b l e = 9 8 4 . 6 8 3 5 9 4 MB.
n g s p i c e 2 >
This command has been tested under Windows OS and LINUX. It may not be available in your
operating system environment.

17.5.75

Tf*: Run a Transfer Function analysis

General Form:
t f output_node input_source
The tf command performs a transfer function analysis, returning:
the transfer function (output/input),
output resistance,
and input resistance
between the given output node and the given input source. The analysis assumes a small-signal
DC (slowly varying) input. The following example file

17.5. COMMANDS

311

Example input file:


* Tf t e s t
vs
1
r1
1
r2
2
r3
3
r4
2

circuit
0
dc 5
2
100
3
50
0
150
0
200

. control
t f v ( 3 , 5 ) vs
print all
. endc
. end
will yield the following output:
transfer_function = 3.750000e-001
output_impedance_at_v(3,5) = 6.662500e+001
vs#input_impedance = 2.000000e+002

17.5.76

Trace*: Trace nodes

General Form:
t r a c e [ node . . . ]
For every step of an analysis, the value of the node is printed. Several traces may be active at
once. Tracing is not applicable for all analyses. To remove a trace, use the delete (17.5.16)
command.

17.5.77

Tran*: Perform a transient analysis

General Form:
t r a n T s t e p T s t o p [ T s t a r t [ Tmax ] ] [ UIC ]
Perform a transient analysis. See chapter 15.3.9 of this manual for more details.
An interactive transient analysis may be interrupted by issuing a ctrl-c (control-C) command.
The analysis then can be resumed by the resume command (17.5.51). Several options may be
set to control the simulation (15.1.4).

17.5.78

Transpose: Swap the elements in a multi-dimensional data set

General Form:
transpose vector vector

...

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CHAPTER 17. INTERACTIVE INTERPRETER

This command transposes a multidimensional vector. No analysis in ngspice produces multidimensional vectors, although the DC transfer curve may be run with two varying sources.
You must use the reshape command to reform the one-dimensional vectors into two dimensional vectors. In addition, the default scale is incorrect for plotting. You must plot versus the
vector corresponding to the second source, but you must also refer only to the first segment of
this second source vector. For example (circuit to produce the transfer characteristic of a MOS
transistor):
How to produce the transfer characteristic of a MOS transistor:
ngspice
ngspice
ngspice
ngspice
ngspice

>
>
>
>
>

dc vgg 0 5 1 vdd 0 5 1
p l o t i ( vdd )
reshape a l l [6 ,6]
t r a n s p o s e i ( vdd ) v ( d r a i n )
p l o t i ( vdd ) v s v ( d r a i n ) [ 0 ]

17.5.79

Unalias: Retract an alias

General Form:
u n a l i a s [ word . . . ]
Removes any aliases present for the words.

17.5.80

Undefine: Retract a definition

General Form:
undefine function
Definitions for the named user-defined functions are deleted.

17.5.81

Unlet: Delete the specified vector(s)

General Form:
unlet vector [ vector

... ]

Delete the specified vector(s). See also let (17.5.33).

17.5.82

Unset: Clear a variable

General Form:
u n s e t [ word . . . ]
Clear the value of the specified variable(s) (word).

17.5. COMMANDS

17.5.83

313

Version: Print the version of ngspice

General Form:
v e r s i o n [ s | f | < v e r s i o n i d > ]
Print out the version of ngnutmeg that is running, if invoked without argument or with -s or -f.
If the argument is a <version id> (any string different from -s or -f is considered a <version id>
), the command checks to make sure that the arguments match the current version of ngspice.
(This is mainly used as a Command: line in rawfiles.)
Options description:
No option: The output of the command is the message you can see when running ngspice
from the command line, no more no less.
-s(hort): A shorter version of the message you see when calling ngspice from the command line.
-f(ull): You may want to use this option if you want to know what extensions are included
into the simulator and what compilation switches are active. A list of compilation options
and included extensions is appended to the normal (not short) message. May be useful
when sending bug reports.
The following example shows what the command returns is some situations:
Use of the version command:
n g s p i c e 10 > v e r s i o n
******
** n g s p i c e 24 : C i r c u i t l e v e l s i m u l a t i o n p r o g r a m
** The U . C . B e r k e l e y CAD Group
** C o p y r i g h t 1985 1994 , R e g e n t s o f t h e U n i v e r s i t y o f C a l i f o r n i a .
** P l e a s e g e t y o u r n g s p i c e manual from
h t t p : / / ngspice . s o u r c e f o r g e . net / docs . html
** P l e a s e f i l e y o u r bugr e p o r t s a t
h t t p : / / ngspice . s o u r c e f o r g e . net / bugrep . html
13:36:34
** C r e a t i o n D a t e : J a n 1 2011
******
n g s p i c e 2 >
n g s p i c e 11 > v e r s i o n 14
Note : r a w f i l e i s v e r s i o n 14 ( c u r r e n t v e r s i o n i s 2 4 )
n g s p i c e 12 > v e r s i o n 24
n g s p i c e 13 >
Note for developers: The option listing returned when version is called with the
-f flag is built at compile time using #ifdef blocks. When new compile switches
are added, if you want them to appear on the list, you have to modify the code in
misccoms.c.

314

17.5.84

CHAPTER 17. INTERACTIVE INTERPRETER

Where*: Identify troublesome node or device

General Form:
where
When performing a transient or operating point analysis, the name of the last node or device to
cause non-convergence is saved. The where command prints out this information so that you
can examine the circuit and either correct the problem or make a bug report. You may do this
either in the middle of a run or after the simulator has given up on the analysis. For transient
simulation, the iplot command can be used to monitor the progress of the analysis. When the
analysis slows down severely or hangs, interrupt the simulator (with control-C) and issue the
where command. Note that only one node or device is printed; there may be problems with
more than one node.

17.5.85

Wrdata: Write data to a file (simple table)

General Form:
wrdata [ f i l e ] [ vecs ]
Writes out the vectors to file.
This is a very simple printout of data in array form. Column one is the default scale data, column
two the simulated data. If more than one vector is given, the third column again is the default
scale, the fourth the data of the second vector. The default format is ASCII. All vectors have to
stem from the same plot, otherwise a seg fault may occur. No further information is written to
the file, so you have to keep track of your multiple outputs. The format may be changed in the
near future.
output example from two vectors:
0.000000 e +000
7.629471 e +006
1.525894 e +007
2.288841 e +007
3.051788 e +007
3.814735 e +007
4.577682 e +007
5.340630 e +007
6.103577 e +007
6.866524 e +007
....

-1.845890 e -006
4.243518 e -006
-5.794628 e -006
5.086875 e -006
-3.683623 e -006
1.330798 e -006
-3.804620 e -007
9.047444 e -007
-2.792511 e -006
5.657498 e -006

0.000000 e +000
7.629471 e +006
1.525894 e +007
2.288841 e +007
3.051788 e +007
3.814735 e +007
4.577682 e +007
5.340630 e +007
6.103577 e +007
6.866524 e +007

0.000000 e +000
-4.930171 e -006
4.769020 e -006
-3.670687 e -006
1.754215 e -006
-1.091843 e -006
2.274678 e -006
-3.815083 e -006
4.766727 e -006
-2.397679 e -006

If variable appendwrite is set, the data may be added to an existing file.

17.5.86

Write: Write data to a file (Spice3f5 format)

General Form:
write [ f i l e ] [ exprs ]

17.5. COMMANDS

315

Writes out the expressions to file.


First vectors are grouped together by plots, and written out as such (i.e, if the expression list
contained three vectors from one plot and two from another, then two plots are written, one
with three vectors and one with two). Additionally, if the scale for a vector isnt present, it is
automatically written out as well.
The default format is a compact binary, but this can be changed to ASCII with the set filetype=ascii command. The default file name is rawspice.raw, or the argument to the -r flag
on the command line, if there was one, and the default expression list is all.
If variable appendwrite is set, the data may be added to an existing file.

17.5.87

Wrs2p: Write scattering parameters to file (Touchstone format)

General Form:
wrs2p [ f i l e ]
Writes out the s-parameters of a two-port to file.
In the active plot the following is required: vectors frequency, S11 S12 S21 S22, all having the
same length and having complex values (as a result of an ac analysis), and vector Rbase. For
details how to generate these data see chapt. 17.9.
The file format is Touchstone Version 1, ASCII, frequency in Hz, real and imaginary parts of
Snn versus frequency.
The default file name is s-param.s2p.
output example:
!2 - port S - parameter file
! Title : test for scattering parameters
! Generated by ngspice at Sat Oct 16 13:51:18 2010
# Hz S RI R 50
! freq
ReS11
ImS11
ReS21
...
2.500000 e +006 -1.358762 e -003 -1.726349 e -002
9.966563 e -001
5.000000 e +006 -5.439573 e -003 -3.397117 e -002
9.867253 e -001
....

17.5.88

Xgraph: use the xgraph(1) program for plotting.

General Form:
xgraph f i l e [ exprs ] [ p l o t o p t i o n s ]
The ngspice/ngnutmeg xgraph command plots data like the plot command but via xgraph, a
popular X11 plotting program. If file is either temp or tmp a temporary file is used to hold
the data while being plotted. For available plot options, see the plot command. All options
except for polar or smith plots are supported.

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CHAPTER 17. INTERACTIVE INTERPRETER

17.6

Control Structures

17.6.1

While - End

General Form:
while condition
statement
...
end
While condition, an arbitrary algebraic expression, is true, execute the statements.

17.6.2

Repeat - End

General Form:
r e p e a t [ number ]
statement
...
end
Execute the statements number times, or forever if no argument is given.

17.6.3

Dowhile - End

General Form:
dowhile c o n d i t i o n
statement
...
end
The same as while, except that the condition is tested after the statements are executed.

17.6.4

Foreach - End

General Form:
foreach var value
statement
...
end

...

The statements are executed once for each of the values, each time with the variable var set to
the current one. (var can be accessed by the $var notation - see below).

17.6. CONTROL STRUCTURES

17.6.5

317

If - Then - Else

General Form:
if condition
statement
...
else
statement
...
end
If the condition is non-zero then the first set of statements are executed, otherwise the second
set. The else and the second set of statements may be omitted.

17.6.6

Label

General Form:
l a b e l word
If a statement of the form goto word is encountered, control is transferred to this point, otherwise
this is a no-op.

17.6.7

Goto

General Form:
g o t o word
If a statement of the form label word is present in the block or an enclosing block, control is
transferred there. Note that if the label is at the top level, it must be before the goto statement
(i.e, a forward goto may occur only within a block). A block to just include goto on the top
level may look like
Example noop block to include forward goto on top level:
if (1)
...
goto gohere
...
l a b e l gohere
end

17.6.8

Continue

General Form:
continue
If there is a while, dowhile, or foreach block enclosing this statement, control passes to the test,
or in the case of foreach, the next value is taken. Otherwise an error results.

318

17.6.9

CHAPTER 17. INTERACTIVE INTERPRETER

Break

General Form:
break
If there is a while, dowhile, or foreach block enclosing this statement, control passes out of the
block. Otherwise an error results.
Of course, control structures may be nested. When a block is entered and the input is the
terminal, the prompt becomes a number of >s corresponding to the number of blocks the user
has entered. The current control structures may be examined with the debugging command
cdump (see 17.5.9).

17.7

Internally predefined variables

The operation of both ngutmeg and ngspice may be affected by setting variables with the set
command (17.5.57). In addition to the variables mentioned below, the set command in
ngspice also affects the behavior of the simulator via the options previously described under
the section on .OPTIONS (15.1). You also may define new variables or alter existing variables
inside .control ... .endc for later use in your user-defined script (see chapter 17.8).
The following list is in alphabetical order. All of them are acknowledged by ngspice. Frontend
variables (e.g. on circuits and simulation) are not defined in ngnutmeg. The predefined variables
which may be set or altered by the set command are:
appendwrite Append to the file when a write command is issued, if one already exists.
brief If set to FALSE, the netlist will be printed.
colorN These variables determine the colors used, if X is being run on a color display. N may
be between 0 and 15. Color 0 is the background, color 1 is the grid and text color, and
colors 2 through 15 are used in order for vectors plotted. The value of the color variables
should be names of colors, which may be found in the file /usr/lib/rgb.txt. ngspice
for Windows does support only white background (color0=white with black grid and text)
or or color0=black with white grid and text.
cpdebug Print control debugging information.
curplotdate Sets the date of the current plot.
curplotname Sets the name of the current plot.
curplottitle Sets the title (a short description) of the current plot.
debug If set then a lot of debugging information is printed.
device The name (/dev/tty??) of the graphics device. If this variable isnt set then the users
terminal is used. To do plotting on another monitor you probably have to set both the
device and term variables. (If device is set to the name of a file, nutmeg dumps the
graphics control codes into this file this is useful for saving plots.)

17.7. INTERNALLY PREDEFINED VARIABLES

319

diff_abstol The relative tolerance used by the diff command (default is 1e-12).
diff_reltol The relative tolerance used by the diff command (default is 0.001).
diff_vntol The absolute tolerance for voltage type vectors used by the diff command (default
is 1e-6).
echo Print out each command before it is executed.
editor The editor to use for the edit command.
filetype This can be either ascii or binary, and determines the format of the raw file (compact binary or text editor readable ascii). The default is binary.
fourgridsize How many points to use for interpolating into when doing Fourier analysis.
gridsize If this variable is set to an integer, this number is used as the number of equally spaced
points to use for the Y axis when plotting. Otherwise the current scale is used (which
may not have equally spaced points). If the current scale isnt strictly monotonic, then
this option has no effect.
gridstyle Sets the grid during plotting with the plot command. Will be overridden by direct
entry of gridstyle in the plot command. A linear grid is standard for both x and y axis. Allowed values are lingrid loglog xlog ylog smith smithgrid polar nogrid.
hcopydev If this is set, when the hardcopy command is run the resulting file is automatically
printed on the printer named hcopydev with the command lpr -Phcopydev -g file.
hcopyfont This variable specifies the font name for hardcopy output plots. The value is device
dependent.
hcopyfontsize This is a scaling factor for the font used in hardcopy plots.
hcopydevtype This variable specifies the type of the printer output to use in the hardcopy command. If hcopydevtype is not set, Postscript format is assumed. plot (5) is recognized
as an alternative output format. When used in conjunction with hcopydev, hcopydevtype
should specify a format supported by the printer.
hcopyscale This is a scaling factor for the font used in hardcopy plots (between 0 and 10).
hcopywidth Sets width of the hardcopy plot.
hcopyheight Sets height of the hardcopy plot.
hcopypscolor Sets the color of the hardcopy output. If not set, black & white plotting is assumed with different linestyles for each output vector plotted. Setting to any valid color
integer value yields a colored plot background (0: black 1: white, others see below) and
colored solid lines. This is valid for postscript only.
hcopypstxcolor This variable sets the color of the text in the postscript hardcopy output. If not
set, black is assumed on white background, white on black background. Valid colors are
0: black 1: white 2: red 3: blue 4: orange 5: green 6: pink 7: brown 8: khaki 9: plum 10:
orchid 11: violet 12: maroon 13: turquoise 14: sienna 15: coral 16: cyan 17: magenta
18: gray for smith grid 19: gray for smith grid 20: gray for normal grid

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CHAPTER 17. INTERACTIVE INTERPRETER

height The length of the page for asciiplot and print col.
history The number of events to save in the history list.
lprplot5 This is a printf(3s) style format string used to specify the command to use for
sending plot(5)-style plots to a printer or plotter. The first parameter supplied is the printer
name, the second parameter supplied is a file name containing the plot. Both parameters
are strings. It is trivial to cause ngspice to abort by supplying a unreasonable format
string.
lprps This is a printf(3s) style format string used to specify the command to use for sending
Postscript plots to a printer or plotter. The first parameter supplied is the printer name, the
second parameter supplied is a file name containing the plot. Both parameters are strings.
It is trivial to cause ngspice to abort by supplying a unreasonable format string.
modelcard The name of the model card (normally .MODEL)
nfreqs The number of frequencies to compute in the Fourier command. (Defaults to 10.)
ngbehavior Sets the compatibility mode of ngspice. To be set in spinit (16.5) or .spiceinit
(16.6).Its value all will improve compatibility to commercial simulators. Full compatibility is however not the intention of ngspice! This value may be set as a standard in
the future. ps, hs and spice3 are available. See chapt. 16.13.
noaskquit Do not check to make sure that there are no circuits suspended and no plots unsaved.
Normally ngspice warns the user when he tries to quit if this is the case.
nobjthack BJTs can have either 3 or 4 nodes, which makes it difficult for the subcircuit expansion routines to decide what to rename. If the fourth parameter has been declared as a
model name, then it is assumed that there are 3 nodes, otherwise it is considered a node.
To disable this, you can set the variable "nobjthack" which forces BJTs to have 4 nodes
(for the purposes of subcircuit expansion, at least).
nobreak Dont have asciiplot and print col break between pages.
noasciiplotvalue Dont print the first vector plotted to the left when doing an asciiplot.
nobjthack Assume that BJTs have 4 nodes.
noclobber Dont overwrite existing files when doing IO redirection.
noglob Dont expand the global characters *, ?, [, and ]. This is the default.
nomoremode If nomoremode is not set, whenever a large amount of data is being printed to
the screen (e.g, the print or asciiplot commands), the output is stopped every screenful
and continues when a carriage return is typed. If nomoremode is set then data scrolls off
the screen without check.
nonomatch If noglob is unset and a global expression cannot be matched, use the global characters literally instead of complaining.
noparse Dont attempt to parse input files when they are read in (useful for debugging). Of
course, they cannot be run if they are not parsed.

17.7. INTERNALLY PREDEFINED VARIABLES

321

noprintscale Dont print the scale in the leftmost column when a print col command is given.
nosort Dont have display sort the variable names.
nosubckt Dont expand subcircuits.
notrnoise Switch off the transient noise sources (chapt. 4.1.7).
numdgt The number of digits to print when printing tables of data (a, print col). The default
precision is 6 digits. On the VAX, approximately 16 decimal digits are available using
double precision, so p should not be more than 16. If the number is negative, one fewer
digit is printed to ensure constant widths in tables.
num_threads The number of of threads to be used if OpenMP (see chapt. 16.10) is selected.
The default value is 2.
plotstyle This should be one of linplot, combplot, or pointplot. linplot, the default,
causes points to be plotted as parts of connected lines. combplot causes a comb plot
to be done. It plots vectors by drawing a vertical line from each point to the X-axis, as
opposed to joining the points. pointplot causes each point to be plotted separately.
pointchars Set a string as a list of characters to be used as points in a point plot. Standard is
ox*+#abcdefhgijklmnpqrstuvwyz. Characters C are not allowed.
polydegree The degree of the polynomial that the plot command should fit to the data. If
polydegree is N, then nutmeg fits a degree N polynomial to every set of N points and
draw 10 intermediate points in between each end point. If the points arent monotonic,
then it tries rotating the curve and reducing the degree until a fit is achieved.
polysteps The number of points to interpolate between every pair of points available when
doing curve fitting. The default is 10.
program The name of the current program (argv[0]).
prompt The prompt, with the character ! replaced by the current event number. Single quotes
are required around the string entered!
rawfile The default name for rawfiles created.
remote_shell Overrides the name used for generating rspice runs (default is "rsh").
renumber Renumber input lines when an input file has .includes.
rndseed Seed value for random number generator (used by sgauss, sunif, and rnd functions).
If not set, the process Id is used as seed value.
rhost The machine to use for remote ngspice runs, instead of the default one (see the description of the rspice command, below).
rprogram The name of the remote program to use in the rspice command.
sourcepath A list of the directories to search when a source command is given. The default
is the current directory and the standard ngspice library (/usr/local/lib/ngspice, or
whatever LIBPATH is #defined to in the ngspice source.

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CHAPTER 17. INTERACTIVE INTERPRETER

specwindow Windowing for commands spec (17.5.69) or fft (17.5.24). May be one of the
following:
bartlet blackman cosine gaussian hamming hanning none rectangular triangle.
specwindoworder Integer value 2 - 8 (default 2), used by commands spec or fft.
spicepath The program to use for the aspice command. The default is /cad/bin/spice.
strict_errorhandling If set by the user, an error detected during circuit parsing will immediately lead ngspice to exit with exit code 1 (see 18.5). May be set in files spinit (16.5) or
.spiceinit (16.6) only.
subend The card to end subcircuits (normally .ends).
subinvoke The prefix to invoke subcircuits (normally X).
substart The card to begin subcircuits (normally .subckt).
term The mfb name of the current terminal.
ticmarks An integer value n, n tics (a small x) will be set on your graph. (Arrangement of
the tics ?)
ticlist A list of integers, e.g. ( 4 14 24 ) to set tics (small x) on your graph.(Arrangement of
the tics ?)
units If this is degrees, then all the trig functions will use degrees instead of radians.
unixcom If a command isnt defined, try to execute it as a UNIX command. Setting this option
has the effect of giving a rehash command, below. This is useful for people who want to
use ngnutmeg as a login shell.
wfont Set the font for the graphics plot in MS Windows. Typical fonts are courier, times,
arial and all others found on your machine. Default is courier.
wfont_size The size of the windows font. Default is depending on systems settings, something
like
width The width of the page for asciiplot and print col (see also 15.5.7).
x11lineararcs Some X11 implementations have poor arc drawing. If you set this option,
Ngspice will plot using an approximation to the curve using straight lines.
xbrushwidth Linewidth for grid, border and graph.
xfont Set the font for the graphics plot in X11 (LINUX, Cygwin, etc.). Input format has still to
be checked.
xtrtol Set trtol, e.g. to 7, so to avoid the speed reduction with XSPICE (see 16.9). Be aware of
potential precision degradation or convergence issues using this option.

17.8. SCRIPTS

17.8

323

Scripts

Expressions, functions, constants, commands, variables, vectors, and control structures may be
assembled into scripts within a .control ... .endc section of the input file. The script allows
to automate a more complex ngspice behavior: simulations are performed, output data are the
analyzed, simulations repeated with modified parameters, output vectors for plotting are assembled. The ngspice scripting language is not very powerful, but easily integrated into the
simulation flow.
The ngspice input file for scripting contains the usual circuit netlist, modelcards, and a script,
enclosed in the .control .. .endc section. ngspice is started in interactive mode with the input
file in the command line (or sourced later with the source command). After reading the input
file, the command sequence is immediately processed. Variables or vectors set by previous
commands may be used in commands following their definition. data may be stored, plotted or
grouped into new vectors for additional charts supporting data evaluation.

17.8.1

Variables

Variables are defined and initialized with the set command (17.5). set output=10 will defined the variable output and set it to a (real) number 10. Predefined variables, which are used
inside ngspice for specific purposes, are listed in chapt. 17.7. Variables are accessible globally.
The values of variables may be used in commands by writing $varname where the value of the
variable is to appear, e.g. $output. The special variables $$ and $< refer to the process ID of
the program and a line of input which is read from the terminal when the variable is evaluated,
respectively. If a variable has a name of the form $&word, then word is considered a vector (see
below), and its value is taken to be the value of the variable. If $foo is a valid variable, and is of
type list, then the expression $foo[low-high] represents a range of elements. Either the upper
index or the lower may be left out, and the reverse of a list may be obtained with $foo[len-0].
Also, the notation $?foo evaluates to 1 if the variable foo is defined, 0 otherwise, and $#foo
evaluates to the number of elements in foo if it is a list, 1 if it is a number or string, and 0 if it is
a Boolean variable.

17.8.2

Vectors

Ngspice and ngnutmeg data is in the form of vectors: time, voltage, etc. Each vector has a type,
and vectors can be operated on and combined algebraically in ways consistent with their types.
Vectors are normally created as a result of a transient or dc simulation. They are also established
when a data file is read in (see the load command 17.5.36). They can also be created with the
let command 17.5.33 inside a script. If a variable has a name of the form $&word, then word
is considered a vector, and its value is taken to be the value of the variable.

17.8.3

Commands

Commands have been described in chapter 17.5.

324

17.8.4

CHAPTER 17. INTERACTIVE INTERPRETER

control structures

Control structures have been described in chapter 17.6. Some simple examples will be given
below.

Control structure examples:


Test sequences for ngspice control structures
* vectors are used ( except foreach )
* start in interactive mode
. control
* test sequence for while , dowhile
let loop = 0
echo
echo enter loop with " $ & loop "
dowhile loop < 3
echo within dowhile loop " $ & loop "
let loop = loop + 1
end
echo after dowhile loop " $ & loop "
echo
let loop = 0
while loop < 3
echo within while loop " $ & loop "
let loop = loop + 1
end
echo after while loop " $ & loop "
let loop = 3
echo
echo enter loop with " $ & loop "
dowhile loop < 3
echo within dowhile loop " $ & loop "
let loop = loop + 1
end
echo after dowhile loop " $ & loop "
echo
let loop = 3
while loop < 3
echo within while loop " $ & loop "
$ no output expected
let loop = loop + 1
end
echo after while loop " $ & loop "

$ output expected

17.8. SCRIPTS

325

Control structure examples (continued):


* test for while , repeat , if , break
let loop = 0
while loop < 4
let index = 0
repeat
let index = index + 1
if index > 4
break
end
end
echo index " $ & index "
loop " $ & loop "
let loop = loop + 1
end
* test sequence for foreach
echo
foreach outvar 0 0.5 1 1.5
echo parameters : $outvar
end
* test for if ... else ... end
echo
let loop = 0
let index = 1
dowhile loop < 10
let index = index * 2
if index < 128
echo " $ & index " lt 128
else
echo " $ & index " ge 128
end
let loop = loop + 1
end
* simple test for label , goto
echo
let loop = 0
label starthere
echo start " $ & loop "
let loop = loop + 1
if loop < 3
goto starthere
end
echo end " $ & loop "

$ foreach parameters are variables ,


$ not vectors !

326

CHAPTER 17. INTERACTIVE INTERPRETER

Control structure examples (continued):


* test for label , nested goto
echo
let loop = 0
label starthere1
echo start nested " $ & loop "
let loop = loop + 1
if loop < 3
if loop < 3
goto starthere1
end
end
echo end " $ & loop "
* test for label , goto
echo
let index = 0
label starthere2
let loop = 0
echo We are at start with index " $ & index " and loop " $ & loop "
if index < 6
label inhere
let index = index + 1
if loop < 3
let loop = loop + 1
if index > 1
echo jump2
goto starthere2
end
end
echo jump
goto inhere
end
echo We are at end with index " $ & index " and loop " $ & loop "

17.8. SCRIPTS

327

Control structure examples (continued):


* test goto in while loop
let loop = 0
if 1
$ outer loop to allow nested forward label endlabel
while loop < 10
if loop > 5
echo jump
goto endlabel
end
let loop = loop + 1
end
echo before $ never reached
label endlabel
echo after " $ & loop "
end
* test for using variables , simple test for label , goto
set loop = 0
label starthe
echo start $loop
let loop = $loop + 1 $ expression needs vector at lhs
set loop = " $ & loop "
$ convert vector contents to variable
if $loop < 3
goto starthe
end
echo end $loop
. endc

17.8.5

Example script spectrum

A typical example script named spectrum is delivered with the ngspice distribution. Even if it
is made obsolete by the internal spec command (see 17.5.69) and especially by the much faster
fft command (see 17.5.24), it may act as a good example for getting acquainted with the ngspice
(or nutmeg) post-processor language.
As a suitable input for spectrum you may run a ring-oscillator, delivered with ngspice in e.g.
test/bsim3soi/ring51_41.cir. For an adequate resolution you will need a simulation time of 1
s. Then a small control script may start ngspice by loading the R.O. simulation data and start
spectrum.
Small script to start ngspice, read the simulation data and start spectrum:
* t e s t f o r s c r i p t spectrum
. control
load ring51_41 . out
s p e c t r u m 10MEG 2500MEG 1MEG v ( o u t 2 5 ) v ( o u t 5 0 )
. endc

328

CHAPTER 17. INTERACTIVE INTERPRETER

17.8. SCRIPTS

17.8.6

329

Example script for random numbers

Generation and test of random numbers with Gaussian distribution


* agauss t e s t in ngspice
* g e n e r a t e a s e q u e n c e o f g a u s s i a n d i s t r i b u t e d random numbers .
* t e s t t h e d i s t r i b u t i o n by s o r t i n g t h e numbers i n t o
* a histogram ( buckets )
. control
d e f i n e a g a u s s ( nom , a v a r , s i g ) ( nom + a v a r / s i g * s g a u s s ( 0 ) )
l e t mc_runs = 200
l e t run = 0
l e t no_buck = 8
$ number o f b u c k e t s
l e t b u c k e t = u n i t v e c ( no_buck ) $ e a c h e l e m e n t c o n t a i n s 1
l e t d e l t a = 3 e 11
$ width of each bucket , depends
$ on a v a r and s i g
l e t l o l i m i t = 1 e 09 3 * d e l t a
l e t h i l i m i t = 1 e 09 + 3 * d e l t a
d o w h i l e r u n < mc_runs
l e t v a l = a g a u s s ( 1 e 09 , 1 e 10 , 3 ) $ g e t t h e random number
i f ( val < l o l i m i t )
l e t bucket [0] = bucket [0] + 1 $ lowest bucket
end
let part = 1
d o w h i l e p a r t < ( no_buck 1 )
i f (( val < ( l o l i m i t + part * delta )) &
+ ( v a l > ( l o l i m i t + ( p a r t 1) * d e l t a ) ) )
l e t bucket [ part ] = bucket [ part ] + 1
break
end
let part = part + 1
end
i f ( val > h i l i m i t )
* highest bucket
l e t b u c k e t [ no_buck 1 ] = b u c k e t [ no_buck 1 ] + 1
end
l e t run = run + 1
end
let part = 0
d o w h i l e p a r t < no_buck
l e t value = bucket [ part ] 1
s e t v a l u e = " $&v a l u e "
* p r i n t the buckets contents
echo $ v a l u e
let part = part + 1
end
. endc
. end

330

17.8.7

CHAPTER 17. INTERACTIVE INTERPRETER

Parameter sweep

While there is no direct command to sweep a device parameter during simulation, you may use
a script to emulate such behavior. The example input file contains of an resistive divider with
R1 and R2, where R1 is swept from a start to a stop value inside of the control section, using
the alter command (see 17.5.3).
Input file with parameter sweep
p a r a m e t e r sweep
* r e s i s t i v e d i v i d e r , R1 s w e p t from s t a r t _ r t o s t o p _ r
VDD 1 0 DC 1
R1 1 2 1 k
R2 2 0 1 k
. control
l e t s t a r t _ r = 1k
l e t s t o p _ r = 10 k
l e t d e l t a _ r = 1k
let r_act = start_r
* loop
while r_act le stop_r
a l t e r r1 r _ a c t
op
print v (2)
let r_act = r_act + delta_r
end
. endc
. end

17.8.8

Output redirection

The console outputs delivered by commands like print (17.5.45), echo (17.5.21), or others may
be redirected into a text file. print vec > filename will generate a new file or overwrite
an existing file named filename, echo text >> filename will append the new data to the
file filename. Output redirection may be mixed with commands like wrdata.

17.9. SCATTERING PARAMETERS (S-PARAMETERS)

331

Input file with output redirection > and >>


** MOSFET Gain S t a g e (AC ) : B e n c h m a r k i ng I m p l e m e n t a t i o n o f BSIM4 . 0 . 0
** by Weidong L i u 5 / 1 6 / 2 0 0 0 .
** o u t p u t r e d i r e c t i o n i n t o f i l e
M1 3 2 0 0 N1 L=1u W=4u
R s o u r c e 1 2 100 k
R l o a d 3 vdd 25 k
Vdd vdd 0 1 . 8
Vin 1 0 1 . 2 a c 0 . 1
. control
a c d e c 10 100 1000Meg
plot v (2) v (3)
l e t f l e n = length ( frequency ) $ length of the vector
l e t loopcounter = 0
e c h o o u t p u t t e s t > t e x t . t x t $ s t a r t new f i l e t e s t . t x t
* loop
while loopcounter l t f l e n
l e t v o u t 2 = v ( 2 ) [ l o o p c o u n t e r ] $ g e n e r a t e a s i n g l e p o i n t complex v e c t o r
l e t vout2re = r e a l ( vout2 ) $ g e n e r a t e a s i n g l e p o i n t r e a l v e c t o r
l e t v o u t 2 i m = imag ( v o u t 2 ) $ g e n e r a t e a s i n g l e p o i n t i m a g i n a r y v e c t o r
l e t v o u t 3 = v ( 3 ) [ l o o p c o u n t e r ] $ g e n e r a t e a s i n g l e p o i n t complex v e c t o r
l e t vout3re = r e a l ( vout3 ) $ g e n e r a t e a s i n g l e p o i n t r e a l v e c t o r
l e t v o u t 3 i m = imag ( v o u t 3 ) $ g e n e r a t e a s i n g l e p o i n t i m a g i n a r y v e c t o r
l e t freq = frequency [ loopcounter ] $ generate a single point vector
e c h o bbb " $&f r e q " " $&v o u t 2 r e " " $&v o u t 2 i m " " $&v o u t 3 r e " " $&v o u t 3 i m " >>
+text . txt
$ a p p e n d t e x t and d a t a t o f i l e ( c o n t i n u e d fromm l i n e a b o v e )
l e t loopcounter = loopcounter + 1
end
. endc
.MODEL N1 NMOS LEVEL=14 VERSION = 4 . 3 . 0 TNOM=27
. end

17.9

Scattering parameters (s-parameters)

17.9.1

Intro

A command line script, available from the ngspice distribution at examples/control_structs/sparam.cir, together with the command wrs2p (see chapt. 17.5.87) allows to calculate, print
and plot the scattering parameters S11, S21, S12, and S22 of any two port circuit at varying
frequencies.
The printed output using wrs2p is a Touchstone version 1 format file. The file follows the
format according to The Touchstone File Format Specification, Version 2.0, available from here.

332

CHAPTER 17. INTERACTIVE INTERPRETER

An example is given as number 13 on page 15 of that specification.

17.9.2

S-parameter measurement basics

S-parameters allow a two-port description not just by permuting I1 , U1 , I2 , U2 , but using a


superposition, leading to a power view of the port (We only look at two-ports here, because
multi-ports are not (yet?) implemented.).
You may start with the effective power, being negative or positive
P = ui

(17.1)

The value of P may be the difference of two real numbers, with K being another real number.



ui = P = a2 b2 = (a+b)(ab) = (a+b)(KK 1 )(ab) = {K(a + b)} K 1 (a b) (17.2)
Thus you get
K 1 u = a + b

(17.3)

Ki = a b

(17.4)

a=

u + K 2i
2K

(17.5)

b=

u K 2i
2K

(17.6)

and finally

By introducing the reference resistance Z0 := K 2 > 0 we get finally the Heaviside transformation
a=

u + Z0 i
,
2 Z0

b=

u Z0 i

2 Z0

(17.7)

In case of our two-port we subject our variables to a Heaviside transformation


a1 =

U1 + Z0 I1

2 Z0

b1 =

U1 Z0 I1

2 Z0

(17.8)

a2 =

U2 + Z0 I2

2 Z0

b2 =

U2 Z0 I2

2 Z0

(17.9)

The s-matrix for a two-port then is

17.9. SCATTERING PARAMETERS (S-PARAMETERS)

b1
b2


=

s11 s12
s21 s22



a1
a2

333


(17.10)

Two obtain s11 we have to set a2 = 0. This is accomplished by loading the output port exactly
with the reference resistance Z0 , which sinks a current I2 = U2 /Z0 from the port.

s11 =

s11 =

b1
a1


(17.11)
a2 =0

U1 Z0 I1
U1 + Z0 I1

(17.12)

Loading the input port from an ac source U0 via a resistor with resistance value Z0 , we obtain
the relation
U0 = Z0 I1 +U1

(17.13)

2U1 U0
U0

(17.14)

Entering this into 17.12, we get


s11 =
For s21 we obtain similarly

s21 =

s21 =

b2
a1


(17.15)
a2 =0

U2 Z0 I2 2U2
=
U1 + Z0 I1
U0

(17.16)

Equations 17.14 and 17.16 now tell us how to measure s11 and s21 : Measure U1 at the input port,
multiply by 2 using an E source, subtracting U0 which for simplicity is set to 1, and divide by
U0 . At the same time measure U2 at the output port, multiply by 2 and divide by U0 . Biasing and
measuring is done by subcircuit S_PARAM. To obtain s22 and s12 , you have to exchange the
input and output ports of your two-port and do the same measurement again. This is achieved
by switching resistors from low (1m) to high (1T ) and thus switching the input and output
ports.

17.9.3

Usage

Copy and then edit s-param.cir. You will find this file in directory /examples/control_structs of
the ngspice distribution.
The reference resistance (often called characteristic impedance) for the measurements is added
as a parameter
.param Rbase=50
The bias voltages at the input and output ports of the circuit are set as parameters as well:

334

CHAPTER 17. INTERACTIVE INTERPRETER

.param Vbias_in=1 Vbias_out=2


Place your circuit at the appropriate place in the input file, e.g. replacing the existing example
circuits. The input port of your circuit has two nodes in, 0. The output port has the two nodes
out, 0. The bias voltages are connected to your circuit via the resistances of value Rbase at the
input and output respectively. This may be of importance for the operating point calculations if
your circuit draws a large dc current.
Now edit the ac commands (see 17.5.1) according to the circuit provided, e.g.
ac lin 100 2.5MEG 250MEG $ use for Tschebyschef
Be careful to keep both ac lines in the .control ... .endc section the same and only change both
in equal measure!
Select the plot commands (lin/log, or smith grid) or the write to file commands (write, wrdata,
or wrs2p) according to your needs.
Run ngspice in interactive mode
ngspice s-param.cir

17.10

MISCELLANEOUS (old stuff, has to be checked for


relevance)

C-shell type quoting with and , and backquote substitution may be used. Within single
quotes, no further substitution (like history substitution) is done, and within double quotes,
the words are kept together but further substitution is done. Any text between backquotes is
replaced by the result of executing the text as a command to the shell.
History substitutions, similar to C-shell history substitutions, are also available - see the C-shell
manual page for all of the details. The characters ~, @{, and @} have the same effects as
they do in the C-Shell, i.e., home directory and alternative expansion. It is possible to use the
wildcard characters *, ?, [, and ] also, but only if you unset noglob first. This makes them rather
useless for typing algebraic expressions, so you should set noglob again after you are done with
wildcard expansion. Note that the pattern [^abc] matches all characters except a, b, and c.
If X is being used, the cursor may be positioned at any point on the screen when the window
is up and characters typed at the keyboard are added to the window at that point. The window
may then be sent to a printer using the xpr(1) program.

17.11

Bugs (old stuff, has to be checked for relevance)

When defining aliases like alias pdb plot db( !:1 - !:2 ) you must be careful to quote the
argument list substitutions in this manner. If you quote the whole argument it might not work
properly.
In a user-defined function, the arguments cannot be part of a name that uses the plot.vec syntax.
For example: define check(v(1)) cos(tran1.v(1)) does not work.

Chapter 18
Ngspice User Interfaces
ngspice offers a variety of user interfaces. For an overview (several screen shots) please have a
look at the ngspice web page.

18.1

MS Windows Graphical User Interface

If compiled properly (e.g. using the with-wingui flag for ./configure under MINGW), ngspice
for Windows offers a simple graphical user interface. In fact this interface does not offer much
more for data input than a console would offer, e.g. command line inputs, command history
and program text output. First of all it applies the Windows api for data plotting. If you run the
sample input file given below, you will get an output as shown in fig. 16.1.
Input file:
***** S i n g l e NMOS T r a n s i s t o r F o r BSIM3V3 . 1
g e n e r a l p u r p o s e c h e c k ( IdVd ) ***
*
*** c i r c u i t d e s c r i p t i o n ***
m1 2 1 3 0 n1 L = 0 . 6 u W= 1 0 . 0 u
vgs 1 0 3 . 5
vds 2 0 3 . 5
vss 3 0 0
*
. dc v d s 0 3 . 5 0 . 0 5 v g s 0 3 . 5 0 . 5
*
. control
run
p l o t vss # branch
. endc
*
* UCB p a r a m e t e r s BSIM3v3 . 2
. i n c l u d e . . / Exam_BSIM3 / M o d e l c a r d s / m o d e l c a r d . nmos
. i n c l u d e . . / Exam_BSIM3 / M o d e l c a r d s / m o d e l c a r d . pmos
*
. end

335

336

CHAPTER 18. NGSPICE USER INTERFACES

The GUI consists of an I/O port (lower window) and a graphics window, created by the plot
command.

Figure 18.1: MS Windows GUI

The output window displays messages issued by ngspice. You may scroll the window to get
more of the text. The input box (white box) may be activated by a mouse click to accept any
of the valid ngspice commends. The lower left output bar displays the actual input file. ngspice
progress during setup and simulation is shown in the progress window (ready). The Quit
button allow to interrupt ngspice. If ngspice is actively simulating, due to using only a single
thread, this interrupt has to wait until the window is accessible from within ngspice, e.g. during
an update of the progress window.
In the plot window there is the upper left button, which activated a drop down menu. You may
select to print the plot window shown (a very simple printer interface, to be improved), set
up any of the printers available on your computer, or issue a postscript file of the actual plot
window, either black&white or colored.

18.2. MS WINDOWS CONSOLE

337

Instead of plotting with black background, you may set the background to any other color,
preferably to white using the command shown below.
Input file modification for white background:
. control
run
* white background
s e t color0 =white
* b l a c k g r i d and t e x t ( o n l y n e e d e d w i t h X11 , a u t o m a t i c w i t h MS Win )
set color1=black
* w i d e r g r i d and p l o t l i n e s
s e t x b r u s h w i d t h =2
p l o t vss # branch
. endc

Figure 18.2: Plotting with white background

18.2

MS Windows Console

If the with-wingui flag for ./configure under MINGW is omitted (see 32.2.5) or console_debug
or console_release is selected in the MS Visual Studio configuration manager, then ngspice will
compile without any internal graphical input or output capability. This may be useful if you
apply ngspice in a pipe inside the MSYS window, or use it being called from another program,
and just generating output files from a given input. The plot (17.5.43) command will not do
and leads to an error message.

338

CHAPTER 18. NGSPICE USER INTERFACES

Only on the ngspice console binary in MS Windows input/output redirection is possible, if


ngspice is called (e.g. within a MSYS shell or from a shell script) like
$ ngspice < input.
This feature is used in the new CMC model test suite (to be described elsewhere), thus requires
a console binary.
You still may generate graphics output plots or prints by gnuplot (17.5.26), if installed properly
(18.7), or by selecting a suitable printing option (18.6).

18.3

LINUX

The standard user interface is a console for input and the X11 graphics system for output with
the interactive plot (17.5.43) command. If ngspice is compiled with the without-x flag for
./configure, a console application without graphical interface results. For more sophisticated
input user interfaces please have a look at chapt. 18.8.

18.4

CygWin

The CygWin interface is similar to the LINUX interface (18.3), i.e. console input and X11
graphics output. To avoid the warning of a missing graphical user interface, you have to start
the X11 window manager by issuing the commands
$ export DISPLAY=:0.0
$ xwin -multiwindow -clipboard &
inside of the CygWin window before starting ngspice.

18.5

Error handling

Error messages and error handling in ngspice have grown over the years, include a lot of traditional behavior and thus are not very systematic and consistent.
Error messages may occur with the token Error:. Often the errors are non-recoverable and will
lead to exiting ngspice with error code 1. Sometimes, however, you will get an error message,
but ngspice will continue, and may either bail out later because the error has propagated into
the simulation, sometimes ngspice will continue, deliver wrong results and exit with error code
0 (no error detected!).
In addition ngspice may issue warning messages like Warning: .... These should cover recoverable errors only.
So there is still work to be done to define a consistent error messaging, recovery or exiting. A
first step is the user definable variable strict_errorhandling. This variable may be set in files
spinit (16.5) or .spiceinit (16.6) to immediately stop ngspice, after an error is detected during
parsing the circuit. An error message is sent, the ngspice exit code is 1. This behavior deviates
from traditional spice error handling and thus is introduced as an option only.
XSPICE error messages are explained in chapter 29.

18.6. POSTSCRIPT PRINTING OPTIONS

18.6

339

Postscript printing options

This info is compiled from Roger L. Traylors web page. All the commands and variables you
can set are described in chapt. 17.5. The corresponding input file for the examples given below
is listed in chapt. 21.1. Just add the .control section to this file and run in interactive mode by
$ ngspice xspice_c1_print.cir
================================================================
One way is to setup your printing like this:
.control
set hcopydevtype=postscript
op
run
plot vcc coll emit
hardcopy temp.ps vcc coll emit
.endc
Then print the postscript file temp.ps to a postscript printer.
================================================================
You can add color traces to it if you wish:
.control
set hcopydevtype=postscript
* allow color and set background color if set to value > 0
set hcopypscolor=1
*color0 is background color
*color1 is the grid and text color
*colors 2-15 are for the vectors
set color0=rgb:f/f/f
set color1=rgb:0/0/0
op
run
hardcopy temp.ps vcc coll emit
.endc
Then print the postscript file temp.ps to a postscript printer.
================================================================
You can also direct your output directly to a designated printer (not available in MS Windows):
.control
set hcopydevtype=postscript

340

CHAPTER 18. NGSPICE USER INTERFACES

*send output to the printer kec3112-clr


set hcopydev=kec3112-clr
hardcopy out.tmp vcc coll emit
=================================================================

18.7

Gnuplot

Install Gnuplot (on LINUX available from the distribution, on Windows available here). On
Windows expand the zip file to a directory of your choice, add the path <any directory>/gnuplot/bin
to the PATH variable, and go... The command to invoke Gnuplot (17.5.26) is limited however
to x/y plots (no polar etc.).

18.8

Integration with CAD software and third party GUIs

In this chapter you will find some links and comments on GUIs for ngspice offered from other
projects and on the integration of ngspice into a circuit development flow. The data given rely
mostly on information available from the web and thus is out of our control. It also may be far
from complete. The GUIs KJWaves and GNUSpiceGUI help you to navigate the commands
to need to perform your simulation. XCircuit and the GEDA tools gschem and gnetlist offer
integrating schematic capture and simulation.

18.8.1

KJWaves

KJWaves was written to be a cross-platform SPICE tool in pure Java. It aids in viewing, modifying, and simulating SPICE CIRCUIT files. Output from SPICE3 (ngspice) can be read
and displayed. Resulting graphs may be printed and saved. The Java executable will run
under LINUX and Windows (and maybe other OSs). The development site is available at
http://sourceforge.net/projects/kjwaves/. You may find the project home page at http://www.comefly.us/.

18.8.2

GNU Spice GUI

Another GUI, to be found at http://sourceforge.net/projects/gspiceui/.

18.8.3

XCircuit

CYGWIN and especially LINUX users may find XCircuit valuable to establish a development
flow including schematic capture and circuit simulation.

18.8. INTEGRATION WITH CAD SOFTWARE AND THIRD PARTY GUIS

18.8.4

341

GEDA

The gEDA project is developing a full GPLd suite and toolkit of Electronic Design Automation
tools for use with a LINUX. Ngspice may be integrated into the development flow. Two web
sites offer tutorials using gschem and gnetlist with ngspice:
http://geda.seul.org/wiki/geda:csygas
http://geda.seul.org/wiki/geda:ngspice_and_gschem

18.8.5

CppSim

A complete simulation environment called CppSim has been developed and made available for
system level simulation of complex mixed signal circuits. ngspice has been integrated into the
simulation flow, as described here.

18.8.6

NGSPICE Online

A web browser based interface is offered here. Simulation is performed on a remote server. The
project is not directly linked to our ngspice development project.

18.8.7

Spicy Schematics

An IPAD and web interface (including schematics entry) to ngspice is offered here.Simulation
is performed on a remote server.

18.8.8

MSEspice

A graphical front end to ngspice, using the Free Pascal cross platform RAD environment
MSEide+MSEgui.

18.8.9

PartSim

A web based guiin your browser, including schematics entry. Simulation is performed on a
remote server.

342

CHAPTER 18. NGSPICE USER INTERFACES

Chapter 19
ngspice as shared library or dynamic link
library
ngspice may be compiled as a shared library. This allows adding ngspice to an application
which then gains control over the simulator. The shared module offers an interface which
exports functions controlling the simulator and callback functions for feedback.
So you may send an input "file" with a netlist to ngspice, start the simulation in a separate thread,
read back simulation data at each time point, stop the simulator depending on some condition,
alter device or model parameters and then resume the simulation.
Shared ngspice does not have any user interface. The calling process is responsible for this. It
may offer a graphical user interface, add plotting capability or any other interactive element.
You may develop and optimize these user interface elements without a need to alter the ngspice
source code itself, using a console application or GUIs like gtk, Delphi, Qt or others.

19.1

Compile options

19.1.1

How to get the sources

Currently (as of ngspice-25 being the actual release), you will have to use the direct loading of
the sources from the git repository (see chapt. 32.1.2).

19.1.2

LINUX, MINGW, CYGWIN

Compilation is done as described in chapts. 32.1 or 32.2.1. Use the configure option --with-ngshared
instead of --with-x or --with-wingui.
Other operation systems (Mac OS, BSD, ...) have not been tested so far. Your input is welcome!

19.1.3

MS Visual Studio

Compilation is similar to what has been described in chapt. 32.2.3. There is however a dedicated project file coming with the source code to generate ngspice.dll. Go to the directory
visualc-shared and start the project with double clicking on sharedspice.sln.

343

344

19.2

CHAPTER 19. NGSPICE AS SHARED LIBRARY OR DYNAMIC LINK LIBRARY

Linking shared ngspice to a calling application

Basically there are two methods (as with all *.so, *.dll libraries). The caller may link to a (small)
library file during compiling/linking, and then immediately search for the shared library upon
being started. It is also possible to dynamically load the ngspice shared library at runtime using
the dlopen/LoadLibrary mechanisms.

19.2.1

Linking during creating the caller

While creating the ngspice shared lib, not only the *.so (*.dll) file is created, but also a small
library file, which just includes references to the exported symbols. Depending on the OS, these
may be called libngspice.dll.a, ngspice.lib. Linux and MINGW also allow linking to the shared
object itself. The shared object is not included into the executable component but is tied to the
execution.

19.2.2

Loading at runtime

dlopen (LINUX) or LoadLibrary (MS Windows) will load libngspice.so or ngspice.dll into the
address space of the caller at runtime. The functions return a handle which may be used to
acquire the pointers to the functions exported by libngspice.so. Detaching ngspice at runtime is
equally possible (using dlclose/FreeLibrary), after the background thread has been stopped and
all callbacks have returned.

19.3

Shared ngspice API

The sources for the ngspice shared library API are contained in a single c file (sharedspice.c)
and a corresponding header file sharedspice.h. The type and function declarations are contained
in sharedspice.h, which may be directly added to the calling application, if written in C or C++.

19.3.1

structs and types defined for transporting data

pvector_info is returned by the exported function ngGet_Vec_Info (see 19.3.2.5). Adresses of


the vector name, type, real or complex data are transferred and may be read asynchronously
during or after the simulation.
vector_info
typedef s t r u c t vector_info {
c h a r * v_name ;
/*
i n t v_type ;
/*
short v_flags ;
/*
double * v _ r e a l d a t a ;
/*
ngcomplex_t * v_compdata ; / *
int v_length ;
/*
} vector_info , * pvector_info ;

Same a s so_vname . * /
Same a s s o _ v t y p e . * /
F l a g s ( a c o m b i n a t i o n o f VF_ * ) . * /
Real d a t a . */
Complex d a t a . * /
Length of t h e v e c t o r . */

19.3. SHARED NGSPICE API

345

The next two structures are used by the callback function SendInitData (see 19.3.3.5). Each
time a new plot is generated during simulation, e.g. when a sequence of op, ac and tran is used
or commands like linearize or fft are invoked, the function is called once by ngspice. Among
its parameters you find a pointer to a struct vecinfoall, which includes an array of vecinfo, one
for each vector. Pointers to the struct dvec, containing the vector, are included. This struct is
declared in header file src/include/ngspice/dvec.h.

vecinfo
typedef s t r u c t vecinfo
{
i n t number ;
/ * number o f v e c t o r , a s p o s t i o n i n t h e
linked l i s t of vectors , s t a r t s with 0 */
c h a r * vecname ;
/ * name o f t h e a c t u a l v e c t o r * /
bool i s _ r e a l ;
/ * TRUE i f t h e a c t u a l v e c t o r h a s r e a l d a t a * /
void * pdvec ;
/ * a v o i d p o i n t e r t o s t r u c t dvec *d , t h e
actual vector */
v o i d * p d v e c s c a l e ; / * a v o i d p o i n t e r t o s t r u c t d v e c * ds ,
the scale vector */
} vecinfo , * pvecinfo ;

vecinfoall
typedef s t r u c t vecinfoall
{
/* the plot */
c h a r * name ;
char * t i t l e ;
char * date ;
char * type ;
i n t veccount ;
/ * t h e d a t a a s an a r r a y o f v e c i n f o w i t h
l e n g t h e q u a l t o t h e number o f v e c t o r s
in the plot */
pvecinfo * vecs ;
} vecinfoall , * pvecinfoall ;

The next two structures are used by the callback function SendData (see 19.3.3.4). Each time a
new data point (e.g. time value and simulation output value(s)) is added to the vector structure
of the current plot, the function SendData is called by ngspice, among its parameters the actual
pointer pvecvaluesall, which contains an array of pointers to pvecvalues, one for each vector.

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vecvalues
typedef s t r u c t vecvalues {
c h a r * name ;
/ * name o f a s p e c i f i c v e c t o r * /
double c r e a l ;
/* actual data value */
d o u b l e cimag ;
/* actual data value */
bool i s _ s c a l e ;
/ * i f name i s t h e s c a l e v e c t o r * /
b o o l i s _ c o m p l e x ; / * i f t h e d a t a a r e complex numbers * /
} vecvalues , * pvecvalues ;
Pointer vecvaluesall to be found as parameter to callback function SendData.
vecvaluesall
typedef s t r u c t vecvaluesall {
i n t veccount ;
/ * number o f v e c t o r s i n p l o t * /
i n t vecindex ;
/* index of a c t u a l s e t of vectors , i . e .
t h e number o f a c c e p t e d d a t a p o i n t s * /
pvecvalues * vecsa ; /* values of a c t u a l s e t of vectors ,
i n d e x e d from 0 t o v e c c o u n t 1 * /
} vecvaluesall , * pvecvaluesall ;

19.3.2

Exported functions

The functions listed in this chapter are the (only) symbols exported by the shared library.
19.3.2.1

int ngSpice_Init(SendChar*, SendStat*, ControlledExit*, SendData*, SendInitData*, BGThreadRunning*, void)

After caller has loaded ngspice.dll, the simulator has to be initialized by calling ngSpice_Init(...).
Address pointers of several callback functions (see 19.3.3), which are to be defined in the caller,
are sent to ngspice.dll. The int return value is not used.
Pointers to callback functions (details see 19.3.3):
SendChar* callback function for reading printf, fprintf, fputs (NULL allowed)
SendStat* callback function for reading status string and percent value (NULL allowed)
ControlledExit* callback function for transferring a flag to caller, generated by ngspice upon
a call to function controlled_exit. May be used by caller to detach ngspice.dll, if dynamically loaded or to try any other recovery method, or to exit. (required)
SendData* callback function for sending an array of structs containing data values of all vectors in the current plot (simulation output) (NULL allowed)
SendInitData* callback function for sending an array of structs containing info on all vectors
in the current plot (immediately before simulation starts) (NULL allowed)

19.3. SHARED NGSPICE API

347

BGThreadRunning* callback function for sending a boolean signal (true if thread is running)
(NULL allowed)
void* Using the void pointer, you may send the object address of the calling function (self
or this pointer) to ngspice.dll. This pointer will be returned unmodified by any callback
function (see the *void pointers in chapter 19.3.3). Callback functions are to be defined
in the global section of the caller. Because they now have got the object address of the
calling function, they may direct their actions to the calling object.

19.3.2.2

int ngSpice_Init_Sync(GetVSRCData* , GetISRCData* , GetSyncData* , int*,


void*)

see chapt. 19.6.

19.3.2.3

int ngSpice_Command(char*)

Send a valid command (see the control or interactive commands) from caller to ngspice.dll.
Will be executed immediately (as if in interactive mode). Some commands are rejected (e.g.
plot, because there is no graphics interface). Command quit will remove internal data, and
then send a notice to caller via ngexit(). The function returns a 1 upon error, otherwise 0.

19.3.2.4

bool ngSpice_running (void)

Checks if ngspice is running in its background thread (returning true).

19.3.2.5

pvector_info ngGet_Vec_Info(char*)

uses the name of a vector (may be in the form vectorname or <plotname>.vectorname) as


parameter and returns a pointer to a vector_info struct. The caller may then directly assess the
vector data (but better should not modify them).

19.3.2.6

int ngSpice_Circ(char**)

sends an array of null-terminated char* to ngspice.dll. Each char* contains a single line of a
circuit (Each line is like it is found in an input file *.sp.). The last entry to char** has to be
NULL. Upon receiving the array, ngspice.dll will immediately parse the input and set up the
circuit structure (as if the circuit is loaded from a file by the source command). The function
returns a 1 upon error, otherwise 0.

19.3.2.7

char* ngSpice_CurPlot(void)

returns to the caller a pointer to the name of the current plot. For a definition of the term plot
see chapt. 17.3.

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19.3.2.8

char** ngSpice_AllPlots(void)

returns to the caller a pointer to an array of all plots (listed by their typename).
19.3.2.9

char** ngSpice_AllVecs(char*)

returns to the caller a pointer to an array of all vector names in the plot named by the string in
the argument.
19.3.2.10

bool ngSpice_SetBkpt(double)

see chapt. 19.6.

19.3.3

Callback functions

Callback functions are a means to return data from ngspice to the caller. These functions are
defined as global functions in the caller, so to be reachable by the C-coded ngspice. They are
declared according to the typedefs given below. ngspice receives their addresses from the caller
upon initialization with the ngSpice_Init(...) function (see 19.3.2.1). If the caller will not make
use of a callback, it may send NULL instead of the address (except for ControlledExit, which
is always required).
If ngspice is run in the background thread (19.4.2), the callback functions (defined in the caller)
also are called from within that thread. One has to be carefully judging how this behavior might
influence the caller, where now you have the primary and the background thread running in
parallel. So make the callback function thread safe. The integer identification number is only
used if you run several shared libraries in parallel (see chapt. 19.6). Three additional callback
function are described in chapt. 19.6.3.
19.3.3.1

typedef int (SendChar)(char*, int, void*)

char* string to be sent to caller output


int identification number of calling ngspice shared lib (default is 0, see chapt. 19.6)
void* return pointer received from caller during initialization, e.g. pointer to object having sent
the request
Sending output from stdout, stderr to caller. ngspice printf, fprintf, fputs, fputc functions are
redirected to this function. The char* string is generated by assembling the print outputs of
the above mentioned functions according to the following rules: The string commences with
"stdout ", if directed to stdout by ngspice (with "stderr " respectively); all tokens are assembled
in sequence, taking the printf format specifiers into account, until \n is hit. If set addescape
is given in .spiceinit, the escape character \ is added to any character from $[]\" found in the
string.
Each callback function has a void pointer as the last parameter. This is useful in object oriented programming. You may have sent the this (or self) pointer of the callers class object to
ngspice.dll during calling ngSpice_Init (19.3.2.1). The pointer is returned unmodified by each
callback, so the callback function may identify the class object which has initialized ngspice.dll.

19.3. SHARED NGSPICE API


19.3.3.2

349

typedef int (SendStat)(char*, int, void*)

char* simulation status and value (in percent) to be sent to caller


int identification number of calling ngspice shared lib (default is 0, see chapt. 19.6)
void* return pointer received from caller
sending simulation status to caller, e.g. the string tran 34.5%.

19.3.3.3

typedef int (ControlledExit)(int, bool, bool, int, void*)

int exit status


bool if true: immediate unloading dll, if false: just set flag, unload is done when function has
returned
bool if true: exit upon quit, if false: exit due to ngspice.dll error
int identification number of calling ngspice shared lib (default is 0, see chapt. 19.6)
void* return pointer received from caller
asking for a reaction after controlled exit.

19.3.3.4

typedef int (SendData)(pvecvaluesall, int, int, void*

vecvaluesall* pointer to array of structs containing actual values from all vectors
int number of structs (one per vector)
int identification number of calling ngspice shared lib (default is 0, see chapt. 19.6)
void* return pointer received from caller
send back actual vector data.

19.3.3.5

typedef int (SendInitData)(pvecinfoall, int, void*)

vecinfoall* pointer to array of structs containing data from all vectors right after initialization
int identification number of calling ngspice shared lib (default is 0, see chapt. 19.6)
void* return pointer received from caller
send back initialization vector data.

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19.3.3.6

typedef int (BGThreadRunning)(bool, int, void*)

bool true if background thread is running


int identification number of calling ngspice shared lib (default is 0, see chapt. 19.6)
void* return pointer received from caller
indicate if background thread is running

19.4

General remarks on using the API

19.4.1

Loading a netlist

Basically the input to shared ngspice is the same as if you would start a ngspice batch job, e.g.
you enter a netlist and the simulation command (any .dot analysis command like .tran, .op, or
.dc etc. as found in chapt. 15.3), as well as suitable options.
Typically you should not include a .control section in your input file. Any script described in a
.control section for standard ngspice should better be emulated by the caller and be sent directly
to ngspice.dll. Start the simulation according to chapt. 19.4.2 in an extra thread.
As an alternative, only the netlist has to be entered (without analysis command), then you may
use any interactive command as listed in chapt. 17.5 (except for the plot command).
The typical usage examples given below are excerpted from a caller written in C.
19.4.1.1

Loading from file

As with interactive ngspice, you may use the ngspice internal command source (17.5.68) to
load a complete netlist from a file.
Typical usage:
ngSpice_Command ( " s o u r c e . . / e x a m p l e s / a d d e r _ m o s . c i r " ) ;

19.4.1.2

Loading line by line

As with interactive ngspice, you may use the ngspice internal command circbyline (17.5.10) to
send a netlist line by line to the ngspice circuit parser.
Typical usage:
ngSpice_Command ( "
ngSpice_Command ( "
ngSpice_Command ( "
ngSpice_Command ( "
ngSpice_Command ( "

circbyline
circbyline
circbyline
circbyline
circbyline

fail test ");


V1 1 0 1 " ) ;
R1 1 0 1 " ) ;
. dc V1 0 1 0 . 1 " ) ;
. end " ) ;

The first line is a title line, which will be ignored during circuit parsing. As soon as the line
.end has been sent to ngspice, circuit parsing commences.

19.4. GENERAL REMARKS ON USING THE API


19.4.1.3

351

Loading as a string array

Typical usage:
c i r c a r r a y = ( char **) malloc ( s i z e o f ( char *) * 7 ) ;
circarray [0] = strdup (" t e s t array ");
c i r c a r r a y [ 1 ] = s t r d u p ( " V1 1 0 1 " ) ;
c i r c a r r a y [ 2 ] = s t r d u p ( " R1 1 2 1 " ) ;
c i r c a r r a y [ 3 ] = s t r d u p ( " C1 2 0 1 i c = 0 " ) ;
c i r c a r r a y [ 4 ] = s t r d u p ( " . t r a n 10 u 3 u i c " ) ;
c i r c a r r a y [ 5 ] = s t r d u p ( " . end " ) ;
c i r c a r r a y [ 6 ] = NULL ;
ngSpice_Circ ( c i r c a r r a y ) ;
An array of char pointers is mallocd, each netlist line is then copied to the array. strdup will
care for the memory allocation. The first entry to the array is a title line, the last entry has to
contain NULL. ngSpice_Circ(circarray); sends the array to ngspice, where circuit parsing is
started immediately. Dont forget to free the array after sending it, to avoid a memory leak.

19.4.2

Running the simulation

The following commands are used to start the simulator in its own thread, halt the simulation
and resume it again. The extra (background) thread enables the caller to continue with other
tasks in the main thread, e.g. watching its own event loop. Of course you have to take care
that the caller will not exit before ngspice is finished, otherwise you immediately will loose all
data. After having halted the simulator by suspending the background thread, you may assess
data, change ngspice parameters, or read output data using the callers main thread, before you
resume simulation using a background thread again. While the background thread is running,
ngspice will reject any other command sent by ngSpice_Command.
Typical usage:
ngSpice_Command ( " b g _ r u n " ) ;
...
ngSpice_Command ( " b g _ h a l t " ) ;
...
ngSpice_Command ( " b g _ r e s u m e " ) ;
Basically you may send the commands run or resume (no prefix bg_), starting ngspice within
the main thread. The caller then has to wait until ngspice returns from simulation. A command
halt is not available then.
After simulation is finished (test with callback 19.3.3.6), you may send other commands from
chapt. 17.5, emulating any .control script. These commands are executed in the main thread,
which should be o.k., because execution time is typically short.

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19.4.3

Accessing data

19.4.3.1

Synchronous access

The callback functions SendInitData (19.3.3.5) and SendData (19.3.3.4) allow access to simulator output data synchronized with the simulation progress.
Each time a new plot is generated during simulation, e.g. when a sequence of op, ac and tran
is used or commands like linearize or fft are invoked, the callback SendInitData is called by
ngspice. Immediately after setting up the vector structure of the new plot, the function is called
once. Its parameter is a pointer to the structure vecinfoall (19.3.1), which contains an array of
structures vecinfo, one for each vector in the actual plot. You may simply use vecname to get
the name of any vector. This time the vectors are still empty, but pointers to the vector structure
are available.
Each time a new data point (e.g. time value and simulation output value(s)) is added to the
vector structure of the current plot, the function SendData is called by ngspice. This allows
you to immediately access the simulation output synchronized with the simulation time, e.g.
to interface it to a runtime plot or to use it for some controlled simulation by stopping the
simulation based on a condition, altering parameters and resume the simulation. SendData
returns a structure vecvaluesall as parameter, which contains an array of structures vecvalues,
one for each vector.
Some code to demonstrate the callback function usage is referenced below (19.5).
19.4.3.2

Asynchronous access

During simulation, while the background thread is running, or after it is finished, you may
use the functions ngSpice_CurPlot (19.3.2.7), ngSpice_AllPlots (19.3.2.8), ngSpice_AllVecs
(19.3.2.9) to retrieve information about vectors available, and function ngGet_Vec_Info (19.3.2.5)
to obtain data from a vector and its corresponding scale vector. The timing of the caller and the
simulation progress are independent from each other and not synchronized.
Again some code to demonstrate the callback function usage is referenced below (19.5).

19.4.4

Altering model or device parameters

After halting ngspice by stopping the background thread (19.4.2), nearly all ngspice commands
are available. Especially alter (17.5.3) and altermod (17.5.4) may be used to change device
or model parameters. After the modification, the simulation may be resumed immediately.
Changes to a circuit netlist, however, are not possible. You would need to load a complete new
netlist (19.4.1) and restart the simulation from the beginning.

19.4.5

Output

After the simulation is finished, use the ngspice commands write (17.5.86) or wrdata (17.5.85)
to output data to a file as usual, use the print command (17.5.45) to retrieve data via callback
SendChar (19.3.3.1), or refer to accessing the data as described in chapter 19.4.3.

19.5. EXAMPLE APPLICATIONS

353

Typical usage:
ngSpice_Command ( " w r i t e t e s t o u t . raw V ( 2 ) " ) ;
ngSpice_Command ( " p r i n t V ( 2 ) " ) ;

19.4.6

Error handling

There are several occasions where standard ngspice suffers from an error, cannot recover internally and then exits. If this is happening to the shared module this would mean that the
parent application, the caller, is also forced to exit. Therefore (if not suffering form a seg fault)
ngspice.dll will call the function controlled_exit as usual, this now calls the callback function
ControlledExit (19.3.3.3), which hands over the request for exiting to the caller. The caller
now has the task to handle the exit code for ngspice.
If ngspice has been linked at runtime by dlopen/LoadLibrary (see 19.2.2), the callback may
close all threads, and then detach ngspice.dll by invoking dlclose/FreeLibrary. The caller may
then restart ngspice by another loading and initialization (19.3.2.1).
If ngspice is included during linking the caller (see 19.2.1), there is not yet a good and general
solution to error handling, if the error is non-recoverable from inside ngspice.

19.5

Example applications

Three executables (coming with source code) serve as examples for controlling ngspice. These
are not meant to be "productive" programs, but just give some commented example usages of
the interface.
ng_start.exe is a MS Windows application loading ngspice.dll dynamically. All functions and
callbacks of the interface are assessed. The source code, generated with Turbo Delphi 2006,
may be found here, the binaries compiled for 32 Bit are here.
Two console applications, compilable with LINUX, CYGWIN, MINGW or MS Visual Studio,
are available here, demonstrating either linking upon start-up or loading shared ngspice dynamically at runtime. A simple feedback loop is shown in tests 3 and 4, where a device parameter
is changed upon having an output vector value crossing a limit.

19.6

ngspice parallel

The following chapter describes an offer to the advanced user and developer community. If you
are interested in evaluating the parallel and synchronized operation of several ngspice instances,
this may be one way to go. However, no ready to use implementation is available. You will
find a toolbox and some hints how to use it. Parallelization and synchronization is your task by
developing a suitable caller! And of course another major input has to come from partitioning
the circuit into suitable, loosely coupled pieces, each with its own netlist, one netlist per ngspice
instance. And you have to define the coupling between the circuit blocks. Both are not provided
by ngspice, but are again your responsibility. Both are under active research, and the toolbox
described below is an offer to join that research.

354

19.6.1

CHAPTER 19. NGSPICE AS SHARED LIBRARY OR DYNAMIC LINK LIBRARY

Go parallel!

A simple way to run several invocations of ngspice in parallel for transient simulation is to
define a caller which loads two or more ngspice shared libraries. There is one prerequisite however to do so: the shared libraries have to have different names. So compile ngspice shared
lib (see 19.1), then copy and rename the library file, e.g. ngspice.dll may become ngspice1.dll,
ngspice2.dll etc. Then dynamically load ngspice1.dll, retrieve its address, initialize it by calling
ngSpice_init() (see 19.3.2.1), then continue initialization by calling ngSpice_init_Sync() (see
19.6.2.1). An integer identification number may be sent during this step to later uniquely identify each invocation of the shared library, e.g. by having any callback use this identifier. Repeat
the sequence with ngspice2.dll and so on.
Inter-process communication and synchronization is now done by using three callback functions. To understand their interdependency, it might be useful to have a look at the transient
simulation sequence as defined in the ngspice source file dctran.c. The following listing includes the shared library option (It differs somewhat from standard procedure.) and disregards
XSPICE.
1. initialization.
2. calculation of operating point.
3. next time step: set new breakpoints (VSRC, ISRC, TRA, LTRA).
4. send simulation data to output, callback function SendData* datfcn.
5. check for autostop and other end conditions.
6. check for interrupting simulation (e.g. by bg_halt).
7. breakpoint handling (e.g. enforce breakpoint, set new small cktdelta if directly after the
breakpoint).
8. calling ngspice internal function sharedsync() which calls callback function GetSyncData* getsync with location flag loc = 0.
9. save the previous states.
10. start endless loop.
11. save cktdelta to olddelta, set new time point by adding cktdelta to ckttime.
12. new iteration of circuit at new time point, which uses callback functions GetVSRCData*
getvdat and GetISRCData* getidat to retrieve external voltage or current inputs, returns
redostep=0, if converged, redostep=1 if not converged.
13. if not converged, divide cktdelta by 8.
14. check for truncation error with all non-linear devices, if necessary create a new (smaller)
cktdelta to limit the error, optionally change integration order.
15. calling ngspice internal function sharedsync() which calls callback function GetSyncData* getsync with location flag loc = 1: as a result either goto 3 (next time step) or to
10 (loop start), depending on ngspice and user data, see next paragraph.

19.6. NGSPICE PARALLEL

355

The code of the synchronization procedure is handled in the ngspice internal function sharedsync()
and its companion user defined callback function GetSyncData* getsync. The actual setup is
as follows:
If no synchronization is asked for (GetSyncData* set to NULL), program control jumps to next
time step (3) if redostep==0, or subtracts olddelta from ckttime and jumps to loop start (9) if
redostep <> 0. This is the standard ngspice behavior.
If GetSyncData* has been set to a valid address by ngSpice_Init_Sync(), the callback function
getsync is involved. If redostep <> 0, olddelta is subtracted from ckttime, getsync is called,
either the cktdelta time suggested by ngspice is kept or the user provides his own deltatime,
and the program execution jumps to (9) for redoing the last step with the new deltatime. The
return value of getsync is not used. If redostep == 0, getsync is called. The user may keep
the deltatime suggested by ngspice or define a new value. If the user sets the return value of
getsync to 0, the program execution then jumps to next time step (3). If the return value of
getsync is 1, olddelta is subtracted from ckttime, and the program execution jumps to (9) for
redoing the last step with the new deltatime. Typically the user provided deltatime should be
smaller than the value suggested by ngspice.

19.6.2

Additional exported functions

The following functions (exported or callback) are designed to support the parallel action of
several ngspice invocations. They may be useful, however, also when only a single library is
loaded into a caller, if you want to use external voltage or current sources or play with the
advancing simulation time.
19.6.2.1

int ngSpice_Init_Sync(GetVSRCData* , GetISRCData* , GetSyncData* , int*,


void*)

Pointers to callback functions (details see 19.3.3):


GetVSRCData* callback function for retrieving a voltage source value from caller (NULL
allowed)
GetISRCData* callback function for retrieving a current source value from caller (NULL allowed)
GetSyncData* callback function for synchronization (NULL allowed)
More pointers
int* pointer to integer unique to this shared library (defaults to 0)
void* pointer to user-defined data, will not be modified, but handed over back to caller during Callback, e.g. address of calling object. If NULL is sent here, userdata info from
ngSpice_Init() will be kept, otherwise userdata will be overridden by new value from
here.

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CHAPTER 19. NGSPICE AS SHARED LIBRARY OR DYNAMIC LINK LIBRARY

19.6.2.2

bool ngSpice_SetBkpt(double)

Sets a breakpoint in ngspice, a time point which the simulator is enforced to hit during the
transient simulation. After the breakpoint time has been hit, the next delta time starts with a
small value and is ramped up again. A breakpoint should be set only when the background
thread in ngspice is not running (before the simulation has started, or after the simulation has
been paused by bg_halt). The time sent to ngspice should be larger than the current time (which
is either 0 before start or given by the callback GetSyncData (19.6.3.3). Several breakpoints
may be set.

19.6.3

Additional callback functions

19.6.3.1

typedef int (GetVSRCData)(double*, double, char*, int, void*)

double* return voltage value


double actual time
char* node name
int identification number of calling ngspice shared lib
void* return pointer received from caller

Ask for a VSRC EXTERNAL voltage value. The independent voltage source (see chapt. 4.1)
with EXTERNAL option allows to set a voltage value to the node defined in the netlist and
named here at the time returned by the simulator.

19.6.3.2

typedef int (GetISRCData)(double*, double, char*, int, void*)

double* return current value


double actual time
char* node name
int identification number of calling ngspice shared lib
void* return pointer received from caller

Ask for ISRC EXTERNAL value. The independent current source (see chapt. 4.1) with EXTERNAL option allows to set a current value to the node defined by the netlist and named here
at the time returned by the simulator.

19.6. NGSPICE PARALLEL


19.6.3.3

357

typedef int (GetSyncData)(double, double*, double, int, void*)

double actual time (ckt->CKTtime)


double* delta time (ckt->CKTdelta)
double old delta time (olddelta)
int identification number of calling ngspice shared lib
int location of call for synchronization in dctran.c
void* return pointer received from caller
Ask for new delta time depending on synchronization requirements. See 19.6.1 for an explanation.

19.6.4

Parallel ngspice example

A first example is available as a compacted 7z archive. It contains the source code of a controlling application, as well as its compiled executable and ngspice.dll (for MS Windows). As the
input circuit an inverter chain has been divided into three parts. Three ngspice shared libraries
are loaded, each simulates one partition of the circuit. Interconnections between the partitions
are provided via a callback function. The simulation time is synchronized among the three
ngspice invocations by another callback function.

358

CHAPTER 19. NGSPICE AS SHARED LIBRARY OR DYNAMIC LINK LIBRARY

Chapter 20
TCLspice
Spice historically comes as a simulation engine with a Command Line Interface. Spice engine
now can be used with friendly Graphical User Interfaces. Tclspice represent a third approach
to interfacing ngspice simulation functionality. Tclspice is nothing more than a new way of
compiling and using spice source code Spice is no longer considered as a standalone program
but as a library invoked by a TCL interpreter. It either permits direct simulation in a friendly
TCL shell (this is quite analogous to the command line interface of ngspice), or it permits the
elaboration of more complex, more specific, or more user friendly simulation programs, by
writing TCL scripts.

20.1

tclspice framework

The technical difference between the ngspice CLI interface and tclspice is that the CLI interface
is compiled as a standalone program, whereas tclspice is a shared object. Tclspice is designed to
work with tools that expand the capabilities of ngspice: TCL for the scripting and programming
language interface and BLT for data processing and display. This two tools give tclspice all of
its relevance, with the insurance that the functionality is maintained by competent people.
Making tclspice (see 20.6) produces two files: libspice.so and pkgIndex.tcl. libspice.so is the
executable binary that the TCL interpreter calls to handle spice commands. pkgIndex.tcl take
place in the TCL directory tree, providing the spice package1 to the TCL user.
BLT is a TCL package. It is quite well documented. It permits to handle mathematical vector
data structure for calculus and display, in a Tk interpreter like wish.

20.2

tclspice documentation

A detailed documentation on tclspice commands is available on the original tclspice web page.

20.3

spicetoblt

Tclspice opens its doors to TCL and BLT with a single specific command spicetoblt.
1 package

has to be understood as the TCL package

359

360

CHAPTER 20. TCLSPICE

TCLspice gets its identity in the command spice::vectoblt This command copies data computed
by the simulation engine into a tcl variable. vectoblt is composed of three words: vec, to and
blt. Vec means spice vector data. To is the English preposition, and blt is a useful tcl package
providing a vector data structure. Example:
b l t : : vector c r e a t e Iex
s p i c e : : v e c t o b l t Vex# b r a n c h I e x
Here an empty blt vector is created. It is then filled with the vector representation of the current
flowing out of source Vex. Vex#branch is native spices syntax. Iex is the name of the BLT
vector.
The reverse operation is handled by native spice commands, such as alter, let and set.

20.4

Running TCLspice

TCLspice consists of a library or a package to include in your tcl console or script:


l oa d / somepath / l i b s p i c e . so
package r e q u i r e s p i c e
Then you can execute any native spice command by preceding it with spice:: For example if
you want to source the testCapa.cir netlist, type the following:
spice : : source testCapa . c i r
s p i c e : : s p i c e t o b l t example . . .
Plotting data is not a matter of spice, but of tcl. Once the data is stored in a blt vector, it can be
plotted. Example:
b l t : : g r a p h . cimvd t i t l e " Cim = f ( Vd ) "
p a c k . cimvd
. cimvd e l e m e n t c r e a t e l i n e 1 x d a t a Vcmd y d a t a Cim
With blt::graph a plotting structure is allocated in memory. With pack it is placed into the output
window, and becomes visible. The last command, and not the least, plots the function Cim =
f(Vcmd), where Cim and Vcmd are two BLT vectors.

20.5

examples

20.5.1

Active capacitor measurement

In this crude implementation of a circuit described by Marc KODRNJA, in his PhD thesis that
I found on the Internet. This simulation outputs a graph representing the virtual capacitance
versus the command voltage. The function C = f (V ) is calculated point by point. For each

20.5. EXAMPLES

361

control voltage value, the virtual capacitance is calculated with the voltage and intensity across
the output port in a frequency simulation. A control value that should be as close to zero as
possible is calculated to assess simulation success.

20.5.1.1

Invocation:

This script can be invoked by typing wish testbench1.tcl

20.5.1.2

testbench1.tcl

This line loads the simulator capabilities

package r e q u i r e s p i c e
This is a comment (Quite useful if you intend to live with other Human beings)

# Test of v i r t u a l c a p a c i t o r e c i r c u i t
# Vary t h e c o n t r o l v o l t a g e and l o g t h e r e s u l t i n g c a p a c i t a n c e
A good example of the calling of a spice command: precede it with spice::

spice : : source " testCapa . c i r "


This reminds that any regular TCL command is of course possible

set
set
set
set

n 30 s e t dv 0 . 2
vmax [ e x p r $dv / 2 ]
vmin [ e x p r 1 * $dv / 2 ]
p a s [ e x p r $dv / $n ]

BLT vector is the structure used to manipulate data. Instantiate the vectors

blt
blt
blt
blt

::
::
::
::

vector
vector
vector
vector

create
create
create
create

Ctmp
Cim
check
Vcmd

Data is, in my coding style, plotted into graph objects. Instantiate the graph

362

CHAPTER 20. TCLSPICE

b l t : : g r a p h . cimvd t i t l e " Cim = f ( Vd ) "


b l t : : g r a p h . c h e c k v d t i t l e " Rim = f ( Vd ) "
b l t : : vector c r e a t e Iex
blt : : vector create freq
b l t : : graph . f r e q a n a l t i t l e " Analyse f r e q u e n t i e l l e "
#
# F i r s t s i m u l a t i o n : A s i m p l e AC p l o t
#
s e t v [ e x p r { $vmin + $n * $ p a s / 4 } ]
s p i c e : : a l t e r vd = $v
s p i c e : : op
s p i c e : : a c d e c 10 100 100 k
Retrieve a the intensity of the current across Vex source
s p i c e : : v e c t o b l t {Vex# b r a n c h } I e x
Retrieve the frequency at which the current have been assessed
spice : : vectoblt { frequency } freq
Room the graph in the display window
pack . f r e q a n a l
Plot the function Iex =f(V)
. f r e q a n a l e l e m e n t c r e a t e l i n e 1 x d a t a f r e q y d a t a I e x
#
# Second s i m u l a t i o n : C a p a c i t a n c e v e r s u s v o l t a g e c o n t r o l
# f o r { s e t i 0} { [ e x p r $n $ i ] } { i n c r i }
#
{ s e t v [ e x p r { $vmin + $ i * $ p a s } ]
s p i c e : : a l t e r vd = $v
s p i c e : : op s p i c e : : a c d e c 10 100 100 k
Image capacitance is calculated by spice, instead of TCL there is no objective reason
s p i c e : : l e t Cim = r e a l ( mean ( Vex# b r a n c h / ( 2 * P i * i * f r e q u e n c y * (V(5) V ( 6 ) ) ) ) )
s p i c e : : v e c t o b l t Cim Ctmp
Build function vector point by point
Cim a p p e n d $Ctmp ( 0 : end )
Build a control vector to check simulation success

20.5. EXAMPLES

363

s p i c e : : l e t e r r = r e a l ( mean ( s q r t ( ( Vex# b r a n c h
( 2 * P i * i * f r e q u e n c y * Cim *V(5) V ( 6 ) ) ) ^ 2 ) ) )
s p i c e : : v e c t o b l t e r r Ctmp c h e c k
a p p e n d $Ctmp ( 0 : end )
Build abscissa vector
FALTA ALGO . . . Vcmd a p p e n d $v }
Plot
p a c k . cimvd
. cimvd e l e m e n t c r e a t e l i n e 1 x d a t a Vcmd y d a t a Cim
pack . checkvd
. c h e c k v d e l e m e n t c r e a t e l i n e 1 x d a t a Vcmd y d a t a c h e c k

20.5.2

Optimization of a linearization circuit for a Thermistor

This example is both the first and the last optimization program I wrote for an electronic circuit.
It is far from perfect.
The temperature response of a CTN is exponential. It is thus nonlinear. In a battery charger
application floating voltage varies linearly with temperature. A TL431 voltage reference sees
its output voltage controlled by two resistors (r10, r12) and a thermistor (r11). The simulation
is run at a given temperature. The thermistor is modeled in spice by a regular resistor. Its
resistivity is assessed by the TCL script. It is set with a spice::alter command before running
the simulation. This script uses an iterative optimization approach to try to converge to a set
of two resistor values which minimizes the error between the expected floating voltage and the
TL431 output.

20.5.2.1

Invocation:

This script can be executed by the user by simply executing the file in a terminal.
. / testbench3 . tcl
Two issues are important to point out2 :
2 For

those who are really interested in optimizing circuits: Some parameters are very important for quick and
correct convergence. The optimizer walks step by step to a local minimum of the cost function you define. Starting
from an initial vector YOU provide, it converges step by step. Consider trying another start vector if the result is
not the one you expected.
The optimizer will carry on walking until it reaches a vector which resulting cost is smaller than the target cost
YOU provide it. You will also provide a maximum iteration count in case the target can not be achieved. Balance
your time, specifications, and every other parameters. For a balance between quick and accurate convergence
adjust the "factor" variable, at the beginning of minimumSteepestDescent in the file differentiate.tcl.

364

CHAPTER 20. TCLSPICE


During optimization loop, graphical display of the current temperature response is not yet
possible and I dont know why. Each time a simulation is performed, some memory is
allocated for it.
The simulation result remains in memory until the libspice library is unloaded (typically:
when the tcl script ends) or when a spice::clean command is performed. In this kind of
simulation, not cleaning the memory space will freeze your computer and youll have to
restart it. Be aware of that.

20.5.2.2

testbench3.tcl

This calls the shell sh who then runs wish with the file itself.

# ! / bin / sh
# WishFix \
e x e c w i s h " $0 " $ {1+"$@" }
#
#
#
Regular package for simulation

package r e q u i r e s p i c e
Here the important line is source differentiate.tcl which contains optimization library

source d i f f e r e n t i a t e . t c l
Generates a temperature vector

proc t e m p e r a t u r e s _ c a l c { t e m p _ i n f temp_sup p o i n t s } {
s e t t s t e p [ expr " ( $temp_sup $temp_inf ) / $ p o i n t s " ]
s e t t $temp_inf
s e t temperatures ""
for { set i 0 } { $i < $points } { incr i } {
s e t t [ expr { $t + $ t s t e p } ]
set temperatures " $temperatures $t "
}
return $temperatures }
generates thermistor resistivity as a vector, typically run: thermistance_calc res B [ temperatures_calc temp_inf temp_sup points ]

20.5. EXAMPLES

365

proc t h e r m i s t a n c e _ c a l c { res B p o i n t s } {
s e t t z e r o 273.15
s e t t r e f 25
s e t thermistance ""
foreach t $points {
s e t r e s _ t e m p [ e x p r " $ r e s * exp ( $B * ( 1 / ( $ t z e r o + $ t ) 1
/ ( $tzero + $tref ) ) ) " ]
s e t t h e r m i s t a n c e " $thermistance $res_temp "
}
return $thermistance }
generates the expected floating value as a vector, typically run: tref_calc res B [ temperatures_calc temp_inf temp_sup points ]

proc t r e f _ c a l c { p o i n t s } {
s e t t r e f ""
foreach t $points {
s e t t r e f " $ t r e f [ e x p r " 6 * ( 2 . 2 7 5 0 . 0 0 5 * ( $ t 2 0 ) ) 9" ] "
}
return $tref }
In the optimization algorithm, this function computes the effective floating voltage at the given
temperature.

### NOTE :
### As component v a l u e s a r e m o d i f i e d by a s p i c e : : a l t e r
Component v a l u e s c a n be c o n s i d e r e d a s g l o b a l v a r i a b l e .
### R10 and R12 a r e n o t p a s s e d t o i t e r a t i o n f u n c t i o n b e c a u s e i t
i s e x p e c t e d t o be c o r r e c t , i e t o h a v e b e e n m o d i f i e d s o o n
before proc i t e r a t i o n { t } { s e t t z e r o 273.15 s pi ce : : a l t e r
r 1 1 = [ t h e r m i s t a n c e _ c a l c 10000 3900 $ t ]
# T e m p e r a t u r e s i m u l a t i o n o f t e n c r a s h e s . Comment i t o u t . . .
# s p i c e : : s e t temp = [ e x p r " $ t z e r o + $ t " ]
s p i c e : : op
spice : : v e c t o b l t vref_temp tref_tmp
###NOTE :
### As t h e l i b r a r y i s e x e c u t e d o n c e f o r t h e whole s c r i p t
e x e c u t i o n , i t i s i m p o r t a n t t o manage t h e memory
### and r e g u l a r l y d e s t r o y u n u s e d d a t a s e t . The d a t a computed
h e r e w i l l n o t be r e u s e d . C l e a n i t
spice : : destroy a l l r e t u r n [ tref_tmp range 0 0 ] }
This is the cost function optimization algorithm will try to minimize. It is a 2-norm (Euclidean
norm) of the error across the temperature range [-25:75]C.

366

CHAPTER 20. TCLSPICE

proc c o s t { r10 r12 } {


t r e f _ b l t length 0
s p i c e : : a l t e r r10 = $r10
s p i c e : : a l t e r r12 = $r12
foreach point [ t e m p e r a t u r e s _ b l t range 0 [ expr " [
t e m p e r a t u r e s _ b l t l e n g t h ] 1" ] ] {
t r e f _ b l t append [ i t e r a t i o n $ p o i n t ]
}
s e t r e s u l t [ b l t : : v e c t o r e x p r " 1000 * sum ( ( t r e f _ b l t
e x p e c t e d _ b l t ) ^2 ) " ]
d is p_ cu rv e $r10 $r12
return $result }
This function displays the expected and effective value of the voltage, as well as the r10 and r12
resistor values
proc disp_curve { r10 r12 } { . g c o n f i g u r e t i t l e " Valeurs
o p t i m a l e s : R10 = $ r 1 0 R12 = $ r 1 2 " }
Main loop starts here
#
# Optimization
# blt : : vector create tref_tmp
blt : : vector create t r e f _ b l t
blt : : vector create expected_blt
blt : : vector create temperatures_blt temperatures_blt
a p p e n d [ t e m p e r a t u r e s _ c a l c 25 75 30 ] e x p e c t e d _ b l t
append [ t r e f _ c a l c [ t e m p e r a t u r e s _ b l t range 0 [ expr " [
t e m p e r a t u r e s _ b l t l e n g t h ] 1" ] ] ]
b l t : : graph . g
p a c k . g s i d e t o p f i l l b o t h e x p a n d t r u e
. g e l e m e n t c r e a t e r e a l p i x e l s 4 x d a t a t e m p e r a t u r e s _ b l t y d a t a
tref_blt
. g e l e m e n t c r e a t e e x p e c t e d f i l l r e d p i x e l s 0 d a s h e s d o t
x d a t a t e m p e r a t u r e s _ b l t y d a t a e x p e c t e d _ b l t
Source the circuit and optimize it, result is retrieved in r10r12 variable and affected to r10 and
r12 with a regular expression. A bit ugly.
s p i c e : : s o u r c e FB14 . c i r
s e t r 1 0 r 1 2 [ : : math : : o p t i m i z e : : m i n i m u m S t e e p e s t D e s c e n t c o s t {
10000 10000 } 0 . 1 50 ]
regexp {([0 9.]*) ([0 9.]*) } $r10r12 r10r12 r10 r12
Outputs optimization result

20.5. EXAMPLES

367

#
# Results
# s p i c e : : a l t e r r10 = $r10
s p i c e : : a l t e r r12 = $r12
foreach point [ t e m p e r a t u r e s _ b l t range 0 [ expr " [
t e m p e r a t u r e s _ b l t l e n g t h ] 1" ] ] {
t r e f _ b l t append [ i t e r a t i o n $ p o i n t ]
}
d is p_ cu rv e $r10 $r12

20.5.3

Progressive display

This example is quite simple but it is very interesting. It displays a transient simulation result
on the fly. You may now be familiar with most of the lines of this script. It uses the ability of
BLT objects to automatically update. When the vector data is modified, the strip-chart display
is modified accordingly.

20.5.3.1

testbench2.tcl

# ! / bin / sh
# WishFix \
e x e c w i s h f " $0 " $ {1+"$@" }
###
p a c k a g e r e q u i r e BLT p a c k a g e r e q u i r e s p i c e
this avoids to type blt:: before the blt class commands

namespace i m p o r t b l t : : *
wm t i t l e . " V e c t o r T e s t s c r i p t "
wm g e o m e t r y . 800 x600 +40+40 p a c k p r o p a g a t e . f a l s e
A strip chart with labels but without data is created and displayed (packed)

368

CHAPTER 20. TCLSPICE

stripchart . chart
p a c k . c h a r t s i d e t o p f i l l b o t h e x p a n d t r u e
. c h a r t a x i s c o n f i g u r e x t i t l e " Time " s p i c e : : s o u r c e e x a m p l e . c i r
s p i c e : : bg
r u n a f t e r 1000 v e c t o r
c r e a t e a0 v e c t o r
c r e a t e b0 v e c t o r r y
c r e a t e a1 v e c t o r
c r e a t e b1 v e c t o r
create stime
p r o c b l t u p d a t e {} {
puts [ spice : : spice_data ]
s p i c e : : s p i c e t o b l t a0 a0
s p i c e : : s p i c e t o b l t b0 b0
s p i c e : : s p i c e t o b l t a1 a1
s p i c e : : s p i c e t o b l t b1 b1
spice : : s p i c e t o b l t time stime
a f t e r 100 b l t u p d a t e }
b l t u p d a t e . c h a r t e l e m e n t c r e a t e a0 c o l o r r e d x d a t a s t i m e y d a t a a0
. c h a r t e l e m e n t c r e a t e b0 c o l o r b l u e x d a t a s t i m e y d a t a b0
. c h a r t e l e m e n t c r e a t e a1 c o l o r y e l l o w x d a t a s t i m e y d a t a a1
. c h a r t e l e m e n t c r e a t e b1 c o l o r b l a c k x d a t a s t i m e y d a t a b1

20.6

Compiling

20.6.1

LINUX

Get tcl8.4 from your distribution. You will need the blt plotting package (compatible to the old
tcl 8.4 only) from here. See also the actual blt wiki.
./configure --with-tcl ..
make
sudo make install

20.6.2

MS Windows

Can be done, but is tedious. I will describe my procedure on Windows 7, 64 Bit Home Edition.
20.6.2.1

Downloads

download tcl8.6b2-src.zip from http://www.tcl.tk/software/tcltk/download.html


download tk8.6b2-src.zip
download blt from http://ngspice.sourceforge.net/experimental/blt2.4z.7z
expand all to d:\software

20.7. MS WINDOWS 32 BIT BINARIES


20.6.2.2

369

Tcl

double click on D:\software\tcl8.6b2\win\tcl.dsw


convert to MS visual Studio 2008 project
select release or debug
create tcl as tcl86t.dll.
20.6.2.3

Tk

edit D:\software\tk8.6b2\win\buildall.vc.bat
line 31 to
call "C:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\vcvarsall.bat"
line 53 to
if "%TCLDIR%" == "" set TCLDIR=..\..\tcl8.6b2
open cmd window
cd to
d:\software\tk8.6b2\win>
then
d:\software\tk8.6b2\win> buildall.vc.bat debug
tk will be made as tk86t.dll, in addition wish86t.exe is generated.
20.6.2.4

blt

blt sorce files have been downloaded from the blt web page and modified for compatibility with
TCL8.6. To facilitate making blt24.dll, the modified source code is available as a 7z compressed
file, including a project file for MS Visual Studio 2008.
20.6.2.5

tclspice

ngspice is compiled and linked into a dll called spice.dll which may be loaded by wish86t.exe.
MS Visual Studio 2008 is the compiler applied. A project file may be downloaded as a 7z
compressed file. Expand this file in the ngspice main directory. The links to tcl and tk are
hard-coded, so both have to be installed in the places described above (d:\software\...). spice.dll
may be generated in Debug, Release or ReleaseOMP mode.

20.7

MS Windows 32 Bit binaries

You may download the compiled binaries, including tcl, tk, blt and tclspice, plus the examples,
slightly modified, from http://ngspice.sourceforge.net/experimental/tclspice-25.7z.

370

CHAPTER 20. TCLSPICE

Chapter 21
Example Circuits
This section starts with an ngspice example to walk you through the basic features of ngspice
using its command line user interface. The operation of ngspice will be illustrated through
several examples (chapters 20.1 to 20.7).
The first example uses the simple one-transistor amplifier circuit illustrated in Figure 21.1. This
circuit is constructed entirely with ngspice compatible devices and is used to introduce basic
concepts, including:

Invoking the simulator:


Running simulations in different analysis modes
Printing and plotting analog results
Examining status, including execution time and memory usage
Exiting the simulator

The remainder of the section (from chapter 21.2 onwards) lists several circuits, which have been
accompanying any ngspice distribution, and may be regarded as the classical SPICE circuits.

21.1

AC coupled transistor amplifier

The circuit shown in Figure 21.1 is a simple one-transistor amplifier. The input signal is amplified with a gain of approximately -(Rc/Re) = -(3.9K/1K) = -3.9. The circuit description file for
this example is shown below.

371

372

CHAPTER 21. EXAMPLE CIRCUITS

Figure 21.1: Transistor Amplifier Simulation Example


Example:
A B e r k e l e y SPICE3 c o m p a t i b l e c i r c u i t
*
* T h i s c i r c u i t c o n t a i n s o n l y B e r k e l e y SPICE3 c o m p o n e n t s .
*
* The c i r c u i t i s an AC c o u p l e d t r a n s i s t o r a m p l i f i e r w i t h
* a s i n e w a v e i n p u t a t node " 1 " , a g a i n o f a p p r o x i m a t e l y 3.9 ,
* and o u t p u t on node " c o l l " .
*
. t r a n 1 e5 2 e3
*
vcc vcc 0 12.0
v i n 1 0 0 . 0 a c 1 . 0 s i n ( 0 1 1k )
c c o u p l e 1 b a s e 10 uF
r b i a s 1 v c c b a s e 100 k
r b i a s 2 b a s e 0 24 k
q1 c o l l b a s e e m i t g e n e r i c
r c o l l e c t o r vcc c o l l 3 . 9 k
r e m i t t e r e m i t 0 1k
*
. model g e n e r i c npn
*
. end
To simulate this circuit, move into a directory under your user account and copy the file xspice_c1.cir
from directory /examples/xspice/. This file stems from the original XSPICE introduction,

21.1. AC COUPLED TRANSISTOR AMPLIFIER

373

therefore its name, but you do not need installing the XSPICE option to run it.
$ cp /examples/xspice/xspice_c1.cir xspice_c1.cir
Now invoke the simulator on this circuit as follows:
$ ngspice xspice_c1.cir
After a few moments, you should see the ngspice prompt:
ngspice 1 ->
At this point, ngspice has read-in the circuit description and checked it for errors. If any errors
had been encountered, messages describing them would have been output to your terminal.
Since no messages were printed for this circuit, the syntax of the circuit description was correct.
To see the circuit description read by the simulator you can issue the following command:
ngspice 1 -> listing
The simulator shows you the circuit description currently in memory:
a berkeley spice3 compatible circuit
1 : a berkeley spice3 compatible circuit
2 : .global gnd
10 : .tran 1e-5 2e-3
12 : vcc vcc 0 12.0
13 : vin 1 0 0.0 ac 1.0 sin(0 1 1k)
14 : ccouple 1 base 10uf
15 : rbias1 vcc base 100k
16 : rbias2 base 0 24k
17 : q1 coll base emit generic
18 : rcollector vcc coll 3.9k
19 : remitter emit 0 1k
21 : .model generic npn
24 : .end
The title of this circuit is A Berkeley SPICE3 compatible circuit. The circuit description
contains a transient analysis control command .TRAN 1E-5 2E-3 requesting a total simulated
time of 2ms with a maximum time-step of 10us. The remainder of the lines in the circuit
description describe the circuit of Figure 21.1.
Now, execute the simulation by entering the run command:
ngspice 1 -> run

374

CHAPTER 21. EXAMPLE CIRCUITS

The simulator will run the simulation and when execution is completed, will return with the
ngspice prompt. When the prompt returns, issue the rusage command again to see how much
time and memory has been used now.

To examine the results of this transient analysis, we can use the plot command. First we will
plot the nodes labeled 1 and base.
ngspice 2 -> plot v(1) base
The simulator responds by displaying an X Window System plot similar to that shown in Figure
21.2.

Figure 21.2: node 1 and node base versus time


Notice that we have named one of the nodes in the circuit description with a number (1),
while the others are words (base). This was done to illustrate ngspices special requirements
for plotting nodes labeled with numbers. Numeric labels are allowed in ngspice for backwards
compatibility with SPICE2. However, they require special treatment in some commands such
as plot. The plot command is designed to allow expressions in its argument list in addition
to names of results data to be plotted. For example, the expression plot (base - 1) would
plot the result of subtracting 1 from the value of node base.
If we had desired to plot the difference between the voltage at node base and node 1, we
would need to enclose the node name 1 in the construction v( ) producing a command such
as plot (base - v(1)).
Now, issue the following command to examine the voltages on two of the internal nodes of the
transistor amplifier circuit:

21.1. AC COUPLED TRANSISTOR AMPLIFIER

375

ngspice 3 -> plot vcc coll emit


The plot shown in Figure 21.3 should appear. Notice in the circuit description that the power
supply voltage source and the node it is connected to both have the name "vcc". The plot
command above has plotted the node voltage "vcc". However, it is also possible to plot branch
currents through voltage sources in a circuit. ngspice always adds the special suffix "#branch"
to voltage source names. Hence, to plot the current into the voltage source named "vcc", we
would use a command such as plot vcc#branch.

Figure 21.3: VCC, Collector and Emitter Voltages


Now lets run a simple DC simulation of this circuit and examine the bias voltages with the
"print" command. One way to do this is to quit the simulator using the "quit" command, edit
the input file to change the ".tran" line to ".op" (for operating point analysis), re-invoke the
simulator, and then issue the "run" command. However, ngspice allows analysis mode changes
directly from the ngspice prompt. All that is required is to enter the control line, e.g. op (without
the leading "."). ngspice will interpret the information on the line and start the new analysis run
immediately, without the need to enter a new "run" command.
To run the DC simulation of the transistor amplifier, issue the following command:
ngspice 4 -> op
After a moment the ngspice prompt returns. Now issue the "print" command to examine the
emitter, base, and collector DC bias voltages.
ngspice 5 -> print emit base coll
ngspice responds with:
emit = 1.293993e+00 base = 2.074610e+00 coll = 7.003393e+00

376

CHAPTER 21. EXAMPLE CIRCUITS

To run an AC analysis, enter the following command:

ngspice 6 -> ac dec 10 0.01 100

This command runs a small-signal swept AC analysis of the circuit to compute the magnitude
and phase responses. In this example, the sweep is logarithmic with "decade" scaling, 10 points
per decade, and lower and upper frequencies of 0.01 Hz and 100 Hz. Since the command
sweeps through a range of frequencies, the results are vectors of values and are examined with
the plot command. Issue to the following command to plot the response curve at node "coll":

ngspice 7 -> plot coll

This plot shows the AC gain from input to the collector. (Note that our input source in the circuit
description "vin" contained parameters of the form "AC 1.0" designating that a unit-amplitude
AC signal was applied at this point.) For plotting data from an AC analysis, ngspice chooses
automatically a logarithmic scaling for the frequency (x) axis.
To produce a more traditional "Bode" gain phase plot (again with automatic logarithmic scaling
on the frequency axis), we use the expression capability of the "plot" command and the built-in
Nutmeg functions db( ) and ph( ):

ngspice 8 -> plot db(coll) ph(coll)

The last analysis supported by ngspice is a swept DC analysis. To perform this analysis, issue
the following command:

ngspice 9 -> dc vcc 0 15 0.1

This command sweeps the supply voltage "vcc" from 0 to 15 volts in 0.1 volt increments. To
plot the results, issue the command:

ngspice 10 -> plot emit base coll

Finally, to exit the simulator, use the "quit" command, and you will be returned to the operating
system prompt.

ngspice 11 -> quit

So long.

21.2. DIFFERENTIAL PAIR

21.2

377

Differential Pair

The following deck determines the dc operating point of a simple differential pair. In addition,
the ac small-signal response is computed over the frequency range 1Hz to 100MEGHz.
Example:
SIMPLE DIFFERENTIAL PAIR
VCC 7 0 12
VEE 8 0 12
VIN 1 0 AC 1
RS1 1 2 1K
RS2 6 0 1K
Q1 3 2 4 MOD1
Q2 5 6 4 MOD1
RC1 7 3 10K
RC2 7 5 10K
RE 4 8 10K
.MODEL MOD1 NPN BF=50 VAF=50 I S = 1 . E12 RB=100 CJC = . 5 PF TF = . 6NS
. TF V( 5 ) VIN
. AC DEC 10 1 100MEG
. END

21.3

MOSFET Characterization

The following deck computes the output characteristics of a MOSFET device over the range
0-10V for VDS and 0-5V for VGS.
Example:
MOS OUTPUT CHARACTERISTICS
. OPTIONS NODE NOPAGE
VDS 3 0
VGS 2 0
M1 1 2 0 0 MOD1 L=4U W=6U AD=10P AS=10P
* VIDS MEASURES ID , WE COULD HAVE USED VDS, BUT ID WOULD BE NEGATIVE
VIDS 3 1
.MODEL MOD1 NMOS VTO=2 NSUB= 1 . 0 E15 UO=550
. DC VDS 0 10 . 5 VGS 0 5 1
. END

21.4

RTL Inverter

The following deck determines the dc transfer curve and the transient pulse response of a simple
RTL inverter. The input is a pulse from 0 to 5 Volts with delay, rise, and fall times of 2ns and
a pulse width of 30ns. The transient interval is 0 to 100ns, with printing to be done every
nanosecond.

378

CHAPTER 21. EXAMPLE CIRCUITS

Example:
SIMPLE RTL INVERTER
VCC 4 0 5
VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS
RB 1 2 10K
Q1 3 2 0 Q1
RC 3 4 1K
.MODEL Q1 NPN BF 20 RB 100 TF . 1 NS CJC 2PF
. DC VIN 0 5 0 . 1
. TRAN 1NS 100NS
. END

21.5

Four-Bit Binary Adder (Bipolar)

The following deck simulates a four-bit binary adder, using several subcircuits to describe various pieces of the overall circuit.

Example:
ADDER 4 BIT ALLNANDGATE BINARY ADDER
*** SUBCIRCUIT DEFINITIONS
. SUBCKT NAND 1 2 3 4
* NODES : INPUT ( 2 ) , OUTPUT, VCC
Q1 9 5 1 QMOD
D1CLAMP 0 1 DMOD
Q2 9 5 2 QMOD
D2CLAMP 0 2 DMOD
RB 4 5 4K
R1 4 6 1 . 6K
Q3 6 9 8 QMOD
R2 8 0 1K
RC 4 7 130
Q4 7 6 10 QMOD
DVBEDROP 10 3 DMOD
Q5 3 8 0 QMOD
. ENDS NAND

21.5. FOUR-BIT BINARY ADDER (BIPOLAR)

379

Continue 4 Bit adder :


. SUBCKT ONEBIT 1 2 3 4 5 6
* NODES : INPUT ( 2 ) , CARRYIN , OUTPUT, CARRYOUT, VCC
X1 1 2 7 6 NAND
X2 1 7 8 6 NAND
X3 2 7 9 6 NAND
X4 8 9 10 6 NAND
X5 3 10 11 6 NAND
X6 3 11 12 6 NAND
X7 10 11 13 6 NAND
X8 12 13 4 6 NAND
X9 11 7 5 6 NAND
. ENDS ONEBIT
. SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
* NODES : INPUT BIT0 ( 2 ) / BIT1 ( 2 ) , OUTPUT BIT0 / BIT1 ,
* CARRYIN , CARRYOUT, VCC
X1 1 2 7 5 10 9 ONEBIT
X2 3 4 10 6 8 9 ONEBIT
. ENDS TWOBIT
. SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* NODES : INPUT BIT0 ( 2 ) / BIT1 ( 2 ) / BIT2 ( 2 ) / BIT3 ( 2 ) ,
* OUTPUT BIT0 / BIT1 / BIT2 / BIT3 , CARRYIN , CARRYOUT, VCC
X1 1 2 3 4 9 10 13 16 15 TWOBIT
X2 5 6 7 8 11 12 16 14 15 TWOBIT
. ENDS FOURBIT
*** DEFINE NOMINAL CIRCUIT
.MODEL DMOD D
.MODEL QMOD NPN( BF=75 RB=100 CJE=1PF CJC=3PF )
VCC 99 0 DC 5V
VIN1A 1 0 PULSE ( 0 3 0 10NS 10NS 10NS 50NS )
VIN1B 2 0 PULSE ( 0 3 0 10NS 10NS 20NS 100NS )
VIN2A 3 0 PULSE ( 0 3 0 10NS 10NS 40NS 200NS )
VIN2B 4 0 PULSE ( 0 3 0 10NS 10NS 80NS 400NS )
VIN3A 5 0 PULSE ( 0 3 0 10NS 10NS 160NS 800NS )
VIN3B 6 0 PULSE ( 0 3 0 10NS 10NS 320NS 1600NS )
VIN4A 7 0 PULSE ( 0 3 0 10NS 10NS 640NS 3200NS )
VIN4B 8 0 PULSE ( 0 3 0 10NS 10NS 1280NS 6400NS )
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
RBIT0 9 0 1K
RBIT1 10 0 1K
RBIT2 11 0 1K
RBIT3 12 0 1K
RCOUT 13 0 1K
*** (FOR THOSE WITH MONEY (AND MEMORY) TO BURN)
. TRAN 1NS 6400NS
. END

380

21.6

CHAPTER 21. EXAMPLE CIRCUITS

Four-Bit Binary Adder (MOS)

The following deck simulates a four-bit binary adder, using several subcircuits to describe various pieces of the overall circuit.

Example:
ADDER 4 BIT ALLNANDGATE BINARY ADDER
*** SUBCIRCUIT DEFINITIONS
. SUBCKT NAND i n 1 i n 2 o u t VDD
* NODES : INPUT ( 2 ) , OUTPUT, VCC
M1 o u t i n 2 Vdd Vdd p1 W= 7 . 5 u L = 0 . 3 5 u pd = 1 3 . 5 u ad = 2 2 . 5 p p s = 1 3 . 5 u a s = 2 2 . 5 p
M2 n e t . 1 i n 2 0 0 n1
W=3u
L = 0 . 3 5 u pd =9u
ad =9p
p s =9u
a s =9p
M3 o u t i n 1 Vdd Vdd p1 W= 7 . 5 u L = 0 . 3 5 u pd = 1 3 . 5 u ad = 2 2 . 5 p p s = 1 3 . 5 u a s = 2 2 . 5 p
M4 o u t i n 1 n e t . 1 0 n1 W=3u
L = 0 . 3 5 u pd =9u
ad =9p
p s =9u
a s =9p
. ENDS NAND
. SUBCKT ONEBIT 1 2 3 4 5 6 AND
X2
1 7 8 6
NAND
X3
2 7 9 6
NAND
X4
8 9 10 6
NAND
X5
3 10 11 6
NAND
X6
3 11 12 6
NAND
X7 10 11 13 6
NAND
X8 12 13 4 6
NAND
X9 11 7 5 6
NAND
. ENDS ONEBIT
. SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
* NODES : INPUT BIT0 ( 2 ) / BIT1 ( 2 ) , OUTPUT BIT0 / BIT1 ,
CARRYIN , CARRYOUT, VCC
*
X1
1 2 7 5 10 9
ONEBIT
X2
3 4 10 6 8 9
ONEBIT
. ENDS TWOBIT
. SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
*NODES : INPUT BIT0 ( 2 ) / BIT1 ( 2 ) / BIT2 ( 2 ) / BIT3 ( 2 ) ,
OUTPUT BIT0 / BIT1 / BIT2 / BIT3 , CARRYIN ,
*
CARRYOUT, VCC
*
X1
1 2 3 4 9 10 13 16 15
TWOBIT
X2
5 6 7 8 11 12 16 14 15
TWOBIT
. ENDS FOURBIT

21.7. TRANSMISSION-LINE INVERTER

381

Continue 4 Bit adder MOS:


*** POWER
VCC
99 0
DC 3 . 3V
*** INPUTS
VIN1A 1 0
DC 0 PULSE ( 0
VIN1B 2 0
DC 0 PULSE ( 0
VIN2A 3 0
DC 0 PULSE ( 0
VIN2B 4 0
DC 0 PULSE ( 0
VIN3A 5 0
DC 0 PULSE ( 0
VIN3B 6 0
DC 0 PULSE ( 0
VIN4A 7 0
DC 0 PULSE ( 0
VIN4B 8 0
DC 0 PULSE ( 0
DEFINE
NOMINAL
CIRCUIT
***
X1
1 2 3 4 5 6 7

3
3
3
3
3
3
3
3

0
0
0
0
0
0
0
0
8

5NS
5NS
5NS
5NS
5NS
5NS
5NS
5NS

5NS
20NS
50NS )
5NS
30NS 100NS )
5NS
50NS 200NS )
5NS
90NS 400NS )
5NS 170NS 800NS )
5NS 330NS 1600NS )
5NS 650NS 3200NS )
5NS 1290NS 6400NS )

9 10 11 12

0 13 99 FOURBIT

. option acct
. s a v e V( 1 ) V( 2 ) V( 3 ) V( 4 ) V( 5 ) V( 6 ) V( 7 ) V( 8 ) ; INPUTS
. s a v e V( 9 ) V( 1 0 ) V( 1 1 ) V( 1 2 ) V( 1 3 ) ; OUTPUTS
. TRAN 1NS 6400NS
* u s e BSIM3 model w i t h d e f a u l t p a r a m e t e r s
. model n1 nmos l e v e l =49 v e r s i o n = 3 . 3 . 0
. model p1 pmos l e v e l =49 v e r s i o n = 3 . 3 . 0
. END

21.7

Transmission-Line Inverter

The following deck simulates a transmission-line inverter. Two transmission-line elements are
required since two propagation modes are excited. In the case of a coaxial line, the first line
(T1) models the inner conductor with respect to the shield, and the second line (T2) models the
shield with respect to the outside world.
Example:
TRANSMISSIONLINE INVERTER
V1 1 0 PULSE ( 0 1 0 0 . 1N)
R1 1 2 50
X1 2 0 0 4 TLINE
R2 4 0 50
. SUBCKT TLINE 1 2 3 4
T1 1 2 3 4 Z0=50 TD= 1 . 5NS
T2 2 0 4 0 Z0=100 TD=1NS
. ENDS TLINE
. TRAN 0 . 1 NS 20NS
. END

382

CHAPTER 21. EXAMPLE CIRCUITS

Chapter 22
Statistical circuit analysis

22.1

Introduction

Real circuits do not operate in a world with fixed values of device parameters, power supplies
and environmental data. Even if a ngspice output offers 5 digits or more of precision, this
should not mislead you thinking that your circuits will behave exactly the same. All physical
parameters influencing a circuit (e.g. MOS Source/drain resistance, threshold voltage, transconductance) are distributed parameters, often following a Gaussian distribution with a mean value
and a standard deviation .
To obtain circuits operating reliably under varying parameters, it might be necessary to simulate
them taking certain parameter spreads into account. ngspice offers several methods supporting
this task. A powerful random number generator is working in the background. Its seed value
is derived from the process id upon start-up of ngspice. If you need reproducible random numbers, you may start ngspice setting the command set rndseed=<int value> into spinit or
.spiceinit. The following three chapters offer a short introduction to the statistical methods
available in ngspice. The diversity of approaches stems from historical reasons, and from some
efforts to make ngspice compatible to other simulators.

22.2

Using random param(eters)

The ngspice frontend (with its numparam parser) contains the .param (see chapt. 2.8.1) and
.func (see chapt. 2.9) commands. Among the built-in functions supported (see 2.8.5) you will
find the following statistical functions:

383

384

CHAPTER 22. STATISTICAL CIRCUIT ANALYSIS

Built-in function
gauss(nom, rvar, sigma)

agauss(nom, avar, sigma)

unif(nom, rvar)
aunif(nom, avar)
limit(nom, avar)

Notes
nominal value plus variation drawn from Gaussian
distribution with mean 0 and standard deviation rvar
(relative to nominal), divided by sigma
nominal value plus variation drawn from Gaussian
distribution with mean 0 and standard deviation avar
(absolute), divided by sigma
nominal value plus relative variation (to nominal)
uniformly distributed between +/-rvar
nominal value plus absolute variation uniformly distributed
between +/-avar
nominal value +/-avar, depending on random number in
[-1, 1[ being > 0 or < 0

The frontend parser evaluates all .param or .func statements upon start-up of ngspice, before
the circuit is evaluated. The parameters aga, aga2, lim obtain their numerical values once. If the
random function appears in a device card (e.g. v11 11 0 agauss(1,2,3)), a new random
number is generated.
Random number example using parameters:
* random number tests
. param aga = agauss (1 ,2 ,3)
. param aga2 = 2* aga
. param lim = limit (0 ,1.2)
. func rgauss (a ,b , c ) 5* agauss (a ,b , c )
* always same value as defined above
v1 1 0 lim
v2 2 0 lim
* may be a different value
v3 3 0 limit (0 ,1.2)
* always new random values
v11 11 0 agauss (1 ,2 ,3)
v12 12 0 agauss (1 ,2 ,3)
v13 13 0 agauss (1 ,2 ,3)
* same value as defined above
v14 14 0 aga
v15 15 0 aga
v16 16 0 aga2
* using . func , new random values
v17 17 0 rgauss (0 ,2 ,3)
v18 18 0 rgauss (0 ,2 ,3)
. op
. control
run
print v (1) v (2) v (3) v (11) v (12) v (13)
print v (14) v (15) v (16) v (17) v (18)
. endc
. end

22.3. BEHAVIORAL SOURCES (B, E, G, R, L, C) WITH RANDOM CONTROL

385

So v1, v2, and v3 will get the same value, whereas v4 might differ. v11, v12, and v13 will get
different values, v14, v15, and v16 will obtain the values set above in the .param statements.
.func will start its replacement algorithm, rgauss(a,b,c) will be replaced everywhere by
5*agauss(a,b,c).
Thus device and model parameters may obtain statistically distributed starting values. You
simply set a model parameter not to a fixed numerical value, but insert a parameter instead,
which may consist of a token defined in a .param card, by calling .func or by using a builtin function, including the statistical functions described above. The parameter values will be
evaluated once immediately after reading the input file.

22.3

Behavioral sources (B, E, G, R, L, C) with random control

All sources listed in the section header may contain parameters, which will be evaluated before
simulation starts, as described in the previous section (22.2). In addition the nonlinear voltage
or current sources (B-source, 5) as well as their derivatives E and G, but also the behavioral R,
L, and C may be controlled during simulation by a random independent voltage source V with
TRRANDOM option (chapt. 4.1.8).
An example circuit, a Wien bridge oscillator from input file /examples/Monte_Carlo/OpWien.sp
is distributed with ngspice or available at Git. The two frequency determining pairs of R and
C are varied statistically using four independent Gaussian voltage sources as the controlling
units. An excerpt of this command sequence is shown below. The total simulation time ttime
is divided into 100 equally spaced blocks. Each block will get a new set of control voltages,
e.g. VR2, which is Gaussian distributed, mean 0 and absolute deviation 1. The resistor value
is calculated with 10% spread, the factor 0.033 will set this 10% to be a deviation of 1 sigma
from nominal value.
Examples for control of a behavioral resistor:
* random r e s i s t o r
. param r e s = 10 k
. param t t i m e =12000m
. param v a r i a =100
. param t t i m e 1 0 = t t i m e / v a r i a
* random c o n t r o l v o l t a g e ( G a u s s i a n d i s t r i b u t i o n )
VR2 r 2 0 dc 0 t r r a n d o m ( 2 t t i m e 1 0 0 1 )
* behavioral resistor
R2 4 6 R = r e s + 0 . 0 3 3 * r e s *V( r 2 )
So within a single simulation run you will obtain 100 different frequency values issued by the
Wien bridge oscillator. The voltage sequence VR2 is shown below.

386

22.4

CHAPTER 22. STATISTICAL CIRCUIT ANALYSIS

ngspice scripting language

The ngspice scripting language is described in detail in chapter 17.8. All commands listed in
chapter 17.5 are available, as well as the built-in functions decried in chapter 17.2, the control
structures listed in chapter 17.6, and the predefined variables from chapt. 17.7. Variables and
functions are typically evaluated after a simulation run. You may created loops with several
simulation runs and change device and model parameters with the alter (17.5.3) or altermod
(17.5.4) commands, as shown in the next section 22.5. You may even interrupt a simulation run
by proper usage of the stop (17.5.72) and resume (17.5.51) commands. After stop you may
change device or model parameters and then go on with resume, continuing the simulation with
the new parameter values.
The statistical functions provided for scripting are listed in the following table:

22.5. MONTE-CARLO SIMULATION


Name
rnd(vector)

sgauss(vector)

sunif(vector)

poisson(vector)

exponential(vector)

22.5

387

Function
A vector with each component a random integer between 0
and the absolute value of the input vectors corresponding
integer element value.
Returns a vector of random numbers drawn from a
Gaussian distribution (real value, mean = 0 , standard
deviation = 1). The length of the vector returned is
determined by the input vector. The contents of the input
vector will not be used. A call to sgauss(0) will return a
single value of a random number as a vector of length 1..
Returns a vector of random real numbers uniformly
distributed in the interval [-1 .. 1[. The length of the vector
returned is determined by the input vector. The contents of
the input vector will not be used. A call to sunif(0) will
return a single value of a random number as a vector of
length 1.
Returns a vector with its elements being integers drawn
from a Poisson distribution. The elements of the input
vector (real numbers) are the expected numbers l.
Complex vectors are allowed, real and imaginary values
are treated separately.
Returns a vector with its elements (real numbers) drawn
from an exponential distribution. The elements of the input
vector are the respective mean values (real numbers).
Complex vectors are allowed, real and imaginary values
are treated separately.

Monte-Carlo Simulation

The ngspice scripting language may be used to run Monte-Carlo simulations with statistically
varying device or model parameters. Calls to the functions sgauss(0) or sunif(0) (see 17.2) will
return Gaussian or uniform distributed random numbers (real numbers), stored in a vector. You
may define (see 17.5.14) your own function using sgauss or sunif, e.g. to change the mean or
range. In a loop (see 17.6) then you may call the alter (17.5.3) or altermod (17.5.4) statements
with random parameters followed by an analysis like op, dc, ac, tran or other.

22.5.1

Example 1

The first examples is a LC band pass filter, where L and C device parameters will be changed 100
times. Each change is followed by an ac analysis. All graphs of output voltage versus frequency
are plotted. The file is available in the distribution as /examples/Monte_Carlo/MonteCarlo.sp
as well as from the CVS repository.

388

CHAPTER 22. STATISTICAL CIRCUIT ANALYSIS

Monte-Carlo example 1
P e r f o r m Monte C a r l o s i m u l a t i o n i n n g s p i c e
V1 N001 0 AC 1 DC 0
R1 N002 N001 141
*
C1 OUT 0 1 e 09
L1 OUT 0 10 e 06
C2 N002 0 1 e 09
L2 N002 0 10 e 06
L3 N003 N002 40 e 06
C3 OUT N003 250 e 12
*
R2 0 OUT 141
*
. control
l e t mc_runs = 100
l e t run = 1
s e t c u r p l o t = new
$ c r e a t e a new p l o t
s e t s c r a t c h = $ c u r p l o t $ s t o r e i t s name t o s c r a t c h
*
d e f i n e u n i f ( nom , v a r ) ( nom + nom * v a r * s u n i f ( 0 ) )
d e f i n e a u n i f ( nom , a v a r ) ( nom + a v a r * s u n i f ( 0 ) )
d e f i n e g a u s s ( nom , v a r , s i g ) ( nom + nom * v a r / s i g * s g a u s s ( 0 ) )
d e f i n e a g a u s s ( nom , a v a r , s i g ) ( nom + a v a r / s i g * s g a u s s ( 0 ) )
*
d o w h i l e r u n <= mc_runs
a l t e r c1 = u n i f ( 1 e 09 , 0 . 1 )
*
a l t e r l 1 = a u n i f ( 1 0 e 06 , 2 e 06)
*
a
l t e r c2 = a u n i f ( 1 e 09 , 100 e 12)
*
a l t e r l 2 = u n i f ( 1 0 e 06 , 0 . 2 )
*
a l t e r l 3 = a u n i f ( 4 0 e 06 , 8 e 06)
*
a l t e r c3 = u n i f ( 2 5 0 e 12 , 0 . 1 5 )
*
a l t e r c1 = g a u s s ( 1 e 09 , 0 . 1 , 3 )
a l t e r l 1 = a g a u s s ( 1 0 e 06 , 2 e 06 , 3 )
a l t e r c2 = a g a u s s ( 1 e 09 , 100 e 12 , 3 )
a l t e r l 2 = g a u s s ( 1 0 e 06 , 0 . 2 , 3 )
a l t e r l 3 = a g a u s s ( 4 0 e 06 , 8 e 06 , 3 )
a l t e r c3 = g a u s s ( 2 5 0 e 12 , 0 . 1 5 , 3 )
a c o c t 100 250K 10Meg
s e t r u n =" $&r u n "
$ c r e a t e a v a r i a b l e from t h e v e c t o r
set dt = $curplot
$ store the current plot to dt
setplot $scratch
$ make s c r a t c h t h e a c t i v e p l o t
* store the output vector to plot scratch
l e t v o u t { $ r u n }={ $ d t } . v ( o u t )
s e t p l o t $dt
$ go b a c k t o t h e p r e v i o u s p l o t
l e t run = run + 1
end
p l o t db ( { $ s c r a t c h } . a l l )
. endc
. end

22.6. DATA EVALUATION WITH GNUPLOT

22.5.2

389

Example 2

A more sophisticated input file for Monte Carlo simulation is distributed with the file /examples/Monte_Carlo/MCring.sp (or git repository). Due to its length it is not reproduced here, but
some comments on its enhancements over example 1 (22.5.1) are presented in the following.
A 25-stage ring oscillator is the circuit used with a transient simulation. It comprises of CMOS
inverters, modeled with BSIM3. Several model parameters (vth, u0, tox, L, and W) shall be
varied statistically between each simulation run. The frequency of oscillation will be measured
by a fft and stored. Finally a histogram of all measured frequencies will be plotted.
The function calls to sunif(0) and sgauss(0) return uniformly or Gaussian distributed random numbers. A function unif, defined by the line
define unif(nom, var) (nom + (nom*var) * sunif(0))
will return a value with mean nom and deviation var relative to nom.
The line
set n1vth0=@n1[vth0]
will store the threshold voltage vth0, given by the model parameter set, into a variable n1vth0,
ready to be used by unif, aunif, gauss, or agauss function calls.
In the simulation loop the altermod command changes the model parameters before a call to
tran. After the transient simulation the resulting vector is linearized, a fft is calculated, and the
maximum of the fft signal is measured by the meas command and stored in a vector maxffts.
Finally the contents of the vector maxffts is plotted in a histogram.
For more details, please have a look at the strongly commented input file MCring.sp.

22.6

Data evaluation with Gnuplot

Run the example file /examples/Monte_Carlo/OpWien.sp, described in chapt. 22.3. Generate a


plot with Gnuplot by the ngspice command
gnuplot pl4mag v4mag xlimit 500 1500
Open and run the command file in the Gnuplot command line window by
load pl-v4mag.p
A Gaussian curve will be fitted to the simulation data. The mean oscillator frequency and its
deviation are printed in the curve fitting log in the Gnuplot window.

390

CHAPTER 22. STATISTICAL CIRCUIT ANALYSIS

Gnuplot script for data evaluation:


#
#
#
#
#
#

This file : pl - v4mag . p


ngspice file OpWien . sp
ngspice command :
gnuplot pl4mag v4mag xlimit 500 1500
a gnuplot manual :
http :// www . duke . edu /~ hpgavin / gnuplot . html

# Gauss function to be fitted


f1 ( x )=( c1 /( a1 * sqrt (2*3.14159))* exp ( -(( x - b1 )**2)/(2* a1 **2)))
# Gauss function to plot start graph
f2 ( x )=( c2 /( a2 * sqrt (2*3.14159))* exp ( -(( x - b2 )**2)/(2* a2 **2)))
# start values
a1 =50 ; b1 =900 ; c1 =50
# keep start values in a2 , b2 , c2
a2 = a1 ; b2 = b1 ; c2 = c1
# curve fitting
fit f1 ( x ) pl4mag . data using 1:2 via a1 , b1 , c1
# plot original and fitted curves with new a1 , b1 , c1
plot " pl4mag . data " using 1:2 with lines , f1 ( x ) , f2 ( x )

pl4mag.data is the simulation data, f2(x) the starting curve, f1(x) the fitted Gaussian distribution.
This is just a simple example. You might explore the powerful built-in functions of Gnuplot to
do a much more sophisticated statistical data analysis.

Chapter 23
Circuit optimization with ngspice
23.1

Optimization of a circuit

Your circuit design (analog, maybe mixed-signal) has already the best circuit topology. There
might be still some room for parameter selection, e.g. the geometries of transistors or values of
passive elements, to best fit the specific purpose. This is, what (automatic) circuit optimization
will deliver. In addition you may fine-tune, optimize and verify the circuit over voltage, process
or temperature corners. So circuit optimization is a valuable tool in the hands of an experienced
designer. It will relieve you from the routine task of endless repetitions of re-simulating your
design.
You have to choose circuit variables as parameters to be varied during optimization (e.g. device
size, component values, bias inputs etc.). Then you may pose performance constraints onto
you circuits (e.g. Vnode < 1.2V, gain > 50 etc.). Optimization objectives are the variables to be
minimized or maximized. The n objectives and m constraints are assembled into a cost function.
The optimization flow is now the following: The circuit is loaded. Several (perhaps only one)
simulations are started with a suitable starter set of variables. Measurements are done on the
simulator output to check for the performance constraints and optimization objectives. These
data are fed into the optimizer to evaluate the cost function. A sophisticated algorithm now
determines a new set of circuit variables for the next simulator run(s). Stop conditions have to
be defined by the user to tell the simulator when to finish (e.g. fall below a cost function value,
parameter changes fall below a certain threshold, number of iterations exceeded).
The optimizer algorithms, its parameters and the starting point influence the convergence behavior. The algorithms have to provide measures to reaching the global optimum, not to stick
to a local one, and thus are tantamount for the quality of the optimizer.
ngspice does not have an integral optimization processor. Thus this chapter will rely on work
done by third parties to introduce ngspice optimization capability.ngspice provides the simulation engine, a script or program controls the simulator and provides the optimizer functionality.
Four optimizers are presented here, using ngspice scripting language, using tclspice, using a
Python script, and using ASCO, a c-coded optimization program.

391

392

23.2

CHAPTER 23. CIRCUIT OPTIMIZATION WITH NGSPICE

ngspice optimizer using ngspice scripts

Friedrich Schmidt (see his web site) has intensively used circuit optimization during his development of Nonlinear loadflow computation with Spice based simulators. He has provided an
optimizer using the internal ngspice scripting language (see chapt. 17.8). His original scripts
are found here. A slightly modified and concentrated set of his scripts is available from the
ngspice optimizer directory.
The simple example given in the scripts is o.k. with current ngspice. Real circuits have still to
be tested.

23.3

ngspice optimizer using tclspice

ngspice offers another scripting capability, namely the tcl/tk based tclspice option (see chapt.
20). An optimization procedure may be written using a tcl script. An example is provided in
chapter 20.5.2.

23.4

ngspice optimizer using a Python script

Werner Hoch has developed a ngspice optimization procedure based on the differential evolution algorithm [21]. On his web page he provides a Python script containing the control flow
and algorithms.

23.5

ngspice optimizer using ASCO

The ASCO optimizer, developed by Joao Ramos, also applies the differential evolution algorithm [21]. An enhanced version 0.4.7.1, adding ngspice as a simulation engine, may be
downloaded here (7z archive format). Included are executable files (asco, asco-mpi, ngspice-c
for MS Windows). The source code should also compile and function under LINUX (not yet
tested).
ASCO is a standalone executable, which communicates with ngspice via ngspice input and output files. Several optimization examples, originally provided by J. Ramos for other simulators,
are prepared for use with ngspice. Parallel processing on a multi-core computer has been tested
using MPI (MPICH2) under MS Windows. A processor network will be supported as well. A
MS Windows console application ngspice_c.exe is included in the archive. Several stand alone
tools are provided, but not tested yet.
Setting up an optimization project with ASCO requires advanced know-how of using ngspice.
There are several sources of information. First of all the examples provided with the distribution give hints how to start with ASCO. The original ASCO manual is provided as well, or is
available here. It elaborates on the examples, using a commercial simulator, and provides a
detailed description how to set up ASCO. Installation of ASCO and MPI (under Windows) is
described in a file INSTALL.

23.5. NGSPICE OPTIMIZER USING ASCO

393

Some remarks on how to set up ASCO for ngspice are given in the following sections (more
to be added). These a meant not as a complete description, but are an addition the the ASCO
manual.

23.5.1

Three stage operational amplifier

This example is taken from chapter 6.2.2 Tutorial #2 from the ASCO manual. The directory
examples/ngspice/amp3 contains four files:

amp3.cfg This file contains all configuration data for this optimization. Of special interest is
the following section, which sets the required measurements and the constraints on the measured
parameters:
# Measurements #
ac_power:VDD:MIN:0
dc_gain:VOUT:GE:122
unity_gain_frequency:VOUT:GE:3.15E6
phase_margin:VOUT:GE:51.8
phase_margin:VOUT:LE:70
amp3_slew_rate:VOUT:GE:0.777E6
#
Each of these entries is linked to a file in the /extract subdirectory, having exactly the same
names as given here, e.g. ac_power, dc_gain, unity_gain, phase_margin, and amp3_slew_rate.
Each of these files contains an # Info # section, which is currently not used. The # Commands # section may contain a measurement command (including ASCO parameter #SYMBOL#, see file /extract/unity_gain_frequency). It also may contain a .control section (see file
/extract/phase_margin_min). During set-up #SYMBOL# is replaced by the file name, a leading
z, and a trailing number according to the above sequence, starting with 0.

amp3.sp This is the basic circuit description. Entries like #LM2# are ASCO-specific, defined
in the # Parameters # section of file amp3.cfg. ASCO will replace these parameter placeholders
with real values for simulation, determined by the optimization algorithm. The .control ... .endc
section is specific to ngspice. Entries to this section may deliver workarounds of some commands not available in ngspice, but used in other simulators. You may also define additional
measurements, get access to variables and vectors, or define some data manipulation. In this
example the .control section contains an op measurement, required later for slew rate calculation, as well as the ac simulation, which has to occur before any further data evaluation. Data
from the op simulation are stored in a plot op1. Its name is saved in variable dt. The ac measurements sets another plot ac1. To retrieve op data from the former plot, you have to use the
{$dt}.<vector> notation (see file /extract/amp3_slew_rate).

n.typ, p.typ MOSFET parameter files, to be included by amp3.sp.

394

CHAPTER 23. CIRCUIT OPTIMIZATION WITH NGSPICE

Testing the set-up


Copy asco-test.exe and ngspice_c.exe (console executable of ngspice) into the directory, and
run
$ asco-test -ngspice amp3
from the console window. Several files will be created during checking. If you look at <computername>.sp: this is the input file for ngspice_c, generated by ASCO. You will find the additional
.measure commands and .control sections. The quit command will be added automatically
just before the .end command in its own .control section. asco-test will display error messages on the console, if the simulation or communication with ASCO is not o.k.. The output file <computer-name>.out, generated by ngspice during each simulation, contains symbols
like zac_power0, zdc_gain1, zunity_gain_frequency2, zphase_margin3, zphase_margin4, and
zamp3_slew_rate5. These are used to communicate the ngspice output data to ASCO. ASCO
is searching for something like zdc_gain1 =, and then takes the next token as the input value.
Calling phase_margin twice in amp3.cfg has lead to two measurements in two .control sections
with different symbols (zphase_margin3, zphase_margin4).
A failing test may result in an error message from ASCO. Sometimes, however, ASCO freezes
after some output statements. This may happen if ngspice issues an error message which cannot
be handled by ASCO. Here it may help calling ngspice directly with the input file generated by
ASCO:
$ ngspice_c <computer-name>.sp
Thus you may evaluate the ngspice messages directly.
Running the simulation
Copy (w)asco.exe, (w)asco-mpi.exe and ngspice_c.exe (console executable of ngspice) into the
directory, and run
$ asco -ngspice amp3
or alternatively (if MPICH is installed)
$ mpiexec -n 7 asco-mpi -ngspice amp3
The following graph 23.1 shows the acceleration of the optimization simulation on a multi-core
processor (i7 with 4 real or 8 virtual cores), 500 generations, if -n is varied. Speed is tripled, a
mere 15 min suffices to optimize 21 parameters of the amplifier.

23.5.2

Digital inverter

This example is taken from chapter 6.2.1 Tutorial #1 from the ASCO manual. In addition
to the features already mentioned above, it adds Monte-Carlo and corner simulations. The file
inv.cfg contains the following section:
#Optimization Flow#
Alter:yes
$do we want to do corner analysis?
MonteCarlo:yes
$do we want to do MonteCarlo analysis?

23.5. NGSPICE OPTIMIZER USING ASCO

395

Figure 23.1: Optimization speed


AlterMC cost:3.00 $point at which we want to start ALTER and/or
MONTECARLO
ExecuteRF:no
$Execute or no the RF module to add RF parasitics?
SomethingElse:
$
#
Monte Carlo is switched on. It uses the AGAUSS function (see chapt. 22.2). Its parameters are
generated by ASCO from the data supplied by the inv.cfg section #Monte Carlo#. According to
the paper by Pelgrom on MOS transistor matching [22] the AGAUSS parameters are calculated
as


W
ABeta
6

10 , 1
(23.1)
W = AGAUSS W,
2 W L m 100


AV T
9
delvto = AGAUSS 0,
10 , 1
2 W L m

(23.2)

The .ALTER command is not available in ngspice. However, a new option in ngspice to the
altermod command (17.5.4) enables the simulation of design corners. The #Alter# section in
inv.cfg gives details. Specific to ngspice, again several .control section are used.
# ALTER #
.control
* gate oxide thickness varied
altermod nm pm file [b3.min b3.typ b3.max]
.endc
.control
* power supply variation
alter vdd=[2.0 2.1 2.2]
.endc
.control

396

CHAPTER 23. CIRCUIT OPTIMIZATION WITH NGSPICE

run
.endc
#
NMOS (nm) and PMOS (pm) model parameter sets are loaded from three different model files,
each containing both NMOS and PMOS sets. b3.typ is assembled from the original parameter
files n.typ and p.typ, provided with original ASCO, with some adaptation to ngspice BSIM3.
The min and max sets are artificially created in that only the gate oxide thickness deviates 1
nm from what is found in model file b3.typ. In addition the power supply voltage is varied, so
in total you will find 3 x 3 simulation combinations in the input file <computer-name>.sp (after
running asco-test).

23.5.3

Bandpass

This example is taken from chapter 6.2.4 Tutorial #4 from the ASCO manual. S11 in the
passband is to be maximised. S21 is used to extract side lobe parameters. The .net command is
not available in ngspice, so S11 and S21 are derived with a script in file bandpass.sp as described
in chapt. 17.9. The measurements requested in bandpass.cfg as
# Measurements #
Left_Side_Lobe:---:LE:-20
Pass_Band_Ripple:---:GE:-1
Right_Side_Lobe:---:LE:-20
S11_In_Band:---:MAX:--#
are realized as measure commands inside of control sections (see files in directory extract).
The result of a measure statement is a vector, which may be processed by commands in the
following lines. In file extract/S1_In_Band #Symbol# is made available only after a short calculation (inversion of sign), using the print command. quit has been added to this entry because
it will become the final control section in <computer-name>.sp. A disadvantage of measure
inside of a .control section is, that parameters from .param statements may not be used (as is
done in example 23.5.4).
The bandpass example includes the calculation of RF parasitic elements defined in rfmodule.cfg
(see chapt. 7.5 of the ASCO manual). This calculation is invoked by setting
ExecuteRF:yes

$Execute or no the RF module to add RF parasitics?

in bandpass.cfg. The two subcircuits LBOND_sub and CSMD_sub are generated in <computername>.sp to simulate these effects.

23.5.4

Class-E power amplifier

This example is taken from chapter 6.2.3 Tutorial #3 from the ASCO manual. In this example
the ASCO post processing is applied in file extract/P_OUT (see chapter 7.4 of the ASCO manual.). In this example .measurement statements are used. They allow using parameters from
.param statements, because they will be located outside of .control sections, but do not allow to
do data post processing inside of ngspice. You may use ASCO post processing instead.

Chapter 24
Notes
24.1

Glossary

card A logical SPICE input line. A card may be extended through the use of the + sign in
SPICE, thereby allowing it to take up multiple lines in a SPICE deck.
code model A model of a device, function, component, etc. which is based solely on a C
programming language-based function. In addition to the code models included with the
XSPICE option of the ngspice simulator, you can use code models that you develop for
circuit modeling.
deck A collection of SPICE cards which together specify all input information required in
order to perform an analysis. A deck of cards will in fact be contained within a file
on the host computer system.
element card A single, logical line in an ngspice circuit description deck which describes a
circuit element. Circuit elements are connected to each other to form circuits (e.g., a
logical card which describes a resistor, such as R1 2 0 10K, is an element card).
instance A unique occurrence of a circuit element. See element card, in which the instance
R1 is specified as a unique element (instance) in a hypothetical circuit description.
macro A macro, in the context of this document, refers to a C language macro which supports the construction of user-defined models by simplifying input/output and parameterpassing operations within the Model Definition File.
.mod Refers to the Model Definition File in XSPICE. The file suffix reflects the file-name of
the model definition file: cfunc.mod.
.model Refers to a model card associated with an element card in ngspice. A model card allows
for data defining an instance to be conveniently located in the ngspice deck such that the
general layout of the elements is more readable.
Nutmeg The ngspice default post-processor. This provides a simple stand-alone simulator
interface which can be used with the ngspice simulator to display and plot simulator raw
files.

397

398

CHAPTER 24. NOTES

subcircuit A device within an ngspice deck which is defined in terms of a group of element
cards and which can be referenced in other parts of the ngspice deck through element
cards.

24.2

Acronyms and Abbreviations

ATE Automatic Test Equipment


CAE Computer-Aided Engineering
CCCS Current Controlled Current Source.
CCVS Current Controlled Voltage Source.
FET Field Effect Transistor
IDD Interface Design Document
IFS Refers to the Interface Specification File. The abbreviation reflects the file name of the
Interface Specification File: ifspec.ifs.
MNA Modified Nodal Analysis
MOSFET Metal Oxide Semiconductor Field Effect Transistor
PWL Piece-Wise Linear
RAM Random Access Memory
ROM Read Only Memory
SDD Software Design Document
SI Simulator Interface
SPICE Simulation Program with Integrated Circuit Emphasis. This program was developed at
the University of California at Berkeley and is the origin of ngspice.
SPICE3 Version 3 of SPICE.
SRS Software Requirements Specification
SUM Software Users Manual
UCB University of California at Berkeley
UDN User-Defined Node(s)
VCCS Voltage Controlled Current Source.
VCVS Voltage Controlled Voltage Source
XSPICE Extended SPICE; option to ngspice integrating predefined or user defined code models for event-driven mixed-signal simulation.

Bibliography
[1] A. Vladimirescu and S. Liu, The Simulation of MOS Integrated Circuits Using SPICE2
ERL Memo No. ERL M80/7, Electronics Research Laboratory University of California,
Berkeley, October 1980
[2] T. Sakurai and A. R. Newton, A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series-connected MOSFET Structure ERL Memo
No. ERL M90/19, Electronics Research Laboratory, University of California, Berkeley,
March 1990
[3] B. J. Sheu, D. L. Scharfetter, and P. K. Ko, SPICE2 Implementation of BSIM ERL Memo
No. ERL M85/42, Electronics Research Laboratory University of California, Berkeley,
May 1985
[4] J. R. Pierret, A MOS Parameter Extraction Program for the BSIM Model ERL Memo Nos.
ERL M84/99 and M84/100, Electronics Research Laboratory University of California,
Berkeley, November 1984
[5] Min-Chie Jeng, Design and Modeling of Deep Submicrometer MOSFETSs ERL Memo
Nos. ERL M90/90, Electronics Research Laboratory, University of California, Berkeley,
October 1990
[6] Soyeon Park, Analysis and SPICE implementation of High Temperature Effects on MOSFET, Masters thesis, University of California, Berkeley, December 1986.
[7] Clement Szeto, Simulation of Temperature Effects in MOSFETs (STEIM), Masters thesis, University of California, Berkeley, May 1988.
[8] J.S. Roychowdhury and D.O. Pederson, Efficient Transient Simulation of Lossy Interconnect, Proc. of the 28th ACM/IEEE Design Automation Conference, June 17-21 1991, San
Francisco
[9] A. E. Parker and D. J. Skellern, An Improved FET Model for Computer Simulators, IEEE
Trans CAD, vol. 9, no. 5, pp. 551-553, May 1990.
[10] R. Saleh and A. Yang, Editors, Simulation and Modeling, IEEE Circuits and Devices, vol.
8, no. 3, pp. 7-8 and 49, May 1992.
[11] H.Statz et al., GaAs FET Device and Circuit Simulation in SPICE, IEEE Transactions on
Electron Devices, V34, Number 2, February 1987, pp160-169.
[12] Weidong Liu et al.: BSIM3v3.2.3 MOSFET Model Users Manual, BSIM3v3.2.3

399

400

BIBLIOGRAPHY

[13] Weidong Lui et al.: BSIM3.v3.3.0 MOSFET Model Users Manual, BSIM3v3.3.0
[14] SPICE3.C1 Nutmeg Programmers Manual, Department of Electrical Engineering and
Computer Sciences, University of California, Berkeley, California, April, 1987.
[15] Thomas L. Quarles: SPICE3 Version 3C1 Users Guide, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California, April,
1989.
[16] Brian Kernighan and Dennis Ritchie: The C Programming Language, Second Edition,
Prentice-Hall, Englewood Cliffs, New Jersey, 1988.
[17] Code-Level Modeling in XSPICE, F.L. Cox, W.B. Kuhn, J.P. Murray, and S.D. Tynor,
published in the Proceedings of the 1992 International Symposium on Circuits and Systems, San Diego, CA, May 1992, vol 2, pp. 871-874.
[18] A Physically Based Compact Model of Partially Depleted SOI MOSFETs for Analog Circuit Simulation, Mike S. L. Lee, Bernard M. Tenbroek, William Redman-White, James
Benson, and Michael J. Uren, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36,
NO. 1, JANUARY 2001, pp. 110-121
[19] A Realistic Large-signal MESFET Model for SPICE, A. E. Parker, and D. J. Skellern,
IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 9, Sept. 1997, pp.
1563-1571.
[20] Integrating RTS Noise into Circuit Analysis, T. B. Tang and A. F. Murray, IEEE ISCAS,
2009, Proc. of IEEE ISCAS, Taipei, Taiwan, May 2009, pp 585-588 (link)
[21] R. Storn, and K. Price: Differential Evolution, technical report TR-95-012, ICSI, March
1995, see report download, or the DE web page
[22] M. J. M. Pelgrom e.a.: Matching Properties of MOS Transistors, IEEE J. Sol. State Circ,
vol. 24, no. 5, Oct. 1989, pp. 1433-1440
[23] Y. V. Pershin, M. Di Ventra: "SPICE model of memristive devices with threshold",
arXiv:1204.2600v1 [physics.comp-ph] 12 Apr 2012, http://arxiv.org/pdf/1204.2600.pdf

Part II
XSPICE Software Users Manual

401

Chapter 25
XSPICE Basics
25.1

ngspice with the XSPICE option

The XSPICE option allows you to add event-driven simulation capabilities to NGSPICE. NGSPICE
now is the main software program that performs mathematical simulation of a circuit specified
by you, the user. It takes input in the form of commands and circuit descriptions and produces
output data (e.g. voltages, currents, digital states, and waveforms) that describe the circuits
behavior.
Plain NGSPICE is designed for analog simulation and is based exclusively on matrix solution
techniques. The XSPICE option adds even-driven simulation capabilities. Thus, designs that
contain significant portions of digital circuitry can be efficiently simulated together with analog
components. NGSPICE with XSPICE option also includes a User-Defined Node capability
that allows event-driven simulations to be carried out with any type of data.
The XSPICE option has been developed by the Computer Science and Information Technology
Laboratory at Georgia Tech Research Institute of the Georgia Institute of Technology, Atlanta,
Georgia 30332 at around 1990 and enhanced by the NGSPICE team. The manual is based on
the original XSPICE users manual, made available from Georgia Tech.
In the following, the term XSPICE may be read as NGSPICE with XSPICE code model subsystem enabled. You may enable the option by adding --enable-xspice to the ./configure
command. The MS Windows distribution already contains the XSPICE option.

25.2

The XSPICE Code Model Subsystem

The new component of ngspice, the Code Model Subsystem, provides the tools needed to model
the various parts of your system. While NGSPICE is targeted primarily at integrated circuit (IC)
analysis, XSPICE includes features to model and simulate board-level and system-level designs
as well. The Code Model Subsystem is central to this new capability, providing XSPICE with
an extensive set of models to use in designs and allowing you to add your own models to this
model set.
The NGSPICE simulator at the core of XSPICE includes built-in models for discrete components commonly found within integrated circuits. These model primitives include components such as resistors, capacitors, diodes, and transistors. The XSPICE Code Model Subsystem

403

404

CHAPTER 25. XSPICE BASICS

extends this set of primitives in two ways. First, it provides a library of over 40 additional primitives, including summers, integrators, digital gates, controlled oscillators, s-domain transfer
functions, and digital state machines. See chapter 12 for a description of the library entries.
Second, it adds a code model generator to ngspice which provides a set of programming utilities to make it easy for you to create your own models by writing them in the C programming
language.
The code models are generated upon compiling ngspice. They are stored in shared libraries,
which may be distributed independently from the ngspice sources. Upon runtime ngspice will
load the code model libraries and make the code model instances available for simulation.

25.3

XSPICE Top-Level Diagram

A top-level diagram of the XSPICE system integrated into ngspice is shown in Figure 25.1.
The XSPICE Simulator is made up of the NGSPICE core, the event-driven algorithm, circuit
description syntax parser extensions, a loading routine for code models, and the Nutmeg user
interface. The XSPICE Code Model Subsystem consists of the Code Model Generator, 5 standard code model library sources with more than 40 code models, the sources for Node Type
Libraries, and all the interfaces to User-Defined Code Models and to User-Defined Node Types.

Figure 25.1: ngspice/XSPICE Top-Level Diagram

Chapter 26
Execution Procedures
This chapter covers operation of the XSPICE simulator and the Code Model Subsystem. It
begins with background material on simulation and modeling and then discusses the analysis
modes supported in XSPICE and the circuit description syntax used for modeling. Detailed
descriptions of the predefined Code Models and Node Types provided in the XSPICE libraries
are also included.

26.1

Simulation and Modeling Overview

This section introduces the concepts of circuit simulation and modeling. It is intended primarily
for users who have little or no previous experience with circuit simulators, and also for those
who have not used circuit simulators recently. However, experienced SPICE users may wish to
scan the material presented here since it provides background for new Code Model and UserDefined Node capabilities of the XSPICE option.

26.1.1

Describing the Circuit

This section provides an overview of the circuit description syntax expected by the XSPICE
simulator. A general understanding of circuit description syntax will be helpful to you should
you encounter problems with your circuit and need to examine the simulators error messages,
or should you wish to develop your own models.
This section will introduce you to the creation of circuit description input files using the Nutmeg
user interface. Note that this material is presented in an overview form. Details of circuit
description syntax are given later in this chapter and in the previous chapters of this manual.
26.1.1.1

Example Circuit Description Input

Although different SPICE-based simulators may include various enhancements to the basic
version from the University of California at Berkeley, most use a similar approach in describing
circuits. This approach involves capturing the information present in a circuit schematic in
the form of a text file that follows a defined format. This format requires the assignment of
alphanumeric identifiers to each circuit node, the assignment of component identifiers to each

405

406

CHAPTER 26. EXECUTION PROCEDURES

Figure 26.1: Example Circuit 1


circuit device, and the definition of the significant parameters for each device. For example, the
circuit description below shows the equivalent input file for the circuit shown in Figure26.1.
Small Signal Amplifier
*
*This circuit simulates a simple small signal amplifier.
*
Vin
Input 0
0 SIN(0 .1 500Hz)
R_source
Input Amp_In
100
C1
Amp_In 0
1uF
R_Amp_Input Amp_In 0
1MEG
E1
(Amp:Out 0) (Amp_In 0)
-10
R_Load
Amp_Out 0
1000
*
.Tran 1.0u 0.01
*
.end

This file exhibits many of the most important properties common to all SPICE circuit description files including the following:
The first line of the file is always interpreted as the title of the circuit. The title may
consist of any text string.
Lines which provide user comments, but no circuit information, are begun by an asterisk.
A circuit device is specified by a device name, followed by the node(s) to which it is
connected, and then by any required parameter information.
The first character of a device name tells the simulator what kind of device it is (e.g. R =
resistor, C = capacitor, E = voltage controlled voltage source).
Nodes may be labeled with any alphanumeric identifier. The only specific labeling requirement is that 0 must be used for ground.
A line that begins with a dot is a control directive. Control directives are used most
frequently for specifying the type of analysis the simulator is to carry out.

26.1. SIMULATION AND MODELING OVERVIEW

407

An .end statement must be included at the end of the file.


With the exception of the Title and .end statements, the order in which the circuit file is
defined is arbitrary.
All identifiers are case insensitive - the identifier npn is equivalent to NPN and to
nPn.
Spaces and parenthesis are treated as white space.
Long lines may be continued on a succeeding line by beginning the next line with a +
in the first column.
In this example, the title of the circuit is Small Signal Amplifier. Three comment lines are
included before the actual circuit description begins. The first device in the circuit is voltage
source Vin, which is connected between node Input and 0 (ground). The parameters after
the nodes specify that the source has an initial value of 0, a wave shape of SIN, and a DC
offset, amplitude, and frequency of 0, .1, and 500 respectively. The next device in the circuit is
resistor R_Source, which is connected between nodes Input and Amp_In, with a value of
100 Ohms. The remaining device lines in the file are interpreted similarly.
The control directive that begins with .Tran specifies that the simulator should carry out a
simulation using the Transient analysis mode. In this example, the parameters to the transient
analysis control directive specify that the maximum time-step allowed is 1 microsecond and
that the circuit should be simulated for 0.01 seconds of circuit time.
Other control cards are used for other analysis modes. For example, if a frequency response plot
is desired, perhaps to determine the effect of the capacitor in the circuit, the following statement
will instruct the simulator to perform a frequency analysis from 100 Hz to 10 MHz in decade
intervals with ten points per decade.
.ac dec 10 100 10meg

To determine the quiescent operating point of the circuit, the following statement may be inserted in the file.
.op
A fourth analysis type supported by ngspice is swept DC analysis. An example control statement for the analysis mode is
.dc Vin -0.1 0.2 .05

This statement specifies a DC sweep which varies the source Vin from -100 millivolts to +200
millivolts in steps of 50 millivolts.

408

CHAPTER 26. EXECUTION PROCEDURES

Figure 26.2: Example Circuit 2


26.1.1.2

Models and Subcircuits

The file discussed in the previous section illustrated the most basic syntax rules of a circuit
description file. However, ngspice (and other SPICE-based simulators) include many other
features which allow for accurate modeling of semiconductor devices such as diodes and transistors and for grouping elements of a circuit into a macro or subcircuit description which can
be reused throughout a circuit description. For instance, the file shown below is a representation
of the schematic shown in Figure 26.2.

Small Signal Amplifier with Limit Diodes


*
*This circuit simulates a small signal amplifier
*with a diode limiter.
*
.dc Vin -1 1 .05
*
Vin
Input 0 DC
0
R_source Input Amp_In
100
*
D_Neg
0 Amp_In
1n4148
D_Pos
Amp_In 0
1n4148
*
C1
Amp_In 0
1uF
X1
Amp_In 0 Amp.Out
Amplifier
R_Load
Amp_Out 0
1000
*
.model 1n4148 D (is=2.495E-09 rs=4.755E-01 n=1.679E+00
+ tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02
+ ibv=1.000E-04)
*
.subckt Amplifier Input Common Output
E1
(Output Common) (Input Common) -10
R_Input
Input
Common 1meg
.ends Amplifier
*
.end

26.1. SIMULATION AND MODELING OVERVIEW

409

This is the same basic circuit as in the initial example, with the addition of two components and
some changes to the simulation file. The two diodes have been included to illustrate the use of
device models, and the amplifier is implemented with a subcircuit. Additionally, this file shows
the use of the swept DC control card.
Device Models Device models allow you to specify, when required, many of the parameters
of the devices being simulated. In this example, model statements are used to define the silicon
diodes. Electrically, the diodes serve to limit the voltage at the amplifier input to values between
about 700 millivolts. The diode is simulated by first declaring the instance of each diode
with a device statement. Instead of attempting to provide parameter information separately for
both diodes, the label 1n4148 alerts the simulator that a separate model statement is included
in the file which provides the necessary electrical specifications for the device (1n4148 is the
part number for the type of diode the model is meant to simulate).
The model statement that provides this information is:
.model 1n4148 D (is=2.495E-09 rs=4.755E-01 n=1.679E+00
+
tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01
+
bv=1.000E+02 ibv=1.000E-04)

The model statement always begins with the string .model followed by an identifier and the
model type (D for diode, NPN for NPN transistors, etc).
The optional parameters (is, rs, n, etc.) shown in this example configure the simulators
mathematical model of the diode to match the specific behavior of a particular part (e.g. a
1n4148).
Subcircuits In some applications, describing a device by embedding the required elements in
the main circuit file, as is done for the amplifier in Figure 26.1, is not desirable. A hierarchical
approach may be taken by using subcircuits. An example of a subcircuit statement is shown in
the second circuit file:
X1 Amp_In 0 Amp_Out

Amplifier Subcircuits are always identified by a device label beginning with X. Just as with
other devices, all of the connected nodes are specified. Notice, in this example, that three nodes
are used. Finally, the name of the subcircuit is specified. Elsewhere in the circuit file, the
simulator looks for a statement of the form:
.subckt <Name> <Node1> <Node2> <Node3> ...

This statement specifies that the lines that follow are part of the Amplifier subcircuit, and that the
three nodes listed are to be treated wherever they occur in the subcircuit definition as referring,
respectively, to the nodes on the main circuit from which the subcircuit was called. Normal
device, model, and comment statements may then follow. The subcircuit definition is concluded
with a statement of the form:
.ends <Name>

410

CHAPTER 26. EXECUTION PROCEDURES

26.1.1.3

XSPICE Code Models

In the previous example, the specification of the amplifier was accomplished by using a NGSPICE
Voltage Controlled Voltage Source device. This is an idealization of the actual amplifier. Practical amplifiers include numerous non-ideal effects, such as offset error voltages and non-ideal
input and output impedances. The accurate simulation of complex, real-world components can
lead to cumbersome subcircuit files, long simulation run times, and difficulties in synthesizing
the behavior to be modeled from a limited set of internal devices known to the simulator.
To address these problems, XSPICE allows you to create Code Models which simulate complex,
non-ideal effects without the need to develop a subcircuit design. For example, the following file
provides simulation of the circuit in Figure 26.2, but with the subcircuit amplifier replaced with
a Code Model called Amp that models several non-ideal effects including input and output
impedance and input offset voltage.

Small Signal Amplifier


*
*This circuit simulates a small signal amplifier
*with a diode limiter.
*
.dc Vin -1 1 .05
*
Vin
Input 0
DC 0
R_source Input Amp_In
100
*
D_Neg 0
Amp_In
1n4148
D_Pos
Amp_In 0
1n4148
*
C1
Amp_In 0
1uF
A1
Amp_In 0 Amp_Out
Amplifier
R_Load
Amp_Out 0
1000
*
.model 1n4148 D (is=2.495E-09 rs=4.755E-01 n=1.679E+00
+ tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02
+ ibv=1.000E-04)
*
.model Amplifier Amp (gain = -10 in_offset = 1e-3
+
rin = 1meg rout = 0.4)
*
.end

A statement with a device label beginning with A alerts the simulator that the device uses
a Code Model. The model statement is similar in form to the one used to specify the diode.
The model label Amp directs XSPICE to use the code model with that name. Parameter
information has been added to specify a gain of -10, an input offset of 1 millivolt, an input
impedance of 1 meg ohm, and an output impedance of 0.4 ohm. Subsequent sections of this
document detail the steps required to create such a Code Model and include it in the XSPICE
simulator.

26.2. CIRCUIT DESCRIPTION SYNTAX


26.1.1.4

411

Node Bridge Models

When a mixed-mode simulator is used, some method must be provided for translating data
between the different simulation algorithms. XSPICEs Code Model support allows you to
develop models that work under the analog simulation algorithm, the event-driven simulation
algorithm, or both at once.
In XSPICE, models developed for the express purpose of translating between the different algorithms or between different User-Defined Node types are called Node Bridge models. For
translations between the built-in analog and digital types, predefined node bridge models are
included in the XSPICE Code Model Library.
26.1.1.5

Practical Model Development

In practice, developing models often involves using a combination of NGSPICE passive devices, device models, subcircuits, and XSPICE Code Models. XSPICEs Code Models may be
seen as an extension to the set of device models offered in standard NGSPICE. The collection
of over 40 predefined Code Models included with XSPICE provides you with an enriched set of
modeling primitives with which to build subcircuit models. In general, you should first attempt
to construct your models from these available primitives. This is often the quickest and easiest
method.
If you find that you cannot easily design a subcircuit to accomplish your goal using the available
primitives, then you should turn to the code modeling approach. Because they are written in a
general purpose programming language (C), code models enable you to simulate virtually any
behavior for which you can develop a set of equations or algorithms.

26.2

Circuit Description Syntax

If you need to debug a simulation, if you are planning to develop your own models, or if you
are using the XSPICE simulator through the Nutmeg user interface, you will need to become
familiar with the circuit description language.
The previous sections presented example circuit description input files. The following sections
provide more detail on XSPICE circuit descriptions with particular emphasis on the syntax
for creating and using models. First, the language and syntax of the NGSPICE simulator are
described and references to additional information are given. Next, XSPICE extensions to the
ngspice syntax are detailed. Finally, various enhancements to NGSPICE operation are discussed
including polynomial sources, arbitrary phase sources, supply ramping, matrix conditioning,
convergence options, and debugging support.

26.2.1

XSPICE Syntax Extensions

In the preceding discussion, NGSPICE syntax was reviewed, and those features of NGSPICE
that are specifically supported by the XSPICE simulator were enumerated. In addition to these
features, there exist extensions to the NGSPICE capabilities that provide much more flexibility
in describing and simulating a circuit. The following sections describe these capabilities, as
well as the syntax required to make use of them.

412
26.2.1.1

CHAPTER 26. EXECUTION PROCEDURES


Convergence Debugging Support

When a simulation is failing to converge, the simulator can be asked to return convergence diagnostic information that may be useful in identifying the areas of the circuit in which convergence
problems are occurring. When running through the Nutmeg user interface, these messages are
written directly to the terminal.

26.2.1.2

Digital Nodes

Support is included for digital nodes that are simulated by an event-driven algorithm. Because
the event-driven algorithm is faster than the standard SPICE matrix solution algorithm, and
because all digital, real, int and User-Defined Node types make use of the event-driven
algorithm, reduced simulation time for circuits that include these models can be anticipated
compared to simulation of the same circuit using analog code models and nodes.

26.2.1.3

User-Defined Nodes

Support is provided for User Defined Nodes that operate with the event-driven algorithm. These
nodes allow the passing of arbitrary data structures among models. The real and integer node
types supplied with XSPICE are actually predefined User-Defined Node types.

26.2.1.4

Supply Ramping

A supply ramping function is provided by the simulator as an option to a transient analysis


to simulate the turn-on of power supplies to a board level circuit. To enable this option, the
compile time flag XSPICE_EXP has to be set, e.g. by adding CFLAGS="-DXSPICE_EXP" to
the ./configure command line. The supply ramping function linearly ramps the values of all
independent sources and the capacitor and inductor code models (code model extension) with
initial conditions toward their final value at a rate which you define. A complete ngspice deck
example of usage of the ramptime option is shown below.

26.3. HOW TO CREATE CODE MODELS

413

Example:
Supply ramping option
*
* This circuit demonstrates the use of the option
* " ramptime " which ramps independent sources and the
* capacitor and inductor initial conditions from
* zero to their final value during the time period
* specified .
*
*
. tran 0.1 5
. opti