Data Sheet
FN483.6
Applications
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (oC)
PACKAGE
PKG.
DWG. #
CA3086
-55 to 125
14 Ld PDIP
E14.3
CA3086M96
(3086)
-55 to 125
14 Ld SOIC Tape
and Reel
M14.15
Pinout
CA3086 (PDIP, SOIC)
TOP VIEW
1
2
14
Q5
Q1
3
4
5
12
Q2
11
Q4
6
7
13 SUBSTRATE
10
9
Q3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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CA-3086
Absolute Maximum Ratings
Thermal Information
JA (oC/W)
JC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
110
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
130
N/A
Maximum Power Dissipation (Any one transistor) . . . . . . . . .300mW
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor in the CA3086 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid
undesirable coupling between transistors, the substrate (Terminal 13) should be maintained at either DC or signal (AC) ground. A suitable
bypass capacitor can be used to establish a signal ground.
2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V(BR)CBO
lC = 10A, IE = 0
20
60
V(BR)CEO
IC = 1mA, IB = 0
15
24
V(BR)ClO
IC = 10A, ICI = 0
20
60
V(BR)EBO
IE = 10A, IC = 0
ICBO
VCB = 10V, IE = 0,
0.002
100
nA
ICEO
VCE = 10V, IB = 0,
(Figure 2)
hFE
40
100
Electrical Specifications
PARAMETER
SYMBOL
hFE
VBE
TEST CONDITIONS
VCE = 3V
VCE = 3V
TYPICAL
VALUES
UNITS
IC = 10mA
100
IC = 10A
54
IE = 1 mA
0.715
IE = 10mA
0.800
VBE/T
VCE = 3V, lC = 1 mA
-1.9
mV/oC
Collector-to-Emitter
Saturation Voltage
VCE SAT
IB = 1mA, IC = 10mA
0.23
3.25
dB
NF
CA-3086
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
TYPICAL
VALUES
UNITS
hFE
100
hIE
3.5
hOE
15.6
Open-Circuit Reverse-Voltage
Transfer Ratio (Figure 6)
hRE
1.8 X 10-4
Admittance Characteristics:
Forward Transfer Admittance
(Figure 7)
yFE
31 - j1.5
mS
yIE
0.3 + j0.04
mS
yOE
0.001 + j0.03
mS
yRE
See Figure 10
fT
550
MHz
Emitter-to-Base Capacitance
CEBO
VEB = 3V, IE = 0
0.6
pF
Collector-to-Base Capacitance
CCBO
VCB = 3V, IC = 0
0.58
pF
Collector-to-Substrate Capacitance
CClO
VC l = 3V, IC = 0
2.8
pF
IE = 0
10
102
VCB = 15V
VCB = 10V
VCB = 5V
1
10-1
10-2
10-3
10-4
25
50
75
100
TEMPERATURE (oC)
125
IB = 0
102
VCE = 10V
10
VCE = 5V
1
10-1
10-2
10-3
25
50
75
TEMPERATURE (oC)
100
125
CA-3086
Typical Performance Curves
0.8
VCE = 3V
TA = 25oC
110
120
(Continued)
hFE
100
90
80
70
60
0.1
0.7
VBE
0.6
0.5
0.4
0.01
50
0.01
VCE = 3V
TA = 25oC
10
0.1
100
NORMALIZED h PARAMETERS
VCB = 3V
0.9
0.8
0.7
IE = 3mA
IE = 1mA
IE = 0.5mA
0.5
0.4
-75
-50
-25
25
50
75
100
125
TEMPERATURE (oC)
hOE
hFE
hRE
hIE
0.1
0.01
6
INPUT CONDUCTANCE (gIE)
AND SUSCEPTANCE (bIE) (mS)
hIE
hRE
AT
1mA
0.1
1.0
COLLECTOR CURRENT (mA)
10
30
gFE
10
0
bFE
-10
hFE = 100
hIE = 3.5k
hRE = 1.88 x 10-4
hOE = 15.6S
1.0
20
VCE = 3V
f = 1kHz
TA = 25oC
10
40
10
FIGURE 4. VBE vs IE
FIGURE 3. hFE vs IE
0.6
1.0
4
3
bIE
2
gIE
1
0
-20
0.1
10
FREQUENCY (MHz)
100
0.1
10
FREQUENCY (MHz)
100
CA-3086
Typical Performance Curves
5
4
bOE
3
2
1
gOE
0
0.1
10
FREQUENCY (MHz)
bRE
-0.5
-1.0
-1.5
-2.0
100
10
FREQUENCY (MHz)
VCE = 3V
GAIN BANDWIDTH PRODUCT (MHz)
(Continued)
TA = 25oC
1000
900
800
700
600
500
400
300
200
100
0
FIGURE 11. fT vs IC
10
100
CA-3086
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
0.210
5.33
A1
0.015
0.39
A2
0.115
0.195
2.93
4.95
0.014
0.022
0.356
0.558
C
L
B1
0.045
0.070
1.15
1.77
eA
0.008
0.014
0.735
0.775
18.66
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.005
0.13
0.300
0.325
7.62
8.25
E1
0.240
0.280
6.10
7.11
0.100 BSC
eA
0.300 BSC
eB
0.115
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
0.355
19.68
D1
0.204
14
2.54 BSC
7.62 BSC
0.430
0.150
2.93
14
10.92
3.81
4
9
Rev. 0 12/93
CA-3086
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
0.25(0.010) M
B M
INCHES
-B-
L
SEATING PLANE
-A-
h x 45o
D
-C-
A1
B
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
A1
0.0040
0.0098
0.10
0.25
0.013
0.020
0.33
0.51
0.0075
0.0098
0.19
0.25
0.3367
0.3444
8.55
8.75
0.1497
0.1574
3.80
4.00
e
C
0.10(0.004)
B S
0.050 BSC
1.27 BSC
0.2284
0.2440
5.80
6.20
0.0099
0.0196
0.25
0.50
0.016
0.050
0.40
1.27
NOTES:
MILLIMETERS
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
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Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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