EL2095 Digital System

Comb. Circuit Building Blocks (Ch 6)

Combinational Circuit Building Blocks

Digital circuits can be too complicated to design from scratch

Eg., hundreds of inputs, hundreds of outputs

Huge logic functions and truth tables

We use structured thinking design a complex system as a

collection of simpler subsystems

Standard building blocks: Useful subsystems that turn up

regularly

Use these whenever possible

Dont need to redesign every time

Multiplexers

A digital switch connects data from one of N sources to the

output
Each source is b bits wide
Need S selection inputs, S = log2N
Example application:
computer architecture

En
S

Sel
b
b

N sources

mux

D0
D1
:

output

ALU

registers
mux

DN-1

2-to-1 multiplexer
s
w0

w1

0
1

w0
w1

(b) Truth table

(a) Graphical symbol

w0

w0
s

w1

s
w1

(c) Sum-of-products circuit

(d) Circuit with transmission gates

4-to-1 multiplexer
s

w
w
w
w

00

01

10

11

f = s0 s1w0 + s0 s1w1 + s0 s1w2 + s0 s1w3

0
1
2
3

s0
(a) Graphic symbol

(b) Truth table

w0
s1
w1
f
w2

w3

(c) Circuit

Using 2-to-1 multiplexers to build a 4-to-1

multiplexer
s

s0

w
w

f
1

w
w

Cascading Multiplexers
s3

s2

s1

s0

w0

w1

w2

w3

w4

w5

w6

w7

w8

w9

w10

w11

w12

w13

w14

w15

s0
s1
w0
w3

w4

s2
s3

w7
f
w8
w11

w12
w15

A practical application of multiplexers

A crossbar switch

s = 0: y1 = x1 and y2 = x2
s = 1: y1 = x2 and y2 = x1
s

x1

0
1

x1

y1

x2

y2

s
x2

(a) A 2x2 crossbar switch

y1

0
1

y2

(b) Implementation using multiplexers

Implementing programmable switches in an

FPGA
0/1

i1

0/1

i1
i2

(a)PartoftheFPG
AinFigure3.39

Storage
cel

0/1

0/1

0/1

(b)Im
plem
entationusingpasstransistors

i1
f
i2

0/1

0/1

i2

0/1

0/1

0/1

(c)Im
plem
entationusingm
ultiplexers

0/1

0/1

Multiplexers as Function Generators

Weve seen how FPGAs can use multiplexers to perform

arbitrary logic functions
x1 x2

x2
x1

f0

f0

f1

f1

f2

f2

f3

f3

f(x1, x2)

Essentially,
we directly
represent the
truth table

Problem what if you have more than two variables?

Need a larger (e.g., 8-to-1) mux

Or, separate out the additional variables and use external logic

Example
w1 w2

w2
w1

0
1
1
0

(a) Implementation using a 4-to-1 multiplexer

w1 w2

(b) Modified truth table

w1

w2

w2

w1
w2
f

(c) Circuit

Example
3-input majority function
w1 w2 w3

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

w2
w1

0
0
0
1
0
1
1
1

w1 w2

0
0
1
1

w1 w2 w3

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1

0
0
0
1
0
1
1
1

f(w3)
f0(w3)

f0(w3)

f1(w3)
f2(w3)
f3(w3)

f1(w3)
f2(w3)
f3(w3)

w1 w2

0
1
0
1

0
0
1
1

w3
w3

w2
w1

w3

Example

F = w1 xor w2 xor w3
w1 w2 w3

0
0
1
1
0
0
1
1

0
1
1
0
1
0
0
1

0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1

w2 w3

w2

w1

w3
f
w2 w3

(a) Truth table

(b) Circuit

Example

3 input XOR with 4 to 1 Mux

w1 w2 w3

0
0
1
1
0
0
1
1

0
1
1
0
1
0
0
1

0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1

w3
w3

w2
w1
w3
f

w3
w3

(a) Truth table

(b) Circuit

Example

3 input majority function with 2 to 1 Mux

w1 w2 w3

0
0
1
1
0
0
1
1

0
0
0
1
0
1
1
1

0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1

(b) Truth table

w1

0
1

w2w3
w2 + w3
w1

w2
w3

(b) Circuit

Do it Yourself

f(a,b) = ab + ab (use 4 to 1 Mux)

f(a,b,c) = ab + abc (use 4 to 1 Mux)
f(x,y,z)=m(1,2,6,7) (use 4 to 1 Mux)
f(a,b,c,d)=m(1,3,4,11,12,13,14,15) (use 8 to 1 Mux)

Shannons Expansion Theorem

f (w1 , w2 ..., wn ) = w1 f (0, w2 ..., wn ) + w1 f (1, w2 ..., wn )
yields a circuit with
a 2-to-1 mux

w1
f(0,w2, , wn)
f
f(1,w2, , wn)

Example: 3-input majority function

f (w1 , w2 , w3 ) = w1w2 + w1w3 + w2w3

= w1 (0 w2 + 0 w3 + w2w3 ) + w1 (1 w2 + 1 w3 + w2w3 )
w1 (w2w3 ) + w1 (w2 + w3 + w2w3 )
= w1 (w2w3 ) + w1 (w2 + w3 )
w2
w3

w1
f

Example

f (w1 , w2 , w3 ) = w1w3 + w1w2 + w1w3

= w1 (1 w3 + 0 w2 + 0 w3 ) + w1 (0 w3 + 1 w2 + 1 w3 )
= w1 (w3 ) + w1 (w2 + w3 )
w1
f

w3

w2
(a)Usinga2-to-1m
ultiplexer

Try Expanding different variable

f (w1 , w2 =
, w3 ) w1w3 + w2w3

Use w1:

f = w1 fw1 + w1 fw1 = w1 (w3 + w2 ) + w1 (w2w3 )

Use w2:

f = w2 fw2 + w2 fw2 = w2 (w1w3 ) + w2 (w1 + w3 )

Use w3:

f = w3 fw3 + w3 fw3 = w3 (w2 ) + w3 (w1 )

Examples

f(x,y,z) = m(0,4,6,7)

try expanding using x, y, or z

which is cheapest?

Examples

f(x,y,z) = m(0,4,6,7)

try expanding using x, y, or z

which is cheapest?

f =xyz + xyz + xyz + xyz =yz + xy

Expand x:
f = x f (0, y , z) + x f (1, y , z) = x (yz ) + x (y + z )

Expand y:
f = y f (x ,0, z) + y f (x ,1, z) = y (z ) + y (x)

Expand z:
f = z f (x , y ,0) + z f (x , y ,1) = z (y + x) + z (xy)

Choose y.

Expanding Using 2 Variables

f (w1 , w2 ..., wn ) = w1w2 f (0,0, w3 ..., wn ) + w1w2 f (0,1, w3 ..., wn )
+w1w2 f (1,0, w3 ..., wn ) + w1w2 f (1,1, w3 ..., wn )
w2
w1

yields a circuit with

a 4-to-1 mux

f0
f1
f2
f3

f(x1, , xn)

Example
f (w1 , w2 , w3 ) = w1w3 + w1w2 + w1w3
f = w1w2 fw1w2 + w1w2 fw1w2 + w1w2 fw1w2 + w1w2 fw1w2
= w1w2 (w3 ) + w1w2 (w3 ) + w1w2 (w3 ) + w1w2 (1)
w2
w1
w3
f
1
(b)Usinga4-to-1multiplexer

Example

Implement using 2 to 1 Mux only

f (w1 , w2 , w3 ) = w1w2 + w1w3 + w2w3

=
f w1 (w2w3 ) + w1 (w2 + w3 )
f = w1 g + w1 h
g = w2w3
=
h w2 + w3
=
g w2 (0) + w2 (w3 )
=
h w2 (w3 ) + w2 (1)

w1

w2

0
w3

Example

FPGA LUT (Use 3 of 3 input LUT)

f (w1 , w2 , w3 , w4 ) =
w2w3 + w1w2w3 + w2w3w4 + w1w2w4

w1 fw1 + w1 fw1

= w1 (w2w3 + w2w3 ) + w1 (w2w3 + w2w3w4 + w2w4 )

w1
0
w2
w3

f w1

f w1
w4

(a) Using three 3-LUTs

Example

FPGA LUT (Use 3 of 3 input LUT)

f= w1 (w2w3 + w2w3 ) + w1 (w2w3 + w2w3w4 + w2w4 )

w1
0
w2
w3

f w1

f w1

w4

(a) Using three 3-LUTs

I0I1I2

0w2w3

w2 w3 w4

w1fw1fw1

000

001

010

011

100

101

110

111

Example

Expand using w2

f (w1 , w2 , w3 , w4 ) =
w2w3 + w1w2w3 + w2w3w4 + w1w2w4

=
f w2 fw2 + w2 fw2
= w2 (w3 + w1w4 ) + w2 (w1w3 + w3w4 )
fw2 = fw2
(w3 + w1w4 ) =
(w3 (w1w4 ))
= (w3 (w1 + w4 ))
= (w1w3 + w3w4 )

w2
0
w1
w3
w4

fw

(b) Using two 3-LUTs

Example

Expand using w2

f = w2 (w3 + w1w4 ) + w2 (w1w3 + w3w4 )

w2
0
w1
w3
w4

f w2

(b) Using two 3-LUTs

I0I1I2

w1w3w4

0w2fw2

000

001

010

011

100

101

110

111

Do it yourself

f(w,x,y,z)=m(0,1,5,6,7,9,13,14)

Using 4 to 1 Mux (selector w and x)

Using a Mux Tree of

2 to 1 Mux in the first level

4 to 1 Mux in the second level

Do it yourself

f(w,x,y,z)=m(0,1,5,6,7,9,13,14)

Using 4 to 1 Mux (selector w and x)

f =yz + wxy + xyz + wxy

f (w , x , y , z) = wx f (0,0, y , z) + wx f (0,1, y , z)
+ wx f (1,0, y , z) + wx f (1,1, y , z)
f = wx (yz + y ) + wx (yz + yz + y) + wx (yz) + wx (yz + yz )
f = wx (y ) + wx (y + z) + wx (yz) + wx (yz + yz )

Do it yourself

f(w,x,y,z)=m(0,1,5,6,7,9,13,14)

Using a Mux Tree of

2 to 1 Mux in the first level

4 to 1 Mux in the second level

f = wx (y ) + wx (y + z) + wx (yz) + wx (yz + yz )
f = wx (y ) + wx g1 + wx g2 + wx g3
g1 = y g1 (0, z) + y g1 (1, z) = y (z) + y (1)
g2 = y g2 (0, z) + y g2 (1, z) = y (z) + y (0)
g3 = y g3 (0, z) + y g3 (1, z) = y (z) + y (z )

4 to1 Mux

2 to1 Mux

Do it yourself
f = wx (y ) + wx g1 + wx g2 + wx g3
g1 = y (z) + y (1)
g2 = y (z) + y (0)
g3 = y (z) + y (z )

2 to 1 Mux

74157 Quad 2 to 1 Mux

4 to 1 Mux

74153 Dual 4 to 1 Mux

N-bit Mux Example

Four possible display items

Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles
remaining (M) -- each is 8-bits wide
Choose which to display using two inputs x and y
Use 8-bit 4x1 mux

Decoders

Maps a (small) input code word to a

(large) output code word
n
Example: Binary decoder inputs

w0

wn 1

Input: n-bit binary number

Output: 1-out-of-m code*

3-bit binary code

000
001
010
011
100
101
110
111
*A

Enable

En

y0
2n
outputs
y2n 1

1-out-of-8 code

00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000

code where exactly one of the bits is a 1 (also called a one-hot code)

2-to-4 Decoder, with enable

w0
w1
En

y0
y1
y2
y3

En w1 w0
1
1
1
1
0

0
0
1
1
x

0
1
0
1
x

y0 y1 y2 y3
1
0
0
0
0

0
1
0
0
0

0
0
1
0
0

0
0
0
1
0

w0
y0
w1
y1

y2

Equations

y0 = w1w0En
y1 = w1w0En
y2 = w1w0En
y3 = w1w0En

y3
En

3-to-8 Decoder, with enable

En w2 w1 w0 y7 y6 y5 y4 y3 y2 y1 y0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1

0
0
0
0
0
0
1
0

0
0
0
0
0
1
0
0

0
0
0
0
1
0
0
0

0
0
0
1
0
0
0
0

0
0
1
0
0
0
0
0

0
1
0
0
0
0
0
0

1
0
0
0
0
0
0
0

Equations

y0 = w2w1w0En
y1 = w2w1w0En
y2 = w2w1w0En
y3 = w2w1w0En

y4 = w2w1w0En
y5 = w2w1w0En
y6 = w2w1w0En
y7 = w2w1w0En

Decoders as Function Generators

Select minterms, connect to OR gate

Example: f(A,B) = A XOR B

B
A

w0
w1

En

y0
y1
y2
y3

f(A,B) = m(1,2)

Decoders as Function Generators

Implement f(a,b) = ab + ab using 2 to 4 decoder

f(a,b) = m1 + m3
B
A

w0
w1
En

y0
y1
y2
y3

Decoders as Function Generators

Implement f(a,b,c) = m(0,1,4,6,7) using 3 to 8 decoder

c
b
a

w0
w1
w2

En

y0
y1
y2
y3
y4
y5
y6
y7

Decoder 2 to 4

MSI Part 74xx139 Dual

2 to 4 Decoder
Y0 = (m0) = M0
Y1 = (m1) = M1
Y2 = (m2) = M2
Y3 = (m3) = M3

Decoder 3 to 8

74xx138
Active Low Output

Decoders as Function Generators

Implement f(a,b) = ab + ab using 2 to 4 decoder ( 139)

f(a,b) = m1 + m3 = ((m1) (m3) )
f(a,b) = M0 + M2
Y0
a

B1

Y1

A1

Y2

G1

Y3

Decoders as Function Generators

Implement f(a,b,c) = m(0,1,4,6,7) using 3 to 8 decoder

(138)
a

Y0

Y1

Y2
Y3
Y4

G1

G2A

Y6

G2B

Y7

Y5

Cascading Decoders

Creating a 3:8 decoder from 2:4 decoders

use the third input for the enables

w0
w1
w2

En

w0
w1
En

w0
w1
En

y0
y1
y2
y3

y0
y1
y2
y3

y0
y1
y2
y3

y4
y5
y6
y7

Cascading Decoders

Creating a 4:16 decoder from 2:4 decoders

use one 2:4 decoder for the enables

w0
w1

w0
w1
En
w0
w1

w2
w3

w0
w1

En

En

y0
y1
y2
y3

En
w0
w1
En
w0
w1
En

y0
y1
y2
y3

y0
y1
y2
y3

y0
y1
y2
y3

y4
y5
y6
y7

y0
y1
y2
y3

y8
y9
y10
y11

y0
y1
y2
y3

y12
y13
y14
y15

Exercise

Implement using 3:8 decoder

f(x,y,z) = m(2,3,5)
f(x,y,z) = M(1,4,6,7)

Implement using two 3:8 decoder

f(w,x,y,z) = m(1,5,8,9,12,13)

Decoder as Multiplexer

4-to-1 multiplexer built using a decoder

w0

w1
s0
s1
1

w0
w1
En

y0
y1
y2
y3

f
w2

w3

Decoder as Multiplexer

A 4-to-1 multiplexer built using a decoder and tri-state

buffers
w0

s0
s1
1

w0
w1
En

y0
y1
y2
y3

w1
f
w2

w3

Decoder Applications

Address decoding

Take an n-bit address, select

exactly one device

Internal logic in ROMs

Function generator

Do an arbitrary logic
function with a decoder and
an OR gate

Decoders in ROMs

Recall that a ROM

is a type of PLD

Sel0

Fixed connections
from inputs to
AND gates
Programmable
connections to
OR gates
No Enable,
sometimes also
named
Demultiplexers

a0
a1
am 1

m-to-2m decoder

Sel1
Sel2

Sel2m 1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

Read
Data

dn 1 dn 2

d0

Large ROMs

For many address bits, decoders get too big

Example:

10 bits
size of decoder?

210 = 1024

10

10: 1024
Decoder

1024

Can combine a decoder with a mux to reduce size

Two dimensional ROM decoding

5:32 decoder

A9
A8

y0
y1
y2

A5

y31

A4..A0

32:1 mux
D

Example

Find expression for f(w,x,y,z)

4:1 mux

2:4 decoder
x
w
1

w0
w1
En

y0
y1
y2
y3

y0 = w1 w0
y1 = w1 w0
y2 = w1 w0
y3 = w1 w0

d0
d1
d2
d3
z
y

s0
s1

f = s1 s0 d0 + s1 s0 d1 + s1 s0 d2 + s1 s0 d3

f(w,x,y,z) = w x y z + w x y z + w x y z + w x y z

Encoders

Maps a (small) input

code word to a (large)
output code word
Example: Binary encoder

Input: 1-out-of-m code

Output: n-bit binary
number

w0

y0

2n
inputs

n
outputs
yn 1

w2n 1

Truth
table

w3 w2 w1 w0
0
0
0
1

0
0
1
0

0
1
0
0

1
0
0
0

y1 y0
0
0
1
1

0
1
0
1

Circuit
w0
w1

y0

w2
w3

y1

8-to-3 binary encoder

Truth table

Equations

w7 w6 w5 w4 w3 w2 w1 w0 y2

y1

y0

y2 = w4 + w5 + w6 + w7
y1 = w2 + w3 + w6 + w7
y0 = w1 + w3 + w5 + w7

Priority Encoder

Handles the case where input

may not be a valid 1-out-of-m
code

Just looks at the highest 1;

ignores the rest

To handle the case where

there are no 1s, we have a
special output z

Truth table for 4:2 priority encoder

w3 w2 w1 w0
0
0
0
0
1

0
0
0
1
x

0
0
1
x
x

y1 y0

d
0
1
0
1

0
1
1
1
1

0
1
x
x
x

d
0
0
1
1

w3

y1

w2

y0

w1
w0

4:2 priority encoder

Equations for 4:2 Priority Encoder

Define some intermediate variables

i3 = w3
i2 = w3 w2
i1 = w3 w2 w1
i0 = w3 w2 w1 w0

1xxx 1000
01xx 0100
001x 0010
0001 0001

This forces a valid 1-out-of-4 code

Then

y0 = i1 + i3
y1 = i2 + i3

and

z = w3 + w2 + w1 + w0

i3

i2

i1

i0

y1

y0

8:3 Priority Encoder

Equations
w7
w6
w5
w4
w3
w2
w1
w0

Intermediate Variables
y2

i7 = w7

y1

i6 = w6 w7

y0

i5 = w5 w6 w7
...

Example

74148 8-to-3 priority encoder

i7

i6

i1

i0

y2

y1

y0

Code Converter

w0
w1
w2
w3

BCD to 7 Segment

a
b
c
d
e
f
g

0
0
1
1
0
0
1
1
0
0

w3 w2 w1 w0
0
0
0
0
1
1
1
1
0
0

(a) Code converter

0
0
0
0
0
0
0
0
1
1

0
1
0
1
0
1
0
1
0
1

(b) 7-segment display

a

1
0
1
1
0
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

(c) Truth table

Color Space Converter RGB to CMYK

Color

Often represented as weights

of three colors: red, green, and
blue (RGB)

Perhaps 8 bits each, so specific

color is 24 bits

White: R=11111111,
G=11111111, B=11111111
Black: R=00000000, G=00000000,
B=00000000
Other colors: values in between,
e.g., R=00111111, G=00000000,
B=00001111 would be a reddish
purple

Good for computer monitors,

which mix red, green, and blue
lights to form all colors

Printers use opposite color scheme

Because inks absorb light
Use complementary colors of RGB:
Cyan (absorbs red), reflects green
and blue, Magenta (absorbs green),
and Yellow (absorbs blue)

Color Space Converter RGB to CMYK

Printers must quickly convert

RGB to CMY

R
255

C=255-R, M=255-G, Y=255-B

Use subtractors as shown

G
8

255

255

8
C

8
M

8
Y

Comparators

We often need to compare two numbers

XOR as a 1-bit comparator
a

a
DIFF = a $ b

To compare two N-bit numbers for equality

a0
b0
a1

EQ

b1

:
an-1
bn-1

EQ = (a $ b)

Comparators

Given two 4-bit numbers (unsigned)

AeqB
A
B

AeqB = (a3 $ b3) (a2 $ b2) (a1 $ b1) (a0 $ b0)

AgtB = (a3 b3) +

(a3 $ b3) (a2 b2) +
(a3 $ b3) (a2 $ b2) (a1 b1) +
(a3 $ b3) (a2 $ b2) (a1 $ b1) (a0 b0)
AltB = (a3 b3) +
(a3 $ b3) (a2 b2) +
(a3 $ b3) (a2 $ b2) (a1 b1) +
(a3 $ b3) (a2 $ b2) (a1 $ b1) (a0 b0)

AgtB
4

AltB

Comparator 4 bit
a3
b3

i3

a2
b2

i2

a1
b1

i1

a0
b0

i0

AeqB

AltB

AgtB

Combining Comparators

Example: Compare two 16-bit numbers, using 4-bit

comparators

Magnitude Comparator Example:

Minimum of Two Numbers

Design a combinational component that computes the

minimum of two 8-bit numbers

Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux

If A<B, pass A through mux. Else, pass B.

11000000
MIN

01111111

B
8

0
1
0

8
8

A
B
Igt
Ieq 8-bit magnitude comparator
Ilt

AgtB
AeqB
AltB

1
0
0

I1

I0

8-bit
2x1 mux
8
C

(a)

01111111

B
Min
C
8
(b)

Color Space Converter RGB to CMYK

Try to save colored inks

Expensive
Imperfect mixing C, M, Y doesnt
yield good-looking black

Solution: Factor out the black or

gray from the color, print that part
using black ink

e.g., CMY of (250,200,200)=

(200,200,200) + (50,0,0).

(200,200,200) is a dark gray use black

ink

Color Space Converter RGB to CMYK

Call black part K

(200,200,200): K=200

(Letter B already used for blue)

R
G
B
R GB t o CMY
C
M
Y

Compute minimum of C, M, Y
values

Use MIN component designed

earlier, using comparator and
mux, to compute K
Output resulting K value, and
subtract K value from C, M,
and Y values
Ex: Input of (250,200,200)
yields output of (50,0,0)

8
C

8
M

8
Y

MIN
8
MIN
8

C2

M2

8
Y2

8
K