Setting range
0.1 ... 10 %
Time factor
0.1 ... 30
A time synchronisation input enables the time on the REGDA to be synchronised using a DCF77 signal. This input is
designed for an RS485 (5 V) signal and can be wired as a
time synchronisation bus to several devices. The termination
(terminating resistor) can be switched on and off by using
jumpers on the CPU board.
Time behaviour
U t = const
REG 5A/E
LINEAR
CONST
Trend memory
0 ... 60 s
current influence
(load-dependent setpoint)
Apparent current
Active current
Reactive current
LDC
R : 0 ... 30
X : 0 ... 30
Undervoltage <U
Overvoltage >U
0 ... 25 %
Overcurrent >I
Undercurrent >I
Inhibit High
65 V ... 150 V
0 ... -35 %
0 ... 35 %
Inhibit low
-75 % ... 0 %
1 ... 999 s
(Fast step-up 2...999 s)
Parallel programs
TC in operation - maximum
time
dI*sin(phi)
dI*sin(phi)[S]
dcos (phi)
Master-slave
MSI
MSI2
3 ... 40 s
Page 21
Page 21