VHDL

library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY example1 IS
PORT ( x1, x2, x3
: IN STD_LOGIC ;
f
: OUT STD_LOGIC) ;
END example1 ;
ARCHITECTURE LogicFunc OF example1 IS
BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3) ;
END LogicFunc ;
An entity is a simple declaration of a modules inputs and outputs.
An architecture is a detailed description of modules internal structure or behavior.
Mode : specifying the signal direction
In : the signal is an input to the entity.
Out : the signal is an output of the entity.
Inout: the signal can be read as an input or an output of the entity. This mode is typically used for threestate input/output pins.
Buffer: the signal is an output of the entity, and its value can also be read and written inside the entitys
architecture.
Design of Arithmetic Circuits using VHDL

ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;

Declaration of a package.
PACKAGE fulladd_package IS
COMPONENT fulladd
PORT ( Cin, x, y
: IN STD_LOGIC ;
s, Cout
: OUT STD_LOGIC ) ;
END COMPONENT ;
END fulladd_package ;

A four-bit adder defined using multibit signals.

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT (
Cin
: IN STD_LOGIC ;
X, Y
: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S
: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Cout
: OUT
STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
BEGIN
stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;

stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;

stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;
stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;
END Structure ;
REPRESENTATION OF NUMBERS IN VHDL

SIGNAL C : STD_LOGIC_VECTOR (1 TO 3)
C<=100 , C(1) = 1, C(2) = 0, C(3)=0

SIGNAL X : STD_LOGIC_VECTOR (3 TO 0)
X<=1100, X(3)=1, X(2)=1, X(1)=0, X(0)=0

ARCHITECTURE

An architecture specifies the behavior, interconnections and components of an entity.

Architecture defines the function of an entity. It specifies the relationship between inputs and outputs.

VHDL architectures are categorized in style as:
o Behavior
o Dataflow
o Structural

A design can use any or all of these styles.

Behavior: the behavior of the entity is expressed using sequentially executed procedural code (very
similar to programming languages like C). Sometimes called high-level description

Rather than specifying the structure of a circuit, you specify a set of statements that when executed in
sequence model the behavior of the entity.

Uses process statement and sequential statements (the ordering of statements inside process is important)

Dataflow: specifies the functionality of the entity (the flow of information) without explicitly specifying
its structure
o It specifies how data will be transferred from signal to signal and input to output without the use
of sequential statements.
o No use of process or sequential statements

Structural: an entity is modeled as a set of components connected by signals
o Components are instantiated and connected together

Components: design entities used in other designs. Before an entity can be used in another design it has
to be declared. A component declaration defines an interface for instantiating a component.

A component declaration may be
o in a package: the package is made accessible by use statement
o might be declared in an architecture declarative region using component statement

Every time a component is used it has to be instantiated. Every instantiation has a name.
Selected Signal Assignment

Selected signal assignment is used to assign one of multiple values to a signal, based on some criteria.

The WITH-SELECT-WHEN structure can be used for this purpose.

Syntax:

WITH selection_signal SELECT

signal_name <= value_a WHEN value1_of_selection_signal,
value_b WHEN value2_of_selection_signal,
value_c WHEN value3_of_selection_signal;

All values of selection_signal must be listed in the when clause

We can use the word OTHERS to cover some of the values
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f
: OUT
STD_LOGIC ) ;
END mux2to1 ;
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN '0',
w1 WHEN OTHERS ;
END Behavior ;

Conditional signal assignment

Conditional signal assignment is used to assign
one of multiple values to a signal, based on some
criteria.

The WHEN ELSE structure can be used for this
purpose.

Syntax:
signal_name <= value_a WHEN condition1 ELSE
value_b WHEN condition2 ELSE
value_c;
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END Behavior ;
Process Statement

Sensitivity list: signals to which the process is
sensitive

Each time an event occurs on any of the signals in
sensitivity list, the sequential statements within
the process are executed in the order they appear
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ( w0, w1, s )
BEGIN
IF s = '0' THEN
f <= w0 ;
ELSE
f <= w1 ;
END IF ;
END PROCESS ;
END Behavior ;
If statement

An if statement selects a sequence of statements
for execution based on the value of a condition

The general form of an IF statement:

IF expression THEN
statement,
{statement;}
ELSIF expression THEN
statement,
{statement;}
ELSE
statement,
{statement;}
END IF;
Case Statement
Syntax:
CASE expression IS
WHEN constant_value =>
statement,
{statement;}
WHEN constant_value =>
statement,
{statement;}
WHEN OTHERS =>
statement,
{statement;}
END CASE

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
PROCESS ( w0, w1, s )
BEGIN
CASE s IS
WHEN '0' =>
f <= w0 ;
WHEN OTHERS =>
f <= w1 ;
END CASE ;
END PROCESS ;
END Behavior ;

D<=A&B , D=a2a1a0b2b1b0
E=111&A&00 , E=111a2a1a000
B<=A SLL 1, b2=a1, b1=a0, b0=0
B<=A SRL 2; b2=b1=0, b0=a2
B<=A SRA 1; b2=a2, b1=a2, b0=a1
B<=A ROR 2; b2=a1, b1=a0, b0=a2

ENTITY alu IS
PORT (
s
: IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
F
: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END alu ;
ARCHITECTURE Behavior OF alu IS
BEGIN
PROCESS ( s, A, B )
BEGIN
CASE s IS
WHEN "000" =>
F <= "0000" ;
WHEN "001" =>
F <= B - A ;
WHEN "010" =>
F <= A - B ;
WHEN "011" =>
F <= A + B ;
WHEN "100" =>
F <= A XOR B ;
WHEN "101" =>
F <= A OR B ;
WHEN "110" =>
F <= A AND B ;
WHEN OTHERS =>
F <= "1111" ;
END CASE ;
END PROCESS ;
END Behavior ;

Sequential Logic Synthesis

 Sequential logic elements: latch, flip-flop, register, counter
 Behavior of sequential logic elements can be described using a process statement
 The sequential nature of process statements make them idea for the description of circuits that have
memory and must save their state over time
 The design of sequential logic uses one or more of the following rules:
1. A process that does not include all entity inputs in the sensitivity list (otherwise the
combinational circuit will be inferred)
2. Use incompletely specified if-then-elsif logic to imply that one or more signals must hold their
values under certain conditions
3. Use one or more variables in such a way that they must hold a value between iterations of the
process
 Two most basic types of synchronous elements:
1. D-type latch
2. D-type flip-flop
 D-type latch: a level sensitive memory element that passes the input (D) to output (Q) when enabled
(ENA=1) and hold the value of the output when disabled (ENA=0)
 D-type flip-flop: an edge-triggered memory element that transfers the input (D) to output (Q) when an
active edge transition occurs on its clock. The output value is held until the next active clock edge
 Active clock edge: transition of clock from 0 to 1
 Conditional specification is the most common method in describing behavior of basic memory elements
 This relies on an if statement and assigning a value in only one condition
 Exp: Edge triggered flip-flop
ENTITY flipflop IS
PORT (
D, Clock : IN STD_LOGIC ;
Q
: OUT
STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
 The second method is to use a wait statement
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;
END Behavior ;