Clocked Synchronous State Machine Design

Clocked Synchronous
State Machine Design

Design a clocked synchronous
state machine with two inputs,
A and B and a single output Z
that is equal to 1 if:
A has the same value at each of
the two previous clock ticks, or
B has been 1 since the last time
that the first condition was true.
Otherwise Z should be 0.
Clocked Synchronous
A has the same value at each of the
two previous clock ticks, or
B has been 1 since the last time that
the first condition was true.
Meaning
Initial State
S
INIT
00
Input - AB
01
11
10
Output
Z
0
S*
Meaning
Initial State
Got a 0 on A
Got a 1 on A
S
INIT
A0
A1
00
A0
Input - AB
01
11
A0
A1
S*
10
A1
Output
Z
0
0
0
Clocked Synchronous
Try:
(A,B) = (0,0),(0,0),(0,1),(0,0)
(A,B) = (0,0),(0,0),(0,1),(1,0)
Meaning
Initial State
Got a 0 on A
Got a 1 on A
Got two equal A
S
INIT
A0
A1
OK
00
A0
OK
A0
Input - AB
01
11
A0
A1
OK
A1
A0
OK
10
A1
A1
OK
Output
Z
0
0
0
10
A1
A1
OK
?
Output
Z
0
0
0
1
S*
Meaning
Initial State
Got a 0 on A
Got a 1 on A
Got two equal A
S
INIT
A0
A1
OK
00
A0
OK
A0
?
Input - AB
01
11
A0
A1
OK
A1
A0
OK
OK
OK
S*
Clocked Synchronous
Try the sequence (A,B) = (1,0), (1,0),
(1,1), (0,0).
Meaning
Initial State
Got a 0 on A
Got a 1 on A
Two equal, A=0 last
Two equal, A=1 last
S
INIT
A0
A1
OK0
OK1
00
A0
OK
A0
OK0
A0
Input - AB
01
11
A0
A1
OK
A1
A0
OK
OK0
OK1
OK0
OK1
S*
10
A1
A1
OK
A1
OK1
Output
Z
0
0
0
1
1
State Minimization
Equivalence:
For a given input, two states are
equal if their outputs are the
same, and their next state is the
same or an equivalent one.
S
A
B
C
D
E
F
G
Input 0
A
C
A
E
A
G
A
S*
X
1
B
D
D
F
F
F
F
Output
Z
0
0
0
1
1
1
1
State Assignment
Procedures concerned with
methods for assigning binary
values to states in such a way as
to reduce the cost of the
combinational circuit that
drives the flip-flops.
Methods:
Choose an initial coded state
which the machine can easily be
forced to at reset.
Minimize the number of state
variables that change on each
transition.
Maximize the number of state
variables that do not change
State Assignment
Methods:
Exploit symmetries by assigning
state variables differing only in
one bit to both states or group of
states.
If there are unused states, then
choose the best of the available
state-variable combinations to
achieve the foregoing goal.
Decompose the set of state
variables into individual bits or
fields, with well defined meaning.
Consider using more than the
minimum number of state
variables to make decomposed
assignments possible.
State Assignment
Assignment
State
Name
Simplest
Q1Q3
Decomposed
Q1Q3
One-hot
Q1Q5
Almost One-hot
Q1Q4
INIT
000
000
00001
0000
A0
001
100
00010
0001
A1
010
101
00100
0010
OK0
011
110
01000
0100
OK1
100
111
10000
1000
Table 7-7
Possible state
assignments for the
state machine in
Table 7-6.
Unused states:
Minimal risk assumes that it is
possible for the state machine to get into
one unused or illegal state.
Minimal cost assumes that the state
machine will never enter an unused
state.
Designing State Machines

Using State Diagrams
State-diagram design is simpler
but it is more prone to errors.
State table is an exhaustive listing
of the next states for each
state/input combination. No
ambiguity is possible.
When constructing a state
diagram there is no guarantee
that the transition expressions
written on the arcs leaving a
particular state, cover all input
combination exactly once.

Design a state machine to control the
tail lights of a 1965 Ford
Thunderbird. The tail lights are
composed of three light on each side
which operate for the turns in the
manner shown in the picture below.
CALIFORNIA
ZOTTFFS
LC
Copyright 2000 by Prentice Hall, Inc.
Digital Design Principles and Practices, 3/e
LB
LA
RA
RB
RC

(a)
LC
LB
LA
(b)
RA
RB
The state machine has:

Three inputs: left, and right turns,
and hazard.
Six outputs: LA, LB, LC, RA, RB,
and RC.
Free running clock with frequency
equal to the flashing rate.
RC

L2
L1
L3
LEFT
1
(LEFT + RIGHT + HAZ)
HAZ
IDLE
Output Table
State
IDLE
L1
L2
L3
R1
R2
R3
LR3
LC LB LA RA RB RC
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
RIGHT
R1
R3
LA = L1+L2+L3+LR3
LB = L2+L3+LR3
LC = L3+LR3
RA = R1+R2+R3+LR3
RB = R2+R3+LR3
RC = R3+LR3
R2
LR3

Mutual exclusion: For each state the
logical product of each pair of transition
expression on arcs leaving that state is
zero.
All inclusion: For each state the logical
sum of the transition expressions on all
arcs leaving the state is one.
L2
L3
L1
LEFT HAZ RIGHT

1
1

IDLE
HAZ + LEFT RIGHT
1
RIGHT HAZ LEFT
R3
R1
R2
LR3

L2
HAZ
HAZ
L3
HAZ
L1
LEFT HAZ RIGHT
HAZ
1
1

IDLE
HAZ + LEFT RIGHT
LR3
HAZ
RIGHT HAZ LEFT
R3
R1
HAZ
HAZ
R2
HAZ

IDLE state of 000.
Q1 and Q0 are used to count in gray code
sequence (IDLEL1L2L3IDLE)
(IDLER1R2R3IDLE).
Q2 identifies LEFT or RIGHT turn.
HAZ state of 100.
T ab le 7 -16
State assignment
for T-bird tail-lights
state machine.
State
Q2
Q1
Q0
IDLE
L1
L2
L3
R1
R2
R3
LR3

S
Q2
Q1
Q0
Transition Expression
Q2
Q1
Q0
IDLE
IDLE
IDLE
LEFT HAZ RIGHT
L1
IDLE
HAZ + LEFT RIGHT
LR3
IDLE
RIGHT HAZ LEFT
R1
L1
HAZ
L2
L1
HAZ
LR3
L2
HAZ
L3
L2
HAZ
LR3
L3
IDLE
R1
HAZ
R2
R1
HAZ
LR3
R2
HAZ
R3
R2
HAZ
LR3
R3
IDLE
LR3
IDLE
T ab l e 7-17
Transition list for
T-bird tail-lights
state machine.
Feedback Sequential
Circuits
Fundamental mode circuits:
Most common example of
feedback sequential circuits.
Inputs are not normally allowed
to change simultaneously.
Feedback sequential circuits

may be Mealy or Moore
circuits.
A circuit with n feedback loops
has n binary state variables and
2n states.
Feedback Sequential
Circuits
Analysis:
Assumes that input changes occur one
at a time to allow enough time between
successive changes for the circuit to
settle into a internal stable state.
Break the feedback loops so that the
next value stored in each loop can be
predicted as a function of the circuit
inputs and the current value stored in
all loops.
(C D)
C D+(C D+Y)
Q
Y
C
Y
(C D)
QN
C D+Y

Feedback Sequential
Circuits
(C D)
C D+(C D+Y)
Q
Y
C
Y
QN
(C D)
C D+Y

C D
Y
00
01
11
10
Y*
Y* = (C D ) + (C D + Y)
Y* = C D + C Y + D Y
Q = Y* = C D + C Y + D Y
QN = C D + Y
Feedback Sequential
Circuits
Total state: combination of internal state
(value of feedback loop) and input state
(current input value) .
Stable total state: Total state whose next
state predicted by the state table is the same
as the current internal state.
Unstable total state: Total state whose next
state predicted by the state table is the same
as the current internal state.
Note that Q and QN are outputs, not state
variables.
CD
CD
00
01
11
10
00
01
11
10
S0
S0 , 01
S0 , 01
S1 , 11
S0 , 01
S1
S1 , 10
S1 , 10
S1 , 10
S0 , 01
Y*
S*, Q QN
Feedback Sequential
Circuits
CD
00
01
11
10
S0
S0 , 01
S0 , 01
S1 , 11
S0 , 01
S1
S1 , 10
S1 , 10
S1 , 10
S0 , 01
S*, Q QN
CD
00
01
11
10
S0
S0 , 01
S0 , 01
S1 , 11
S0 , 01
S1
S1 , 10
S1 , 10
S1 , 10
S0 , 01
S*, Q QN
Simultaneous input changes dont

always cause unpredictable
behavior.
Races
A race is said to occur when multiple
internal variables change state as a result of
a single input changing state.
Noncritical race: the final state does not
depend on the order in which the state
variables change.
Starting at state 011/00 change CLK to 1.
CLK D
Y1 Y2 Y3
00
01
11
10
000
010
010
000
000
001
011
011
000
000
010
010
110
110
000
011
011
111
111
000
100
010
010
111
111
101
011
011
111
111
110
010
110
111
111
111
011
111
111
111
Y1 Y2 Y3
Races
Critical race: the final state depends on the
order in which the state variables change.
State 010/10 has been changed from 000 to
110.
Try starting at state 011/00 change CLK to
1 and see what state you end up at.
CLK D
Y1 Y2 Y3
00
01
11
10
000
010
010
000
000
001
011
011
000
000
010
010
110
110
110
011
011
111
111
000
100
010
010
111
111
101
011
011
111
111
110
010
110
111
111
111
011
111
111
111
Y1 Y2 Y3
State Tables and Flow

Tables
Once it has been determined that a
transition table does not have any
critical races, the state-variable
combinations can be named and
outputs can be determined to obtain
a state/output table.
CLK D
CLK D
01
11
10
Y1 Y2 Y3
00
01
11
10
00
000
010
010
000
000
S0
S2 , 01
S2 , 01 S0 , 01 S0 , 01
001
011
011
000
000
S1
S3 , 10
S3 , 10 S0 , 10 S0 , 10
010
010
110
110
000
S2
S2 , 01 S6 , 01 S6 , 01 S0 , 01
011
011
111
111
000
S3
S3 , 10 S7 , 10 S7 , 10 S0 , 01
100
010
010
111
111
S4
S2 , 01 S2 , 01 S7 , 11 S7 , 11
101
011
011
111
111
S5
S3 , 10 S3 , 10 S7 , 10 S7 , 10
110
010
110
111
111
S6
S2 , 01 S6 , 01 S7 , 11 S7 , 11
111
011
111
111
111
S7
S3 , 10
Y1 Y2 Y3
S7 , 10 S7 , 10 S7 , 10
S* , Q QN

Tables
Flow table eliminates:
Rows for unused internal states (states
that are stable for no input combination).
Next state entries for total states that
cannot be reached from a stable total
state as the result of a single input
change.
It eliminates multiple hops and show

only the ultimate destination of each
transition.
CLK D
00
01
CLK D
11
10
00
01
11
10
S0
S2 , 01 S2 , 01 S0 , 01 S0 , 01
S0
S2 , 01 S6 , 01 S0 , 01 S0 , 01
S1
S3 , 10 S3 , 10 S0 , 10 S0 , 10
S2
S2 , 01 S6 , 01
S0 , 10
S2
S2 , 01 S6 , 01 S6 , 01 S0 , 01
S3
S3 , 10 S7 , 10
S0 , 01
S3
S3 , 10 S7 , 10 S7 , 10 S0 , 01
S6
S2 , 01 S6 , 01 S7 , 11
S4
S2 , 01 S2 , 01 S7 , 11 S7 , 11
S7
S3 , 10 S7 , 10 S7 , 10 S7 , 10
S5
S3 , 10 S3 , 10 S7 , 10 S7 , 10
S6
S2 , 01 S6 , 01 S7 , 11 S7 , 11
S7
S3 , 10 S7 , 10 S7 , 10 S7 , 10
S* , Q QN
S* , Q QN

Tables
Assume internal state S0/10.

Change D to 1, then 0.
Change clock to 0.
Change D to 1, then 0.
What happens when clock changes
to 1.
CLK D
00
01
11
10
S0
S2 , 01 S6 , 01 S0 , 01 S0 , 01
S2
S2 , 01 S6 , 01
S0 , 10
S3
S3 , 10 S7 , 10
S0 , 01
S6
S2 , 01 S6 , 01 S7 , 11
S7
S3 , 10 S7 , 10 S7 , 10 S7 , 10
S* , Q QN
SSI Latches and

Flip-Flops
PLDs and FPGAs have to a large
extent eliminated their use.
PR
D
PR
J
4
CLK
74x112
74x109
74x74
2
PR
J
CLK
K
CLR
CLR
74x375
4
1
CLK
K
CLR
15
12
12
11
PR
D
14
PR
J
CLK
Q
13
13
10
11
PR
J
13
CLK
K
CLR
15
2D
3,4C
3D
74x112
74x109
12
CLR
10
11
74x74
1D
10
1,2C
12
15
4D
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
3
2
5
6
11
10
13
14
CLK
K
CLR
14

Debouncer
Bouncing Behavior of mechanical
of switches which causes their
contacts to close, and open several
times before finally reaching a
resting or stable closed state.
Typically switches bounce for 10
20 ms, which is a very long time
compared to the switching speeds of
logic gates.
+5V
push
(a)
74LS04
DSW
SW_L
push
(b)
SW_L
first contact
bounce
+5V
GND
DSW
1
0
Debouncer
Debouncing providing a single
signal change or pulse for each switch
transition.
74LS04
SW_L
SW_L
SW
push
(a)
74LS04
SW
DSW
push
VOH
SW
VOL
GND
first contact
(b)
VOH
SW_L
VOL
GND
1
DSW
0
+5 V
R
74LS00
SWU_L
push
DSW_L
+5 V
R
SWD_L
DSW
bounce
Registers
Collection of two or more D flipflops with a common clock input.
Often used to store a collection of
related bits, such as a byte of data.
May also be used to store unrelated
bits of data.
1D
(2)
(4)
D
(3)
CLK
1Q_L
(a)
CLR
2D
(7)
(5)
D
(6)
CLK

1Q
2Q
2Q_L
CLR
74x175
(b)
3D
(10)
(12)
Q
(11)
CLK
CLR
3Q
3Q_L
CLR
12
4D
(15)
(13)
D
(14)
CLK
CLR_L
(9)
CLK
CLR
(1)
CLK
1D
2D
3D
3Q
3Q
4D
4Q
4Q
4Q
4Q_L
13
1Q
1Q
2Q
2Q
10
11
15
14
Registers
OE_L
(a)
1D
(1)
(3)
D
(2)
CLK
2D
(4)
D
(5)
CLK
3D
(7)
(6)
(8)
(b)
2Q
D
CLK
4D
1Q
3Q
D
(9)
CLK
4Q
74x374
11
1
5D
CLK
(13)
(12)
OE
3
4
7
8
13
14
17
18
1D
2D
3D
4D
5D
6D
7D
8D
D
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
5Q
2
5
6
6D
(14)
D
(15)
CLK
6Q
12
15
7D
(17)
D
(16)
16
CLK
7Q
19
8D
CLK
(18)
(11)
D
CLK
(19)
Q
8Q

Registers
74x273
11
1
74x373
11
CLK
CLR
3
4
7
8
13
14
17
18
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
C
OE
1D
4
2D
7
3D
5
6
4D
13
5D
14
6D
9
12
15
17
6Q
16
7Q
19
8Q
18
7D
8D
1Q
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q

(a)
(b)
74x377
11
1
3
4
7
8
13
14
17
18
CLK
EN
1D
2D
3D
4D
5D
(19)
1Q
5
2Q
8D
(18)
3Q
9
4Q
12
6D
5Q
15
6Q
7D
7Q
8D
8Q
EN_L
(1)
16
19

CLK
(11)
Q
CK
8Q
PLD
I1
I2
I3

I4
P1
P2
P3
P4
P5
P6
O1
O2
O3
I1
I2
I3
I4
P1
P2
P3
P4
P5
P6
O1
O2
O3
PLD
VCC
I1
I1
I2
I2
I3
I3
I4
I4
I1
I2
I3
I4

P1
P2
P3
P4
P5
P6
VCC
O1
O2
O3

VCC
floating gate
nonfloating gate
active-low
input lines
active-high AND lines
PLD
(1)
CLK
0 1 2 3
4 5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
(19)
IO1
(2)
I1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
(18)
O2
(3)
I2
(17)
O3
(4)
I3
(16)
O4
(5)
I4
(15)
O5
(6)
I5
(14)
O6
(7)
I6
(13)
O7
(8)
I7
56
57
58
59
60
61
62
63
(9)
I8
(12)
IO8
(11)
OE_L
PLD
(1)
CLK
0 1 2 3
0
1
2
3
4
5
6
7
4 5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
(19)
O1
(2)
I1
8
9
10
11
12
13
14
15
I2
I3
(18)
O2
(3)
16
17
18
19
20
21
22
23
(17)
O3
(4)
24
25
26
27
28
29
30
31
(16)
O4
(5)
I4
32
33
34
35
36
37
38
39
(15)
O5
(6)
I5
40
41
42
43
44
45
46
47
(14)
O6
(7)
I6
48
49
50
51
52
53
54
55
(13)
O7
(8)
I7
56
57
58
59
60
61
62
63
I8
(12)
O8
(9)
(11)
OE_L
PLD
OE CLK
Registered
output logic macrocell
OE CLK
Combinational
output logic macrocell
Q
Q
(a)
(b)

Clocked Synchronous State Machine Design

Diunggah oleh

Informasi Dokumen

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Clocked Synchronous State Machine Design

Diunggah oleh

Hak Cipta:

Format Tersedia

Clocked Synchronous

State Machine Design

Designing State Machines

Designing State Machines

Designing State Machines

The state machine has:

Designing State Machines

(LEFT + RIGHT + HAZ)

Designing State Machines

LEFT HAZ RIGHT

(LEFT + RIGHT + HAZ)

HAZ + LEFT RIGHT

Designing State Machines

(LEFT + RIGHT + HAZ)

HAZ + LEFT RIGHT

Designing State Machines

Designing State Machines

(LEFT + RIGHT + HAZ)

LEFT HAZ RIGHT

HAZ + LEFT RIGHT

RIGHT HAZ LEFT

Feedback sequential circuits

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Simultaneous input changes dont

State Tables and Flow

State Tables and Flow

It eliminates multiple hops and show

State Tables and Flow

Assume internal state S0/10.

SSI Latches and

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

Copyright 2000 by Prentice Hall, Inc.

active-high AND lines

Anda mungkin juga menyukai