PROMISE OF TUNNEL DIODE

INTEGRATED CIRCUITS
Alan Seabaugh
Department of Electrical Engineering
University of Notre Dame
Notre Dame, IN
Acknowledgements: P. Barrios, B. Bate, P. Berger, T. Blake,
B. Brar, T. Broekaert, K. Clark, M. Dashiell, X. Deng, W. Frensley,
G. Frazier, J. Gunther, J. Hellums, K. Hobart, W. Kirk,
J. Kolodzey, R. Lake, J. Lyding, E. Maldonado, C. Marrian,
P. Mazumder, T. Moise, F. Morris, G. Pomrenke, S. Rommel,
G. Spencer, P. Thompson, T. Troeger, P. van der Wagt, G. Witt.

A. Seabaugh, Promise of Tunnel Diode Integrated Circuits, Tunnel Diode and CMOS/HBT
Integration Workshop, December 9, 1999, Naval Research Laboratory, Washington, DC.

THE p +n+ TUNNEL DIODE

High speed, multivalued I-V, with negative differential resistance
depletion region
0.15

Current (mA)

300 K

0.1

EC

0.05

EF

0
1N2927 Si
tunnel diode

-0.05
-0.25

0.25
Voltage (V)

0.5

0.75
Si Plot 1

EV

Scanning electron micrographs of a Si 1N2927

(no longer sold, Microsemi Corp., CA)
70 m

20 m

The demise of the tunnel diode [in the 1960s] was signaled by the arrival in force of the
Swartz, In perspective: the tunnel diode, 1986 IEEE Int. Solid-State
Circuits Conf., pp. 278-280. Until recently, processes for forming tunnel diodes were still based
on the discrete approach shown above.

MAIN POINTS
Circuit simulations using tunnel diodes (TD) show benefit
RTD/HEMT technology shows feasibilty
Silicon TDs now demonstrated: Matsushita, Toshiba, U. Delaware,
NRL, Raytheon, Hughes, Max-Planck Institute
Time is right to add TD to silicon bipolar and MOS
Relatively low risk
High benefit/cost

Figure 1. Circuit schematic diagrams for (a) RTD/HEMT

and (b) HEMT comparators designed for 25 GHz
operation.

A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, ResonantTunneling Mixed-Signal Circuit Technology, Solid State Electronics 43 (1999) 1355-1365.

CIRCUIT DESIGNS SHOW

TD PERFOMANCE BOOST
SPICE models: 18c07 0.25 m CMOS and resonant tunneling diode models
fit to both dc and S-parameter measurements

TD in combination with CMOS reduces the number of devices,

interconnects, and delay stages
TD improves area, speed, and power by the following factors:
Embedded RAM: vs. 6T
vs. 1T
Latches, flip flops, and
shift registers
Dynamic logic and
pass-transistor logic
Quantizers

Area
2.2x
(1.4x)
1.6-3x

Speed
(3x)
same
1.7-2.2x

Active Power
2.1-2.4x

Static Power
8x
23x
(1.1-1.7x)

1.3-1.4x

1.2-2.3x

1.5-1.8x

same

3.5x

2.2x

5.8x

2.3x

( ) performance reduction

Numbers which are not in parenthesis represent improvements obtained using the tunnel diode,
e.g. in line 1, the tunnel diode embedded RAM occupies 2.2x less area than the 6T cell and
dissipates 8x less standby power, while numbers in parenthesis indicate a performance reduction,
e.g. again in line 1, 3x slower access speed for the TD circuit vs the 6T SRAM.

A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G. Frazier,

Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,
IEDM Technical Digest 1998, pp. 429-432

Tunnel Diode For Embedded Memory

WL

0V

I3

TD1
TD2

I1
I2

BL

CURRENT ( pA)

1V
0V

I 2 +I3

16
12

I2

I1
I3

4
0
0

0.4

0.8

NODE VOLTAGE (V)

(a)
(b)
Fig. 3: CMOS/TD SRAM cell: (a) schematic diagram
and (b) current-voltage relations.

TABLE 1
COMPARISON OF CMOS/TD SRAM CELLS WITH CMOS
EMBEDDED DRAM AND 6T SRAM
Process
Cell
CMOS
CMOS
CMOS
+TD
CMOS
+Cap
CMOS
+Cap+TD

6T
SRAM
1T+1Cg
DRAM
1T+1Cg+2TD
SRAM
1T+1Cst
DRAM
1T+1Cst+2TD
SRAM

Area
( m2)
7.00

Density
Ratio
(x6T)
1.0

Cycle
Time
(ns)
4

Standby
Current
(pA)
7

5.79

1.2

18

31

7.02

1.0

18

2.26

3.1

12

21

3.15

2.2

12

0.9

A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G. Frazier,

Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,
IEDM Technical Digest 1998, pp. 429-432

TD-Simplified Keeper Circuit

CK
VD D

CK

VD D
OUT

IN

IN
CK

OUT

CK

(a)

(b)

Fig.6: Static shift register comparison: (a) CMOS/TD

and (b) CMOS only.

A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G. Frazier,

Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,
IEDM Technical Digest 1998, pp. 429-432.

0.05

OUT (V)

0.04
0.03
0.02
0.01
0
0

200

400

600

TIME (ps)

800

1000
3771trtf plot

Figure 19. Resonant tunneling diode clock generator: (a)

schematic diagram and (b) 6.5 GHz output signal
waveform.
A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, ResonantTunneling Mixed-Signal Circuit Technology, Solid State Electronics 43 (1999) 1355-1365.

Figure 6. Scanning electron micrograph of a completed

RTD/HEMT quantizer circuit showing the threedimensional integration of RTDs on HEMT source and
drain contact regions.

A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, ResonantTunneling Mixed-Signal Circuit Technology, Solid State Electronics 43 (1999) 1355-1365.

WHAT ARE THE RISKS

No new materials
Similar to adding resistor, capacitor, or diode
Key technical challenges:
Milestones
Demonstrate production compatible tunnel diode (TD)
Demonstrate TD uniformity
Demonstrate TD reproducibility
Demonstrate TD reliability

Risk
Low
v
v

High

v
v

BENEFITS FROM SUCCESSFUL

IMPLEMENTATION OF Si TD
1.

Extends life of existing facilities by increasing circuit

performance without scaling

2.

Provides a technology differentiator, like low k, or Cu

interconnect

QMOS ROADMAP
Integration of the quantum device (tunnel diode) with CMOS is
called QMOS.

1000

1000

Silicide,
Local
interconnect

Cost (uc/device)

100

10

Cu
Low k
SOI?

QMOS?

10

10

Delay x Power (fJ/device)

No known
solutions - SIA 97

Datapoints: SIA National Roadmap, 1997 Ed.

Lines: qualitative
1 logic function = 4 devices in CMOS
1
1996 250

1997

1999
180
1999

150 2002130
2001
2003

2005100

2006

200870

2009

2011 50

Feature Size
2012 Production Year

CONCLUSIONS
Circuit simulations using tunnel diodes (TD) show benefit
RTD/HEMT technology shows feasibilty
Silicon TDs now demonstrated: Matsushita, Toshiba, U. Delaware,
NRL, Raytheon, Hughes, Max-Planck Institute
Time is right to add TD to silicon bipolar and MOS
Relatively low risk
High benefit/cost