Lab 1 MOSFET DC Ids Vds

Characteristic Curve

Prepared by: RE-ANN CRISTINE O. CALIMPUSAN

EE 272

Submitted to: PROF. ALLEN DELA CERNA LOWATON

Laboratory Step
Step 1:
Connect the NMOS and PMOS as in figure 1.2(a). Simulate the Ids-Vgs characteristics curve as in figures 1.2(b)-(c).

HSPICE code for NMOS

VDD
DC

Drain
Gate

Source

Output Waveform

Region of operation is saturation as expected .This is

because drain voltage is equal to gate voltage .Thus
satisfying the condition that in order to be in
saturation
since
equal
therefore

is always greater than

HSPICE code for PMOS

Output Waveform

Drain

VDD

Gate
Source

DC

Region of operation is saturation as expected .This is

because drain voltage is equal to gate voltage .Thus
satisfying the condition that in order to be in
saturation
since
equal
therefore

is always greater than

Step 2
Disconnect the gate and the drain of the MOS of figure 1.2(a). Then assign different values of V gs to its gate terminal. Simulate the Ids-Vds
characteristics curve as in figure 1.3(a)-(b).
HSPICE code for NMOS

Output Waveform

HSPICE code for PMOS

Output Waveform

Step 3
Follow Step 2, change the channel length. Simulate the Ids-Vds characteristics curve as in figure 1.4(a)-(b).
HSPICE code for NMOS

Output Waveform

HSPICE code for PMOS

Output Waveform

Step 4
Set

to a value smaller than

HSPICE code for NMOS

to operate the MOS in subthreshold region. Simulate

Output Waveform

characteristics curve as figure 1.5(a)-(b).

HSPICE code for PMOS

Output Waveform

Questions/Ans:
1. If we increase W/L of the device in Step 1, what changes will occur to the curves in figures 1.2(b)-(c)
Increasing W/L will increase the value of Id, as seen on the figure below. Also note that it conforms to the drain current
equation at saturation
, assuming no effect of channel modulation, thus it can deduce that
at saturation is direct proportional to W.

2. When the dimensions

equal

does

equal

Yes, approximately they are equal. Assuming operating in saturation region and neglecting channel modulation effect
then
and
. Further assume that
=1 ,
=
and
-

so these variable will cancel and what we have left are

when the dimensions

equal

and

. Thus

Is just equal to

3. What is the relationship between the channel length and the slope of the curve in figure 1.4(a)-(b)?
The channel length and the slope of the curve is inversely proportional as can be seen in figure 1.4(a)-(b), increasing the length
will lessen the slope of the curve.

4. When the MOSFET operates in subthreshold region, what is the relationship between
and the slope of the curves in figures
1.5(a)-(b)?What device either PMOS or NMOS, has the larger slope?Why?
In the output waveform of Step 4 it can be seen that as
falls below
drain current drops at finite rate. exhibits
an exponential dependencies on . As to the question which has the larger slope , it is also depicted in the output waveform
that NMOS has slightly greater value of slope compared to PMOS. This also confirms that mobility of NMOS is greater than
PMOS. Slope of PMOS and NMOS shown below.

Output Waveform of NMOS and its derivative

Output Waveform of PMOS and its derivative