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Behavioral modeling of regenerative comparator using verilog-AMS. Utilizes ADC comparator design and Verilog-AMS coding.

© All Rights Reserved

675 tayangan

Behavioral modeling of regenerative comparator using verilog-AMS. Utilizes ADC comparator design and Verilog-AMS coding.

© All Rights Reserved

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VERILOG-AMS

B.E., Osmania University, India, 2004

PROJECT

the requirements for the degree of

MASTER OF SCIENCE

in

ELECTRICAL AND ELECTRONIC ENGINEERING

at

CALIFORNIA STATE UNIVERSITY, SACRAMENTO

SPRING

2011

VERILOG-AMS

A Project

by

Approved by:

__________________________________, Committee Chair

Thomas W. Matthews, Ph.D.

__________________________________, Second Reader

Perry L. Heedley, Ph.D.

____________________________

Date

ii

I certify that this student has met the requirements for format contained in the University

format manual, and that this project is suitable for shelving in the Library and credit is to

be awarded for the project.

Preetham B. Kumar, Ph.D.

Department of Electrical and Electronic Engineering

iii

________________

Date

Abstract

of

BEHAVIORAL MODELING OF A REGENERATIVE COMPARATOR USING

VERILOG-AMS

by

Comparators are widely used in mixed-signal systems. They are an essential building

block of any analog-to-digital converter architecture. Regenerative comparators are

typically used in high-speed analog-to-digital convertor designs. This particular

architecture has two main characteristics that make it differentiable from the other

architectures. First is the positive feedback during the regenerative phase to achieve high

gain and the second is the cancellation of the memory of previous comparison results

during the reset phase.

A behavioral model of any circuitry block is always helpful, before creating the actual

design, to understand the tradeoffs during system design. Verilog-AMS provides an

extended capability to model any analog or digital block, so as to seamlessly integrate the

behavioral block into the actual design consisting of a combination of analog and digital

blocks. A mapping between the analog and digital domains enhances the (re)usability of

iv

designs for mixed-signal blocks. Since Verilog-AMS actively supports the mixed-signal

approach, the interchange of digital and analog blocks is straightforward. This work will

result in a behavioral model for a regenerative comparator written in Verilog-AMS.

The project presents the behavioral model of a regenerative comparator written in

Verilog-AMS. The model is simulated using the time-windowing function to find the

sensitivity of the comparator to pre- and post-clock inputs. The key specifications

described in [3] by Thomas Matthews will be used to compare Verilog-AMS behavioral

model circuit simulation results with analytical results.

Thomas W. Matthews, Ph.D.

_______________________

Date

ACKNOWLEDGEMENTS

Behind every achievement lies an unfathomable sea of gratitude to those who actuated it,

without whom it would never have come into existence.

It is with my deepest gratitude and honor that I convey my thanks to Dr. Thomas W.

Matthews, for his exemplary guidance, unending support and for giving me an

opportunity to work under his guidance. I am very indebted to Dr. Perry L. Heedley for

patiently reviewing my work as the second reader and for providing his valuable support

to make this project successful.

I would like to extend my gratitude to Dr. Dennis Dahlquist for his guidance and

contribution to the project. Special thanks go to Rajdeep Mukhopadhyay of National

Semiconductor Corporation for his help during the initial phases of the project.

I would like to thank my parents, Venugopal and Mallika, and brother, Hari, who have

been a constant source of my energy. Last but not the least; I thank all my friends who

implicitly or explicitly helped in the success of this project with their constructive

criticism and encouragement.

vi

TABLE OF CONTENTS

Page

Acknowledgements ............................................................................................................ vi

List of Tables ..................................................................................................................... ix

List of Figures ..................................................................................................................... x

Chapter

1. INTRODUCTION .......................................................................................................... 1

1.2 Regenerative Comparators ................................................................................. 2

1.3 A High-speed CMOS Comparator ..................................................................... 3

1.4 Project Objective ................................................................................................ 4

1.5 Report Organization ........................................................................................... 5

2. VERILOG-AMS MODELING ...................................................................................... 6

2.2 Language Basics ................................................................................................. 7

2.3 Model Descriptions ............................................................................................ 8

2.4 Test-bench Design Components ......................................................................... 9

2.4.1 Stimulus Generator ................................................................................ 10

2.4.2 Output Evaluator .................................................................................... 11

2.5 Analog Modeling Development ....................................................................... 11

3. COMPARATORS ........................................................................................................ 13

vii

3.3 Mathematical Model......................................................................................... 16

4. REGENERATIVE COMPARATOR VERILOG-AMS MODEL ............................... 22

4.2 Voltage Limiting Diodes .................................................................................. 24

4.3 Voltage Controlled Current Source .................................................................. 25

4.4 Input Signal Limiting ....................................................................................... 26

4.5 Tweaking the Model ......................................................................................... 28

5. SIMULATION RESULTS ........................................................................................... 29

5.2 Simulation of the Comparator Model ............................................................... 29

5.3 Dynamic Offset Test Bench ............................................................................. 33

5.4 Servo Loop Test Using DOTB ......................................................................... 34

5.5 Simulating the Design ...................................................................................... 37

5.6 Automating the Simulation Environment......................................................... 38

5.7 Interpreting Simulation Results ........................................................................ 39

6. CONCLUSIONS .......................................................................................................... 51

6.2 Future Work ..................................................................................................... 52

Appendix A Source Code for Behavioral Model and Test Bench ................................... 53

Appendix B Verilog-AMS Functions and Operators....................................................... 70

References ......................................................................................................................... 74

viii

LIST OF TABLES

Page

1. Table 1 Verilog-AMS Built-in Mathematical Functions ............................................ 70

2. Table 2 Verilog-AMS Mathematical Operators ......................................................... 72

3. Table 3 Verilog-AMS Built-in Analog Operators. ..................................................... 72

4. Table 4 Common Verilog-AMS Analog Event Types. .............................................. 73

ix

LIST OF FIGURES

Page

1. Figure 1.1 Block diagram of a typical Clocked Comparator ........................................ 3

2. Figure 1.2 Schematic of a high-speed CMOS Comparator [7]. The SR Latch is the

circuitry on the right with outputs labeled Q and Q-bar. .............................................. 4

3. Figure 2.1 Reference Diode Model and Equation. ....................................................... 9

4. Figure 3.1 Schematic of a typical regenerative comparator. ...................................... 14

5. Figure 3.2 Two cross-coupled current sources represent the cross-coupled latch pair.

..................................................................................................................................... 15

6. Figure 3.3 Model used for practical comparator [3]. .................................................. 17

7. Figure 3.4 Difference-mode half-circuit (

). ................................................. 17

8. Figure 3.5 Comparator Impulse response and windowing function [3]. .................... 20

9. Figure 4.1 Initial Macro model of a regenerative comparator. ................................... 23

10. Figure 4.3 Regenerative comparator with differential voltage inputs. ....................... 26

11. Figure 4.4 Step response of the model at various clock edges ................................... 27

12. Figure 4.5 Updated Voltage Controlled Current Source (VCCS) schematic, by adding

additional diodes and additional pull down resistance. This entire cell replaces the

single gm-cell in the Figure 4.3. .................................................................................. 28

13. Figure 5.1 Circuit schematic used for simulation ....................................................... 30

14. Figure 5.2 Simulation of the comparator model with clock rate of 100MHz. ............ 31

15. Figure 5.3 Simulation of the comparator model with clock rate of 10MHz. .............. 32

16. Figure 5.4 Dynamic offset test-bench block diagram. ................................................ 34

17. Figure 5.6 Phase difference between inputs for servo loop test. ................................ 37

18. Figure 5.7 Servo loop test simulation reconstructed output after 60 runs. X axis is

clock to input phase and Y axis is effective input voltage. ......................................... 38

19. Figure 5.8 Effective inputs at 1 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively. ............................................................ 40

20. Figure 5.9 Effective inputs at 10 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively. ............................................................ 41

21. Figure 5.10 Effective inputs at 25 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively. ............................................................ 42

22. Figure 5.11 Effective inputs at 50 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively. ............................................................ 43

23. Figure 5.12 Effective inputs at 80 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively. ............................................................ 44

24. Figure 5.13 Effective inputs at 100 MHz for reset tau value of 1ns and regeneration

tau values of 0.3, 0.8, 1.0 and 1.2ns respectively. ...................................................... 45

25. Figure 5.14 Effective inputs at different frequencies obtained from the servo loop test.

..................................................................................................................................... 46

26. Figure 5.15 Magnitude plot using windowing function for the behavioral model. .... 48

27. Figure 5.16 Phase plot using windowing function for the behavioral model. ............ 49

28. Figure 5.17 Magnitude and Phase plots using windowing function for the

mathematical model. ................................................................................................... 50

xi

1

Chapter1

INTRODUCTION

1.1 Motivation

Comparators are used in analog-to-digital converters (ADCs), data transmission

applications, switching power regulators and many other applications [1]. They are

critical components in analog-to-digital converters. Regenerative comparators in

particular are important for many high-speed applications, especially Flash ADCs, where

their sampling speed and comparison time are key metrics. In many of these systems it

would also be advantageous to simulate an analog system at higher levels of abstraction

to understand the different realizations before undertaking the final IC design. Spice is a

common computer-aided design tool used to simulate analog or RF circuits. There are

three potential drawbacks of using spice in a mixed-signal application. First, a detailed

circuit simulation is possible only after the entire circuit is specified. Second, it takes a

longer time to simulate, if the circuit gets complex. The last one being, spice requires

files specific to the technology being used to fabricate the circuitry that contain very

specific information about device behavior.

simulation requires detailed information that may not be available in the early stages of

the design. Verilog-AMS can overcome these problems [2] and provide better design

reuse capabilities over other modeling languages.

2

The usage of behavioral modeling for mixed-signal circuit designs has been a topic of

research interest [4, 5] because complete transistor-level simulations are often not

practical due to the enormous simulation time that would be required [6]. Usage of

behavioral modeling lets designers easily explore different system-level architectures at

the early design stages and thereby rapidly perform changes to the actual circuit designs.

Hence the design of behavioral models reduces the time to market and helps to ensure

that the design is likely to perform as desired on the first silicon produced.

1.2 Regenerative Comparators

A conceptual block diagram of a clocked comparator is shown in Figure 1.1. A change in

the clock state changes the first stage from a stable reset state to an unstable regenerative

stage [7]. Hence the clock edge corresponding to the start of the regenerative state

initiates the comparison. The digital output is updated and latched when the first stage

output reaches a sufficient level to activate R-S latch. The output remains latched until

the next comparison is made. If (VP VN) >0, the output is high or a logical 1 and if

(VP VN) < 0, the output is low or logical 0.

Regenerative comparators use positive feedback to accomplish the comparison of two

signals. The regenerative comparator is also called the latch because it is bi-stable. The

simplest form of latch consists of a cross-coupled MOSFETS with positive feedback, as

will be shown in Section 1.3. The operation of latch can be broken down to two modes.

The first mode disables the positive feedback and applies the input signals to the drains of

3

cross-coupled MOS devices. The second mode enables the positive feedback and

depending on the relative values of inputs, one of the outputs will go high and the other

will go low. A two-state clock is used to enable or disable the positive feedback. A

second clock phase may be used [7] to control the connection of subsequent stages. The

time domain response characteristics of the latch are important to understand the

operating speed of the comparator.

VN

VP

1.3 A High-speed CMOS Comparator

A high-speed CMOS comparator [7] is shown in Figure 1.2. The comparator consists of

three blocks, an input pre-amplifier stage, a regenerative latch stage and SR latch. The

architecture uses two non overlapping clocks 1 and 2 for the reset and regenerative

mode. During the reset mode, when 2 is high, the transistor M12 is on and the nodes a

and b are connected together by a positive resistance, of M12. During the regeneration

mode, after falling edge of 2, each output a and b nodes is pulled up to the positive

supply or down towards the ground as the small difference established in reset mode

4

regenerates to a full scale voltage. At the end of the regeneration process the SR latch is

driven to fully complementary digital outputs based on the regenerative outputs, and

remains in that state during the subsequent reset mode.

Figure 1.2 Schematic of a high-speed CMOS Comparator [7]. The SR Latch is the

circuitry on the right with outputs labeled Q and Q-bar.

1.4 Project Objective

The objective of this project is to develop a behavioral model for the regenerative

comparator using Verilog-AMS. A model for the comparator will be developed and

discussed, and its functionality is verified using the time-window function as presented

by Matthews [3]. The implications of the time-windowing function in the frequency

domain will be discussed. The model will be developed in Verilog-AMS using a

5

difference mode half-circuit model of regenerative comparator. The dynamic offset test

bench [12] will be used to characterize the dynamic offset of the comparator model. The

resulting offsets will be compared to an analytical model as a way to verify the

performance of the comparator model. Mentor Graphics tools will be utilized to

simulate the model.

1.5 Report Organization

The project report is organized as follows: A brief introduction to Verilog-AMS

modeling, followed by the detailed working of a Regenerative Comparator, there upon

create a Verilog-AMS model for the regenerative comparator, and finally introducing the

reader to Dynamic Offset Test Bench (DOTB) with simulations results using the DOTB

and interpretation of simulation results.

6

Chapter 2

VERILOG-AMS MODELING

2.1 Introduction

Analog behavioral modeling deals with creating and simulating models based on a

desired external circuit behavior. Models can be as complex as necessary to provide the

designer with the necessary information on which to base architectural and circuit-level

design decisions. Before starting to write a behavioral model, it is important to decide

which parameters to model so that the block is not too complicated and yet is useful to

evaluate the design tradeoffs. One of the biggest advantages of using modeling is the

simulation speed gained by removing transistor-level circuit blocks that are slow to

simulate and replacing them with behavioral models that are simpler. Verilog-AMS is the

upcoming modeling language for analog and mixed-signal system in this front. AMS

stand for Analog and Mixed Signal. Verilog-AMS is the extension of two languages,

Verilog-HDL and Verilog-A. It combines the capability of these two languages and adds

additional capability to allow the description of mixed-signal components. Hence its a

true mixed-signal language, interacting with the analog and digital sections by an

Application Program Interface (API) between the analog and digital simulators [9].

Verilog-AMS substantially provides strong event-driven constructs and features to create

behavioral models for mixed-signal blocks. This is very important, because most of the

analog and mixed-signal models used in high level simulations are naturally written using

7

event-driven constructs. Unlike the Verilog digital language, the Verilog-AMS language

cannot be used for synthesize analog blocks and will predominantly be used for modeling

and verification only.

2.2 Language Basics

It is important to understand some of the Verilog-AMS language basics before

understanding the modeling features. Verilog-AMS has ability to model a variety of

disciplines, the most common of which are electrical, magnetic, thermal, kinetic and

rotational [10]. Integrated circuit modeling primarily uses electrical discipline, which is

expressed as voltages and currents. The disciplines are defined in a file called

disciplines.vams which is included during simulation. Apart from the disciplines, there

are three basic modeling styles: Conservative, Signal-Flow and Event. Conservative

modeling uses both voltage and current to model a system. The Signal-Flow modeling

utilizes only voltage (potential) to model systems, typically for high-level modeling

where there is no need to express the functionality using current. The third style is Event

based modeling, which only evaluates based on events. Verilog-AMS allows any

combination of these modeling styles. For this project, we will be utilizing a combination

of Conservative and Event modeling style.

The syntax of the model file starts with a module declaration with a module name and pin

names. Parameter declarations follow, which can be passed from module to module

without editing the model file. A branch statement can be used to provide a name to each

8

branch where components share the same nodes. The analog begin line is where the

analog behavior begins. This is the section where the voltages and currents from outside

pins are sensed, checked for signal crossings, mathematically conditioned, then pushed

out of the circuit or stored in a file. The Verilog-AMS simulator utilizes a continuoustime kernel to evaluate the analog signals. Practically, this means that every analog signal

in the analog begin block is executed at every time-step of the simulator, and stops the

simulation time until the execution of the step is completed. This limits the language

from the usage of delay and wait statements. The event statements, defined by using

@, have been modified to remove any blocking compared to Verilog-D HDL event

statement.

2.3 Model Descriptions

The analog behavioral descriptions are mathematical mappings which relate the input

signals of the module to the output signals in terms of large-signal, time domain or

frequency domain behavioral descriptions. These descriptions use the contribution

operator <+ to assign values to analog signals [9, 10]. It is important to note that the

contribution operator is a concise description of the behavior of the element in terms of

its terminal voltages and currents. This simple way of representing the behavior of a nonlinear complex system, is shown for a diode in Figure 2.1.

9

The behavior of the diode can be defined in the Verilog-AMS language as shown in

Equation (1), where $vt() is the Verilog-AMS system task that returns the thermal

voltage.

1, 2

exp

1.0

1, 2

exp

1, 2 /$

1.0 ;

(1)

This project also required the development of a test-bench, also using Verilog-AMS

components to test the comparator behavioral model. The basic components required to

develop any such test-bench are the stimulus generator, the design under test, and the

output evaluator. The stimulus generators consist of signal generators, voltage sources,

currents sources, resistors and capacitors. The design under test would be the regenerative

comparator. The output evaluator would be a model that extracts the needed information

from the output node of the design under test and make appropriate changes to the input

or flag the user about the output generated. The functionality and purpose of the specific

test-bench for this project is further explained in Chapter 5. The design of various blocks

10

that are used in the test-bench, excluding the design under test, will be outlined in the

following sections.

2.4.1 Stimulus Generator

The stimulus is merely a variable dependent on time, frequency or some other domain

depending on the type of design under test being tested. Verilog-AMS stimuli are always

a function of time because the Verilog-AMS compiler divides the signal constructed in

time steps. The stimulus generators used for this project were a sine wave generator and a

clock signal generator. The sine wave generator uses the simple sine wave equation

shown in Equation (2).

(2)

passed as voltages or currents to variables that are declared as type electrical. Hence, the

Verilog-AMS code for the sine wave generator would look as shown in Equation (3). The

equation has variables: ampl, freq, and phase. The equation also has `M_TWO_PI

which is a constant value defined with a value equivalent to 2*, and $abstime is a

simulator internal task to define the current simulation time.

,

sin ` _

(3)

11

The clock generator for the test-bench uses a Verilog-D code to generate an always

running clock with a parameter value to change the frequency of the clock. Verilog-AMS

has several math functions that can be used to easily implement the stimuli. The list of

these math functions are presented in APPENDIX B.

2.4.2 Output Evaluator

The output evaluator monitors the input and output of the device under test and modifies

the input to the device under test when put under a closed loop. The evaluator can also

just function as an output information storing point. The output evaluator in the project is

a combination of integrator and difference circuit, further discussed in Chapter 5.

2.5 Analog Modeling Development

The process of developing a Verilog-AMS behavioral modeling requires a good

consideration of how the analog simulator will interpret the model and intuitive

understanding of the model. The analog simulators essentially use Newton-Raphson

method to solve for non-linear electrical components. If the equations used in the model

are not continuous, the simulator may not converge on to a solution. These discontinuities

should be anticipated and avoided to minimize non-convergence. When modeling an

ideal discontinuity, it is easy to block the regions of discontinuity using the

$discontinuity() simulator function. Common desired analog effects such as continuous

and smoothly shaped signals can be achieved by carefully studying what is needed and

12

then taking a macro-model approach to creating a model [11]. Modeling can start from a

simple top-down functional model to a detailed bottom-up model that closely resembles

the transistor circuit.

It is also important to consider the limit of simulator time-step and frequency where there

are fast transitions (<1pS), or high pole frequencies (>100 GHz). It is possible that just

one circuit block with a high frequency oscillation can have a dramatic impact of slowing

down the complete simulation. The model should be carefully analyzed and the time-step

should be controlled for each block using the $bound_step() simulator function.

Threshold detection and time window controls help improving the wave-shaping

accuracy. The above said are some of the specifics which caused some trouble in the

initial stages of the project.

Adding common analog effects like input offsets, delay, rise time, fall time, slew rate,

small-signal frequency response, input and output impedance, and signal clipping can

help fine-tune to track the output response of the real circuit to that of the model. In

addition effects such as Noise, PSRR, Temperature and Process Variation can greatly

help the model in various stages during the design phase. But, with complexity, there are

simulation time and other tradeoffs. These complexities are not present in this project.

13

Chapter 3

COMPARATORS

3.1 Comparators

Comparators essentially compare two analog input voltages, and output a single digital

bit that is high or low depending on the relative values of the two input voltages. They

can be classified into two major groups, clocked comparators and continuoustime

comparators. Continuous-time comparators have no clock input and are essentially high

gain differential amplifiers. A clocked comparator, often regenerative in nature, is often

used in high-speed data conversion systems. The clock edge corresponding to the start of

regeneration is considered to be effectively the time at which the comparator samples the

input. It is important to understand, however, that pre- and post-clock inputs do have

some effect on the comparators output. Rather than sampling at an instant, the

comparator is influenced by the input signal during a time window. The comparators time

windowing function is determined by its regeneration time constant and its reset time

constant [3].

3.2 Linear Model

A Schematic of the first stage of a typical regenerative comparator is shown in Figure

3.1. The MOS latch is composed of n-channel devices M2 and M4, and an n-channel

switch M3, for resetting, and a source-coupled pair M5 and M6. The operation of the

14

regenerative comparator is divided into the reset phase and the regeneration phase. In

both clock phases, the transistor pair M2-M4 causes a negative resistance from VD1 to

ground and VD2 to ground. Equivalently, this can be expressed as a negative resistance

between nodes VD1 and VD2 [3]. In reset phase, the CLK signal is held high which

connects the nodes VD1 and VD2 through a low-resistance path (M3) and results in a net

positive resistance between the nodes VD1 and VD2. In the regeneration phase, the CLK

signal is held low which leaves only a negative resistance between nodes VD1 and VD2.

As a result, any difference in voltage between the nodes VD1 and VD2 at the start of

regeneration will be exponentially amplified causing one of these nodes to go high and

other to go low.

The input applied to a source-coupled pair M5-M6 controls the balance of signal currents

going to the cross-coupled pair. The MOS devices M4 and M2 can be represented using

15

two voltage-controlled current sources as in Figure 3.2. The parasitic capacitance at each

node VD1 and VD2 is shown as (CP). The MOS device M3 is used to reset the

comparator using the CLK signal. When the CLK signal is high, the MOS device M3 acts

as a resistor between the nodes VD1 and VD2 with a resistance of 2RRST. In the

difference-mode half circuit, this will result in a resistance of RRST from node VD1 to

ground and from node VD2 to ground. The reset resistance is very high during the

regeneration phase and relatively low during the reset phase. Due to the positive feedback

from the cross-coupled pair M2-M4, a negative resistance RRGN seen from node VD1 to

ground and from node VD2 to ground (some authors [3] define this resistance from node

VD1 to node VD2). Hence during the reset phase the resistance to ground from each side

is (RRST|| RRGN) and during the regeneration phase the resistance is simply RRGN.

The mathematical analysis of the comparator model will be done, in section 3.3, using a

difference-mode half-circuit as the cross-coupled pair circuit is symmetric.

VD1

CP

VD 2

g m 4VD1

g m 2VD 2

CP

Figure 3.2 Two cross-coupled current sources represent the cross-coupled latch pair.

16

3.3 MathematicalModel

In order to validate the Verilog-AMS regenerative comparator model the dynamic

response of the model needs to be compared with that of an analytical model. The

dynamic response of an analytical model is pretty much its response to time-varying

inputs. The results of the comparison depend on the analog inputs a little before and a

little after the clock edge that starts the comparison. The analytical model of the practical

comparator can be modeled using an idealized comparator, with ideal sampling accuracy,

preceded by a time-window function [3]. Figure 3.3 shows the block diagram of the

model used for a practical comparator. The time window function has an impulse

response of

amplifies the sampled value to a full scale output. As the model uses an idealized

comparator and slicer, the model lacks the time delays for the outputs to regenerate to

full-scale values, compared to practical comparators. The function

constants at the nodes VD1 and VD2, in Figure 3.1, during the reset and the regeneration

modes. The function

The response of the comparator to time-varying inputs can be analyzed using the smallsignal difference mode half circuit in Figure 3.4. The input current is represented by

The value of capacitance, parasitic capacitance of the MOS device, is Cp and resistance

17

will be R1 in reset mode and R2 in regeneration mode. The resistance has a positive value

during the reset mode, and switches to a negative values during the regeneration mode.

).

| |

and

(4)

The time constants during the reset mode will be called 1 and the time constant during

the regeneration mode will be called 2. Accordingly, 1 has a positive value and 2 has a

negative value. Assume the comparator as a linear and time-invariant system, to be in

reset mode for

instantaneously from reset to regeneration mode at time =0 [3]. The following analysis

will consider the system as two time-invariant systems, first one while <0 and second

18

one for >0. The capacitor voltage, is the only state of the system, will be kept

constant across the discontinuity at =0. The total response will be found by adding the

zero-state response and the zero-input response.

In the reset mode, <0, the comparator is a linear time-invariant system and the

voltage , voltage across the capacitor Cp, can therefore be represented as:

Where denotes convolution,

If

(5)

the impulse

response in the regeneration mode, then these can be represented as follows, where

is the unit step function:

exp

exp

, evaluate

(t)

(6)

(t)

(7)

is the natural response.

exp

(8)

19

exp

exp

(9)

Similarly, the zero-state response of the circuit for the regeneration mode can be found by

convolution of input current with the corresponding impulse response of the circuit.

Finally the zero-input and zero-state responses are added together and simplified. The

resulting expression is given by [3]:

exp

exp

exp

(10)

resulting in:

exp

The factor exp

(11)

is given by:

exp

exp

(12)

exponential saturation when building a practical model is discussed in Chapter 4.

20

The important consequence of (11) is that the practical comparator considered here can

be modeled as an idealized comparator proceeded by convolution with

noted that

. It should be

The ideal comparator acts on only the instantaneous input value at = 0. However for a

practical comparator, the comparison depends on values before = 0 and after = 0. For

such a comparator Figure 3.5 shows the graph of the function

and the

corresponding regions for the regeneration and reset. The weighted values for > 0 are

present on the left side and < 0 are present on the right side in the Figure 3.5. The

Figure 3.5 can be visualized as reverse of time windowing function used to determine the

effective input at = 0.

w(t )

t

exp

2

t

exp

1

t 0

time

w(t )

Figure 3.5 Comparator Impulse response and windowing function [3].

21

To compare the simulation results of Verilog-AMS comparator models output to that of

the mathematical model, we need to examine

Fourier transform of

leads to:

(13)

presented in [3].

(14)

If we simply add the transconductance, gm2, of the input source-coupled pair M5 and M6

then (13) can be written as in (14). This implies that the DC gain at reset is gm2 (R1- R2).

Also the implication is that the different gains in the reset mode may have an effect on

performance, so minimizing

implications and results of

and varying

. The

compare the results obtained from simulation of the Verilog-AMS comparator model in

Chapter 5.

22

Chapter 4

REGENERATIVE COMPARATOR VERILOG-AMS MODEL

4.1 Macro Model

The Regenerative comparator analyzed in the Chapter 3 is modeled using the VerilogAMS macro-model approach that will be presented in this chapter. This approach

requires the regenerative comparator to be modeled using primitive elements. The start

point to model the comparator is the difference-mode half circuit shown in Figure 3.4.

The model needs to switch from regenerative mode to reset mode at negative and positive

edges of a clock respectively. To accommodate this behavior in the model, for a

continuous operation, a switch can be used controlled by a clock input. Figure 4.1 shows

the schematic of the regenerative comparator model that will be built using VerilogAMS. The operation of this model will be analogous to the difference-mode half circuit.

When the switch, SW1, is closed the total resistance will be

when open

| |

and

The clock edge controls the switch, SW1, in the macro model circuit. The differential

input voltage that is converted to single-ended current represented by iin, is loaded by

resistance (RRST || RRGN) when the switch is closed. The resistance (RRST || RRGN) will be

coded in Verilog-AMS model as positive resistance, similar to the actual circuit behavior,

23

as explained in section 3.2. When the switch is open the resistance is just RRGN, which is

negative. The time constants for the model in Figure 4.1 are as follows:

a) when the switch is closed:

|| R

(15)

(16)

The regenerative comparator model user can set these time constant parameters along

with the parasitic capacitance to control the reset and regeneration resistances of the

model or vice-versa.

In the above model when a small positive input current iin is applied, with the switch

open, the output voltage across the capacitor increases exponentially with a time constant

of

. The problem being the absence of no limiting circuit for this exponential

24

rise in the voltage value causes the simulator to crash with a very huge negative voltage

value. Similarly when a small negative input current -iin is applied, the simulator crashes

with a huge positive value.

4.2 Voltage Limiting Diodes

The problem with the simulator crash can be solved by adding voltage limiting diodes on

either sides of the circuit. The diodes need to be ideal diodes; hence any capacitive

effective of the normal diodes must be removed from the diode models. When the voltage

at the input of the diode, Vout, is higher than VDD by Von the model limits the output to

VDD. When the voltage at the input of the diode is less than VDD a very huge OFF

resistance is used to create smoother outputs. The new circuit with the diodes is shown in

the Figure 4.2.

VDD

SW1

iin

Vout

RRST

RRGN

Cp

VSS

Figure 4.2 Regenerative comparator model with limiting diodes.

25

4.3 Voltage Controlled Current Source

The input of the regenerative comparator model is desired to have a differential voltage

input. The model converts this voltage to current by using a voltage controlled current

source (VCCS), for two main reasons: 1) This models the inputs source-coupled pair of

the actual comparator, and 2) the ideal VCCS is unilateral, so the voltage resulting from

the regeneration does not kick back into the inputs of the comparator model.

The voltage controlled current source (VCCS) block takes differential voltage as input

and current as the output. The VCCS block typically has a gain value (gm) to control the

output current with respect to input voltage. The reset gain is

||

. The

reset gain should not be so high that the comparator will activate the swing-limiting

diodes in the reset mode for normal inputs. Voltage gain of 1 or 2 is typical. Figure 4.3

cell provides a single ended current of

to the half-circuit having RRST, RRGN and CP. Where as in a physical comparator,

all the circuitry is differential and the source-coupled pair supplies currents of

and

/2

in

The input of the comparator is explicitly differential in order to offer the user the same

input connectivity as the physical comparator.

A step response of the regenerative comparator model is shown in Figure 4.4, by stepping

positive node voltage from 0v to 100mv, setting negative node voltage at 0v, time

26

constants at 1ns and 1ns and at clock frequency of 100 MHz. The output response of the

comparator model shown in Figure 4.4 points out that at the positive edge of the clock,

when the switch SW1 is open, the output starts increasing to 5.5v and at negative edge of

the clock, when the switch SW1 is closed, and the output starts resetting back to 0v. This

response continues with the changing clock until there is a change in the input. It should

be noted that the output is measured with respect to VSS.

gm

4.4 Input Signal Limiting

The input of the regenerative comparator can have huge input values swinging between

VDD and VSS. These huge input values can cause large amounts of current to flow into

the circuit. A real comparator needs a few millvolts difference at input to make a decision

and also has a source-coupled pair as the input stage which predominantly has a

limitation for the maximum sinkable current. So to limit the amount of voltage and

current that can flow into the RC circuit, an additional current swing minimizing circuit

27

and limiting circuit needs be added. To limit the current, the VCCS in Figure 4.3 is

replaced with the circuit of Figure 4.5 to make a current-limited. The VCCS gain is now

gm1 R1 gm2, and the output current limit is V1 gm2. The parameter V1 value can be set by

the user.

28

V1

iOUT

vID

gm2

g m1

R1

V1

Figure 4.5 Updated Voltage Controlled Current Source (VCCS) schematic, by adding

additional diodes and additional pull down resistance. This entire cell replaces the single

gm-cell in the Figure 4.3.

4.5 Tweaking the Model

The regenerative comparator model developed using Verilog-AMS is provided with

parameters to tweak the operation of the model. The various parameters included for the

end user to tweak the model are: 1)Reset Tau (1) 2)Regeneration Tau (2) 3)Parasitic

Capacitance (CP) 4)Reset gain of the VCCS model 5)Cut-off voltage (V1) for the input

signal limiting diode 6)Operating Voltage for the model, i.e. VDD and VSS.

The reset and regeneration time constants given calculate the ratio of the resistors. The

capacitance determines the resistance values using the time constants. Once the resistor

values are known, and a reset gain is given, the value of the

is

determined.

The Verilog-AMS code for the model can be found in APPENDIX A for further details.

29

Chapter 5

SIMULATION RESULTS

5.1 Introduction

The regenerative comparator model was developed using Verilog-AMS as explained in

the chapter 4. This chapter deals with simulation of the model with simple inputs, design

of Dynamic Offset Test Bench (DOTB) [12] and finally testing the model using the

Dynamic Offset Test Bench. The model is simulated using Mentor Graphics ADMS

tool. The outputs of the simulation are analyzed using the EZ-wave waveform viewer

tool. The design of the DOTB is done using Verilog-AMS to increase the simulation

speed.

5.2 Simulation of the Comparator Model

The regenerative comparator basically compares the inputs provided and gives the

corresponding output based on the input. If the input of the comparator is

then the output is pulled high. If the input of the comparator is

0,

0 then the

output is pulled low. The positive edge of the clock, to the comparator, starts the

comparison and negative edge of the clock reset the comparator to be used for the next

comparison. The simulation of the comparator is done by setting VDD to 5v and VSS to

-5v. This causes the output of the comparator model to swing to either VDD or VSS

values. To make the simulation inputs easier, one of the inputs of the comparator is fixed

30

to GND, i.e. 0v, and the second input is connected to a piecewise waveform generator.

The circuit schematic is shown in Figure 5.1.

Figure 5.2 shows the output response of the comparator model for various inputs. In the

Figure 5.2, when the input is below 0v, the comparator pulls the dataout node to (VDD +

Vdiode_cutoff) on the positive edge of the clock. When the input of the comparator is above

0v the comparator pulls the dataout node to (VSS Vdiode_cutoff) on the positive edge of

the clock. It should be noted that the comparator resets its output on the negative edge of

the clock. The clock rate defined for this simulation is 100MHz and Vdiode_cutoff was set to

0.6v. At lower clock rates, i.e. 10MHz, the comparator output is held to the same values

until the model detects a negative clock edge as shown in Figure 5.3. A RS latch is

attached to the output stage to above model hold the outputs to either high or low, so that

it appears as digital value for either 100 MHz or 10MHz comparator outputs.

31

Figure 5.2 Simulation of the comparator model with clock rate of 100MHz.

32

Figure 5.3 Simulation of the comparator model with clock rate of 10MHz.

33

5.3 Dynamic Offset Test Bench

Comparators used in high speed ADCs have a decision threshold ideally at zero. This

decision threshold can shift due to component mismatches and other non-ideal

conditions. The amount by which the threshold shifts is called the input offset voltage.

Simulations to determine the input offset voltage of the comparator are difficult, as the

designer must try different inputs in order to find the actual input offset voltage and can

be a time consuming process. A simulation technique presented by [12], dynamic offset

test-bench (DOTB), will be utilized to understand the DC offset and other parasitic

mismatches caused by varying the reset and regeneration tau for the comparator model.

The results from the DOTB can also be used to understand the effective sampling time

accuracy of the comparator for various time constants for the model. The technique

presented by [12] uses idealized components to test the comparator. The components for

the DOTB are created using Verilog-AMS for faster simulation. Figure 5.4 shows the

schematic of the DOTB created to test the comparator. The dynamic offset test-bench

consists of a latch circuit, an integrator, a sinusoidal wave generator and the comparator

under test. The output of the comparator model designed using Verilog-AMS swings

from VDD to VSS, i.e. 5v to -5v. These outputs have to be readjusted to be used by the

SR latch to be applicable for the DOTB. The voltage adjustor model shifts the output of

the comparator to limit between 0 to 5v. The voltage adjuster model combined with SR

latch model works similar to a normal SR latch combined to real comparator. Second

waveform in the Figure 5.5 shows the output of the integrator. The output of the

34

integrator Vout_integrator peak value depends on the integrator gain. A smaller peak-to-peak

variation in Vout_integrator leads to greater accuracy, but will also increase the simulation

time. For the DOTB simulations described below, the integrator output was about 50mV

peak-to-peak.

5.4 Servo Loop Test Using DOTB

The regenerative comparator model is tested using the servo loop test using dynamic

offset test-bench as described in [3] and [12]. A sinusoidal signal generator is used as one

of the inputs to the comparator and the other input is connected to the output of the

35

integrator. The input sine wave signal is phase shifted by an amount

= 6 relative to

input clock, as shown in Figure 5.6. The servo loop is allowed to settle, then the process

is repeated for an increased phase shift between the sine wave and the clock, for total of

60 values of . The servo loop is run for 60 incremental values of , i.e. 360 of sine

wave, for various frequencies between 1 MHz to 100 MHz to study the effective input

magnitude and phase as frequency increases.

36

37

Figure 5.6 Phase difference between inputs for servo loop test.

5.5 Simulating the design

The output of these 60 simulations is used to understand the frequency response of the

comparator and the effective sampling time-window of the comparator. It should be

observed that the ideal comparator samples the sine wave on the positive edge of the

clock for each of the 60 simulations. To understand the sampling accuracy of the

comparator we took the peak-to-peak average of the integrator output once the loop

settles, as shown in Figure 5.5. These average values from the servo loop test, for all of

the 60 runs, if reconstructed, form a single sine waveform as shown in Figure 5.7. The

reconstructed sine waveform represents the effective input of the comparator, and makes

evident the magnitude and phase shift corresponding to W(j). For different comparator

time constants, there is a different W(j).

38

Figure 5.7 Servo loop test simulation reconstructed output after 60 runs. X axis is clock

to input phase and Y axis is effective input voltage.

5.6 Automating the Simulation Environment

A major hurdle in the servo loop test is to get the average values of the integrator output

over several complete cycles after the loop has reached steady-state. The starting peak

time of the integrator output varies for different values of regeneration tau, reset tau and

clock frequencies. Also the peak value changes for every run for any given set of

regeneration tau and rest tau values. The best possible way to get the average value for

the run is by observing the SR latch outputs. Figure 5.5 waveforms show that the

integrator shifts it direction based on the SR latch output change. It can be observed that

SR latch output does not change after the first two positive edges. Starting with the third

positive edge of the SR latch output to a total of 17 edges, both positive and negative SR

latch output swing combined gives a total of 8 peak-to-peak values of the integrator,

39

which will provide the average value needed from the integrator output. This average

value represents the input sampled value of the sine wave by the comparator. These

values have to be obtained for each of the 60 runs to reconstruct the sine wave shown in

Figure 5.7. The simulation results obtained by varying the time constants for different

frequencies can be seen in Figures 5.8, 5.9, 5.10, 5.11, 5.12, 5.13. The following

automation code is used to measure the average values for various time constant corners:

.meas tran vcomp_start TRIG AT=0 TARG V(Q_out) val=2.5v cross=2

.meas tran vcomp_stop TRIG AT=0 TARG V(Q_out) val=2.5v cross=17

.meas tran vint_avg

The analysis done in chapter 3 can be used to interpret the simulation results obtained

from the DOTB for various clock frequencies. The reset tau has been kept at a constant

1.0ns for all the simulations. It can be observed that as value of regeneration tau drifts

away from the reset tau, there is a certain amount of phase shift seen in the sine wave.

Also a smaller regeneration tau increases the magnitude of the effective comparator input

at higher frequencies as seen from Equation (12). It can be observed that if the phase shift

is not well-controlled, the effective sampling time of the comparator for certain fast

changing sinusoids may be uncertain. Clearly, as stated by [3] and results from the DOTB

simulations suggest that for minimal phase shift, i.e. for a comparator to have sampling

accuracy at the zero crossing of the input, its desirable to set 2 = - 1.

40

Figure 5.8 Effective inputs at 1 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively.

41

Figure 5.9 Effective inputs at 10 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively.

42

Figure 5.10 Effective inputs at 25 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively.

43

Figure 5.11 Effective inputs at 50 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively.

44

Figure 5.12 Effective inputs at 80 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively.

45

Figure 5.13 Effective inputs at 100 MHz for reset tau value of 1ns and regeneration tau

values of 0.3, 0.8, 1.0 and 1.2ns respectively.

46

Figure 5.14 Effective inputs at different frequencies obtained from the servo loop test.

The phase shift at value 0 in Figure 5.14 has been observed to change to be from -131mV

to 49.5mv. This indicates the phase shift across the various frequencies using different

time constants. The amplitude can be seen to change from 494mv to 404mv, with input

signal amplitude of 500mv. The magnitude and phase plots of the behavioral model for

various frequencies and various 1 (reset) values, keeping 2 (regeneration) constant to a

value of -1ns, as shown in Figure 5.15 and Figure 5.16. These values appear to be

47

consistent with results obtained by [3] as shown in Figure 5.17. The results from the

graphs suggest that if the excessive phase shift is not well controlled, the effective

sampling time of the comparator for sinusoids may be uncertain. Clearly, for minimal

phase shift the option of 1 = - 2 is desirable.

The plots in the Figure 5.15 and Figure 5.16 were obtained by simulating the comparator

model at only a handful of frequencies. This resulted in the sharp kinks seen in both the

curves. The plot in Figure 5.17 was generated using MATLAB code by [3] resulting in

continuous waveforms. The plots in Figure 5.15 and Figure 5.16 shows the magnitude

and phase plots of W(j) as a function of frequency. It was been seen in Figure 5.15 that

a smaller 1 increases the magnitude of the effective comparator input at high frequencies.

Also it can be noted from Figure 5.16 that a smaller 1 increases the phase shift of the

effective comparator input at high frequencies.

48

Figure 5.15 Magnitude plot using windowing function for the behavioral model.

49

Figure 5.16 Phase plot using windowing function for the behavioral model.

50

W ( j )

10

20

30

W ( j )

Figure 5.17 Magnitude and Phase plots using windowing function for the mathematical

model.

51

Chapter 6

CONCLUSIONS

6.1 Accomplishments

This project report has detailed the development of a behavioral model for a regenerative

comparator using Verilog-AMS. The model has been parameterized to control the values

of time constants, 1 and 2, parasitic capacitance Cp and operational voltage of the

model VDD. The model has been parameterized such that it can be embedded into other

designs with minor modification to the parameter values.

The developed model has been verified for its functionality at different frequencies and

with different combinations of time constants. The testing of the model was done

utilizing the time-windowing function of the comparator. The results obtained from the

analysis of the comparator showed that the desirable minimal phase shift is obtained for

the option 1 = -2. Hence a well-controlled reset transistor in the actual design is optimal.

The project also outlined the development of Dynamic Offset Test Bench (DOTB) for

testing the comparator using Verilog-AMS with minor enhancements. The results

obtained from the DOTB matched that of the mathematical analysis results. The project

report also detailed various problems faced in the development of the model and how to

overcome such scenarios.

52

A Shell script was also developed as part of the test-bench to automate the data collection

process during the simulation. This script proved as an essential part of the simulation as

it helped to decrease the amount of time required to process the output data. The

complete code has been automated and parameterized to make the behavioral model

reusable across various designs.

6.2 Future Work

Although a behavioral model has been developed in Verilog-AMS and has been tested

using Verilog-AMS test-bench, its capabilities were not tested in a mixed circuit

simulation with other SPICE circuit simulations. Also further investigations into other

non-linear aspects of the model can be done and incorporated to get some complex

behavior of the model, like full reset functionality, spline functions based curve fitting

and adding noise models.

53

APPENDIX A

Source Code for Behavioral Model and Test Bench

// Library.va

// Various simple components used to build test-bench and DUT.

// Created by Pranav Cherupalli

`ifndef __DEFINES__

`define __DEFINES__

`include "disciplines.vams"

`include "constants.vams"

`endif

`timescale 1ns/1ps

//Capacitor Block

module cap1(p, n);

inout p, n;

electrical p, n;

parameter real c=1 from [0:inf);

analog begin

I(p,n) <+ c*ddt(V(p,n));

end

endmodule

//Simple Resistor Block

module resistor(p, n);

inout p, n;

electrical p,n;

parameter real res=1 from [0:inf);

analog begin

V(p,n) <+ res*I(p,n);

end

endmodule

54

//Clock generator Block

module clk_gen(clk);

output clk;

reg clk;

parameter real clk_period = 400;

initial begin

clk = 0;

forever clk =#(clk_period/2) ~clk;

end

endmodule

//Ideal Diode Block, changed the parameters to suite the design

module DIODEideal(p,n);

inout p,n;

electrical p,n;

parameter real Vg = 0.6;

parameter real rD = 1.0 from (1.0e-6:inf];

parameter real rDOFF = 1.0e8 from (1.0e-6:inf];

// ON resistance of diode

// OFF resistance of diode

analog begin

if (V(p,n) < Vg)

I(p,n) <+ V(p,n)/rDOFF;

else

I(p,n) <+ (V(p,n) - Vg)/rD + Vg/rDOFF;

end

endmodule

//Integrator Block designed out of the transfer function equation

module my_integrator( vout, vip, vin);

input vip, vin;

output vout;

electrical vout, vin, vip;

electrical input_vol;

parameter real RC_Val = 0.0001 exclude 0;

55

parameter real DC_Val = 0;

real Inv_RC_Val;

analog begin

@(initial_step) Inv_RC_Val = -1/RC_Val;

V(input_vol) <+ (V(vip) - V(vin));

V(vout) <+ Inv_RC_Val * idt(V(input_vol), DC_Val);

$bound_step(0.00001);

end

endmodule

//RS Latch Block to be used after the comparator.

module my_rs_latch ( Q, Qb, datain);

input datain;

output Q, Qb;

electrical datain;

electrical Q, Qb, Set, Reset;

parameter real Vth_pos = 4.6 from (-5:5);

parameter real Vth_neg = -4.6 from (-5:5);

parameter real VDD = 5 from (-10:10);

parameter real AGND = 0 from (-10:10);

parameter real SR = 1.0e12 from (0:inf);

real set;

real reset;

real q;

real qb;

real VQ;

real VQb;

analog begin

@(cross(V(datain) - Vth_pos, +1)) begin

set = 1;

reset = 0;

end

56

@(cross(V(datain) - Vth_neg, -1)) begin

set = 0;

reset = 1;

end

if(V(datain) > 4.9) begin

set = 1;

reset = 0;

end

if(V(datain) < -4.9) begin

reset = 1;

set = 0;

end

q = V(Q);

qb = V(Qb);

V(Set) <+ set;

V(Reset) <+ reset;

if(set) begin

VQ = VDD;

VQb = AGND;

end

else if (reset) begin

VQb = VDD;

VQ = AGND;

end

else begin

VQ = q;

VQb = qb;

end

V(Q) <+ slew (VQ, SR, -1*SR);

V(Qb) <+ slew (VQb, SR, -1*SR);

$bound_step(0.001/100);

end

endmodule

57

//Block to Sample the input signal on the posedge of clock

module my_sampler (clk, inpwave, outsignal);

input clk, inpwave;

output outsignal;

electrical inpwave, outsignal;

real outVal;

wire clk;

analog begin

@(initial_step) begin

outVal = 0;

end

@(posedge clk) begin

outVal = V(inpwave);

//$display("Outval is %f", outVal);

end

V(outsignal) <+ outVal;

end

endmodule

//SineWave generator Block

module my_sine(outp);

output outp;

electrical outp,gnd;

ground gnd;

parameter real freq = 10e3 exclude 0;

parameter real phase = 0;

parameter real amplitude = 1.0 exclude 0;

analog begin

V(outp,gnd) <+ amplitude*sin((`M_TWO_PI*freq*$abstime) + phase);

end

endmodule

58

//PWL block in Verilog_AMS for different time steps and voltages

module my_vsrc (outp);

output outp;

electrical outp;

//Initially the parameters are fixed to 0v, so that there is no Signal

parameter real t0 = 0n from [0:inf);

parameter real Vt0 = 0.000 from (-5.1:5.1);

parameter real t1 = 1n from [0:inf);

parameter real Vt1 = Vt0 from (-5.1:5.1);

parameter real t2 = 2n from [0:inf);

parameter real Vt2 = Vt1 from (-5.1:5.1);

parameter real t3 = 3n from [0:inf);

parameter real Vt3 = Vt2 from (-5.1:5.1);

parameter real t4 = 4n from [0:inf);

parameter real Vt4 = Vt3 from (-5.1:5.1);

parameter real t5 = 5n from [0:inf);

parameter real Vt5 = Vt4 from (-5.1:5.1);

parameter real t6 = 6n from [0:inf);

parameter real Vt6 = Vt5 from (-5.1:5.1);

parameter real t7 = 7n from [0:inf);

parameter real Vt7 = Vt6 from (-5.1:5.1);

real outp_volt;

analog begin

@(timer(t0)) outp_volt = Vt0;

@(timer(t1)) outp_volt = Vt1;

@(timer(t2)) outp_volt = Vt2;

@(timer(t3)) outp_volt = Vt3;

@(timer(t4)) outp_volt = Vt4;

@(timer(t5)) outp_volt = Vt5;

@(timer(t6)) outp_volt = Vt6;

@(timer(t7)) outp_volt = Vt7;

V(outp) <+ transition(outp_volt,0,0,0);

end

endmodule

59

//This block generates difference signal on the output

module signal(diffinp, diffinn, outp);

inout diffinp, diffinn;

output outp;

electrical diffinp, diffinn;

electrical outp;

real val_diffp;

real val_diffn;

analog begin

val_diffp = V(diffinp);

val_diffn = V(diffinn);

V(outp) <+ transition((val_diffp - val_diffn),0,0,0);

end

endmodule

//Ideal Switch block, taken from Ken Kundurts book

module my_switch (p,n, pcntrl, ncntrl);

input pcntrl, ncntrl;

output p, n;

electrical p, n, pcntrl, ncntrl;

parameter real thresh = 0;

analog begin

@(cross(V(pcntrl, ncntrl) - thresh, 0))

;

if(V(pcntrl, ncntrl) > thresh)

V(p,n) <+ 0;

else

I(p,n) <+ 0;

end

endmodule

60

//Ideal Voltage Controlled Current Source

module vccs (p,n,ps,ns);

parameter real reset_gain = 1;

output p,n;

input ps,ns;

electrical p,n,ps,ns;

analog

I(p,n) <+ reset_gain*V(ps,ns);

endmodule

//Ideal Voltage Controlled Voltage Source

module vcvs (p, n, ps, ns);

input ps, ns;

output p, n;

electrical p, n, ps, ns;

parameter real gain = 1;

analog

V(p,n) <+ gain*V(ps,ns);

endmodule

61

// Regenerative Comparator Block (RCbloc.va)

// Uses library.va components

//Created by Pranav Cherupalli

`include "disciplines.vams"

`include "constants.vams"

module rcblock ( datain, clk, dataout, gnd);

input clk;

input datain;

output dataout;

electrical datain, dataout, gnd;

electrical datain1;

ground gnd;

wire clk;

electrical VDD_volt; //For Diode

electrical VSS_volt; //For Diode

electrical midpoint;

parameter real reset_tau = 1e-8 from (-inf:inf);

parameter real regen_tau = -1e-8 from (-inf:inf);

parameter real reset_gain1 = 0.0001 from (0:inf);

parameter real reset_gain2 = 0.0001 from (0:inf);

parameter real resistor1 = 1000 exclude 0;

parameter real cap = 0.1n from (-inf:inf);

parameter real VDD = 5 from (-50:50);

parameter real VSS = -5 from (-50:50);

parameter real gain2 = (reset_gain2 * cap) / (reset_tau * reset_gain1);

parameter real gain1 = 1; //* resistor1/10;

//Internal real params

real negRes;

real posRes;

real changeResis;

real mid_val;

real VL;

//Voltage controlled current source 1

//vccs #(.reset_gain(gain1)) CS1(.n(datain1), .p(gnd), .ps(datain), .ns(gnd));

//Resistor to ground for the first gm stage.

62

resistor #(.res(resistor1)) R1(.p(datain1), .n(datain));

//clamper to limit the dataout1 value

DIODEideal #(.Vg(0.1)) DA1(datain1, gnd);

DIODEideal #(.Vg(0.1)) DA2(gnd, datain1);

//Clamper Diodes

DIODEideal #(.Vg(0.0)) D1(dataout, VDD_volt);

DIODEideal #(.Vg(0.0)) D3(VSS_volt, dataout);

//Voltage Controller Current Source 2

vccs #(.reset_gain(gain2)) CS2(.p(dataout), .n(gnd), .ps(datain1), .ns(gnd));

//Simple Capacitor

cap1 #(.c(cap)) C1(.p(dataout),.n(gnd));

analog begin

@(initial_step) begin

negRes = regen_tau/cap;

posRes = ((negRes*reset_tau)/((negRes*cap)-reset_tau));

$display("Values

of

Reset_tau=%14.12f,

Regen_tau=%14.12f,

Reset_gain=%f",reset_tau, regen_tau, reset_gain2);

$display("Value of PosRes=%f, negRes=%f", posRes, negRes);

changeResis = posRes;

end

//additional code to hold the Diode value to constant.

V(VDD_volt) <+ (VDD);

V(VSS_volt) <+ (VSS);

@(posedge clk) begin

changeResis = negRes;

end

@(negedge clk) begin

changeResis = 1/((1/posRes)+(1/negRes));

end

V(dataout, gnd) <+ (changeResis) * I(dataout, gnd);

end

endmodule

63

// Testbench for the comparator (tb_comp.va)

// Created by Pranav Cherupalli

`ifndef __DEFINES__

`define __DEFINES__

`include "discipline.vams"

`include "constants.h"

`endif

`include "library.va"

`include "rcblock.va"

`timescale 1ns/1ps

module tb_comp;

electrical step_in;

electrical dataout;

electrical gnd;

electrical posnode, negnode;

electrical Q_out, Qb_out;

electrical Vout_intgrtr;

electrical wave;

electrical VIN;

ground gnd;

wire clk;

//frequency relative to clkCycle

parameter real sineWaveAmp = $param("sinewaveampl");

parameter real sineWaveFreq = $param("sinewavefreq");

parameter real sineWavePhase = $param("sinewavephase"); //360= 2*pi, 6= 0.1466

parameter real clkCycle = $param("clockcycle");

parameter real posThresh = $param("posThresh");

parameter real negThresh = $param("negThresh");

parameter real RCVal = $param("Intgrtr_RCval");

parameter real initialDCVal = 0;

//parameters of RC block

parameter real reset_tau = $param("reset_tau");

parameter real regen_tau = $param("regen_tau");

parameter real reset_gain1 = $param("reset_gain1");

parameter real reset_gain2 = $param("reset_gain2");

parameter real cap = $param("capacitance");

64

parameter real VDD = 5 from (-50:50);

parameter real VSS = -5 from (-50:50);

//Sinusoidal Input source

my_sine #(.freq(sineWaveFreq), .phase(sineWavePhase), .amplitude(sineWaveAmp))

vsine(.outp(wave));

//Signal Difference ckt with clock frequency as parameter

signal sig1 (.diffinp(wave), .diffinn(Vout_intgrtr),.outp(step_in));

//Clock Generator Block

clk_gen #(.clk_period(clkCycle)) clkgen (.clk(clk));

//Comparator block Implementation

rcblock #(.reset_tau(reset_tau), .regen_tau(regen_tau),

.reset_gain1(reset_gain1),.reset_gain2 (reset_gain2), .cap(cap), .VDD(VDD),

.VSS(VSS)) comp1 (.datain(step_in), .clk(clk), .dataout(dataout), .gnd(gnd));

// Modified RS Latch

my_rs_latch #(.Vth_pos(posThresh),.Vth_neg(negThresh)) rs_l1 (.Q(Q_out),

.Qb(Qb_out), .datain(dataout));

//Integrator Block

my_integrator #(.RC_Val(RCVal),.DC_Val(initialDCVal)) testIntg (.vout

(Vout_intgrtr), .vip(Q_out), .vin(Qb_out));

//Dummy Test logic here

analog begin

V(VIN) <+ 0.1;

end

endmodule

65

* The Following code is ELDO Simulator Script.

* It does not consist of any Verilog-AMS code.

***************************************************

* Created by Pranav Cherupalli

* Updated Date Feb 21st, 2010, 12:59 AM

***************************************************

**********************************

*Setup Conditions for simulator

**********************************

.width out=120

!

.option ingold=2

!

.option numdgt=10 !

.option notrclib

!

.option noascii

!

.option nowarn=100 !

.option probe

!

.option captab

!

.option tuning=vhigh !

.option itl1=1000

!

.option itl6=1000

!

.option hmin=1e-10

.option trap

.option eps=5e-5

.option aex

!

Set output format for numbers to Spice 2G6 default

Set number of digits for .op and .meas numerical outputs

Suppress printing of models/subckts from .lib in .chi file

Suppress printing of print/plot outputs in .chi file

Suppress printing of warning 100 in .chi file

Add only requested outputs to .wdb file (graphical output)

Print capacitance table in .chi file

Set simulation to high accuracy

Set limit for max number of DC iterations (default=100)

Transient timestep contol option (see Eldo_ur.pdf)

**********************************

* Measurement commands

**********************************

.meas tran vcomp_start TRIG AT=0 TARG V(Q_out) val=2.5v cross=2

.meas tran vcomp_stop TRIG AT=0 TARG V(Q_out) val=2.5v cross=17

.meas tran vint_avg AVG v(Vout_intgrtr) FROM=vcomp_start TO=vcomp_stop

*********************************

* Simulation specific parameters

*********************************

.param sinewaveampl=(0.5)

.param sinewavephase=(0.0)

.param sinewavefreq=(100000000) ! 100Mhz

.param clockcycle=10 ! 10 ns

66

.param posThresh=4.5

.param negThresh=-4.5

.param Intgrtr_RCval=2.7e-5

*********************************

* RC Model specific parameters

*********************************

.param reset_tau = 1e-9;

.param regen_tau = -1e-9;

.param reset_gain1 = 1.0;

.param reset_gain2 = 1.0;

.param capacitance = 0.1n;

.op

.tran 0.01n 50.0us

**********************************

.alter

.param sinewavephase=((0.104720))

.alter

.param sinewavephase=((0.209440))

.alter

.param sinewavephase=((0.314159))

.alter

.param sinewavephase=((0.418879))

.alter

.param sinewavephase=((0.523599))

.alter

.param sinewavephase=((0.628319))

.alter

.param sinewavephase=((0.733038))

.alter

.param sinewavephase=((0.837758))

.alter

.param sinewavephase=((0.942478))

.alter

.param sinewavephase=((1.047198))

.alter

.param sinewavephase=((1.151917))

.alter

.param sinewavephase=((1.256637))

.alter

.param sinewavephase=((1.361357))

.alter

67

.param sinewavephase=((1.466077))

.alter

.param sinewavephase=((1.570796))

.alter

.param sinewavephase=((1.675516))

.alter

.param sinewavephase=((1.780236))

.alter

.param sinewavephase=((1.884956))

.alter

.param sinewavephase=((1.989675))

.alter

.param sinewavephase=((2.094395))

.alter

.param sinewavephase=((2.199115))

.alter

.param sinewavephase=((2.303835))

.alter

.param sinewavephase=((2.408555))

.alter

.param sinewavephase=((2.513274))

.alter

.param sinewavephase=((2.617994))

.alter

.param sinewavephase=((2.722714))

.alter

.param sinewavephase=((2.827434))

.alter

.param sinewavephase=((2.932153))

.alter

.param sinewavephase=((3.036873))

.alter

.param sinewavephase=((3.141593))

.alter

.param sinewavephase=((3.246313))

.alter

.param sinewavephase=((3.351032))

.alter

.param sinewavephase=((3.455752))

.alter

.param sinewavephase=((3.560472))

.alter

68

.param sinewavephase=((3.665192))

.alter

.param sinewavephase=((3.769911))

.alter

.param sinewavephase=((3.874631))

.alter

.param sinewavephase=((3.979351))

.alter

.param sinewavephase=((4.084071))

.alter

.param sinewavephase=((4.188790))

.alter

.param sinewavephase=((4.293510))

.alter

.param sinewavephase=((4.398230))

.alter

.param sinewavephase=((4.502950))

.alter

.param sinewavephase=((4.607669))

.alter

.param sinewavephase=((4.712389))

.alter

.param sinewavephase=((4.817109))

.alter

.param sinewavephase=((4.921829))

.alter

.param sinewavephase=((5.026548))

.alter

.param sinewavephase=((5.131268))

.alter

.param sinewavephase=((5.235988))

.alter

.param sinewavephase=((5.340708))

.alter

.param sinewavephase=((5.445427))

.alter

.param sinewavephase=((5.550147))

.alter

.param sinewavephase=((5.654867))

.alter

.param sinewavephase=((5.759587))

.alter

69

.param sinewavephase=((5.864306))

.alter

.param sinewavephase=((5.969026))

.alter

.param sinewavephase=((6.073746))

.alter

.param sinewavephase=((6.178466))

**********************************

.end

70

APPENDIX B

Verilog-AMS Functions and Operators

B.1 Mathematical Functions

Table 1 Verilog-AMS Built-in Mathematical Functions

Function

Description

ln(x)

Natural log

x>0

log(x)

Decimal log

x>0

exp(x)

Exponential

x<80

sqrt(x)

Square root

x>=0

min(x,y)

Minimum

All x, all y

max(x,y)

Maximum

All x, all y

abs(x)

Absolute

All x

floor(x)

Floor

All x

ceil(x)

Ceiling

All x

sin(x)

Sine

All x

Domain

71

cos(x)

Cosine(x)

All x

tan(x)

Tangent

x !=n(/2), n is odd

asin(x)

Arc-sine

-1 <=x<=1

acons(x)

Arc-cosine

-1 <=x<=1

atan(x)

Arc-tangent

All x

atan2(x,y)

Arc-tangent x/y

All x, y, except 0

hypot(x)

Sqrt(x2+y2)

All x, y

sinh(x)

Hyperbolic sine

All x

cosh(x)

Hyperbolic cosine

All x

tanh(x)

Hyperbolic tan

All x

asinh(x)

a-hyperbolic sin

All x

acosh(x)

a-hperbolic cos

x >= 1

atanh(x)

a-hperbolic tan

-1<=x<=1

pow(x,y)

Power xy

72

Table 2 Verilog-AMS Mathematical Operators

Operator

Description

+ , - , *, /, %

Equality operators.

(?:)

ternary operator

>>, <<

Shift operators

Table 3 Verilog-AMS Built-in Analog Operators.

Analog Operator

ddt(x)

Description

Time Derivative of its argument.

Usage y = ddt(x);

idt(x)

Usage y = idt(x) + c;

modulus operation.

Its a periodic Integration.

Time delay operator.

Linear time delay for continuous waveforms

Used for transmission line modeling.

Last zero crossing.

Returns time of last crossing of expr.

idtmod(x)

last_crossing(expr)

delay(expr, dt)

Filters piecewise constant waveforms to

piecewise linear.

Adds delay, rise time and fall time.

73

laplace_zd(expr, num, dnom)

laplace_np(expr, num, dnom)

laplace_nd(expr, num, dnom)

zi_zp(expr, num, dnom, T, trf, t0)

zi_zd(expr, num, dnom, T, trf, t0)

zi_np(expr, num, dnom, T, trf, t0)

zi_nd(expr, num, dnom, T, trf, t0)

Slew Filter.

Used for smoothly varying signals.

Bounds the signal rate-of-change to the output.

Laplace filter

Laplace analog operators provide different

variants on specifying the filter coefficients to

work in frequency domain.

Use fixed poles and zeros.

Z transform operator.

These filters implement linear discrete-time

filters using zeros and poles.

T specifies the period of the filter.

trf and t0 are optional transition times.

The analog behavior of the module can be controlled using analog events. These events

differ from the standard control flow constructs like if-else or case. Table 4 list the most

common event commands that are be used. Event is called using the @ (event) syntax.

Table 4 Common Verilog-AMS Analog Event Types.

cross (expr, dir)

above(expr)

Description

Used for threshold and signal crossing.

Signal low to high crossing.

initial_step

final_step

74

REFERENCES

1.

Ken Martin, David Johns, Analog Integrated Circuit Design, John Wiley &

sons, 1997.

2.

Cheng, K., and JOU, K. F., 2.4GHz CMOS VCO Design with Verilog-AMS,

ICM 2003, pp 98-101, December 2003.

3.

comparators, IEEE International Midwest symposium on Circuits and systems,

August 2008, pp. 638-641, vol. 1.

4.

Design Methods for Analog and Mixed-Signal Applications, IEEE Proc. 2002

Design, Automation and Test, Europe, Conference and Exhibition.

5.

Guide community, www.designers-guide.org, 2003.

6.

and Analyzing Multi-Giga Hertz Serial Links, DesignCon 2005.

7.

8-b resolution," IEEE Journal of Solid-State Circuits, vol. 27, pp. 208 - 211,

February 1992.

8.

OXFORD, Second Edition, 2004.

75

9.

Academic publishers, 2004.

10.

Dan FitzPatrick, Ira Miller, Analog Behavioral Modeling with the Verilog-A

Language, Kluwer Academic Publishers, Boston, Massachusetts. 1998.

11.

12.

Determining DC and Dynamic Offsets in Comparators, IEEE International

Midwest Symposium on Circuits and Systems, 2005, pp. 1815-1818, vol. 2.

13.

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