10lec10 Review

EE 3610: Digital Systems
Midterm Exam
Review
EE 3610 Digital Systems
Suketu Naik
Combinational
Logic
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Low Level Modules: Gates
Functions: done in class
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Boolean Algebra
Combinational Logic (text, p4):

Unity Operators: A + 0 = A
A1=A
Complement:
AA=0
A+A= 1
Commutativity: A + B = B + A
AB=BA
Associativity: A + (B + C)= (A + B) + C
A (BC) = (AB) C
Distributed Law: A (B + C) = AB + AC
A + BC= (A + B) (A + C)
Important:
A+A=A
Note:
A + B = AB + AB
DeMorgans:
AA =A
(A + B + ) = AB
A B +A B=A
(ABC) = A+B+
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Types of Digital System
Full Adder (done in class)

X
Y
Co
ADDER
Ci
Truth Table
Outputs
Simplification
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Karnough Maps
Simplification can be difficult; use K-Map
Full Adder using K-Map

More Examples with K-Maps
Variable Entered Map (for large number of
variables)
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Implementation of Logic Gates
Logic Devices: NAND, NOR
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Implementation of Logic Gates
NAND Gate
A
Vout
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Sequential
Logic
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Introduction
10
Combinational Logic
Mathematical function: single input has a single and unique output
Same inputs produce same outputs
Sequential Logic
Output depends on current and past inputs
Same inputs can yield different outputs, depending on memory
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SR Latch (Set-Reset Latch)

With NOR Gates
SR Circuit
SR Truth Table
11
NOR Truth Table
1) Active HIGH
2) S=1, R=1 is metastable
(invalid)
Red =1
Black=0
3) S=0, R=0: latch, no

change
4) Asynchronous
device
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Master-Slave D Latch: D Flip-Flop (FF)

Master and Slave D Latches
(Qm)
12
D flip-flop symbol
(Qs)
What happens to Qs (output

of the FF) in relation to D
(input to the FF)?
Clock
Timing Diagram
While Clock (Enable) stays Clock
high, Qs will follow D after
D
some delay; while clock stays
low, Qs will remember its
Qm
previous state and will not
respond to any changes in D Qs
until the clock goes high again
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Essence of D Flip Flop
13
D Flip-Flop(Synchronous 1-bit memory)
Timing Diagram
Note: propagation delay between D and Q is omitted

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JK Flip-Flop
JK flip-flop circuit
JK flip-flop symbol
J
14
CLK
Q
Y
Clock
Truth Table
Timing Diagram
If J and K are different, Q takes the value of J at the next clk edge
If J and K are both low, no change occurs
If J and K are both high, the output will toggle
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T Flip-Flop
T flip-flop symbol
1
J
K
15
Timing Diagram
Q
Q
T (CLK)
T Flip Flop: Tie J and K to high

Output will toggle at half the frequency of the clock at the
positive edge
Good for binary counters and frequency dividers
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4-bit Register
16
Serial In Parallel Out (SIPO) 4 bit register
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Counters
17
Binary 4-bit
Synchronous Up
Counter
Output in
synchronization with
the clock
Individual output bits
change state at exactly
the same time in
response to the
common clock signal:
no ripple effect and no
propagation delay.
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Multiplexer (MUX)
18
4-to-1 Multiplexer
Select input to output based on S1S0

3 input AND gate
Truth Table
dxxs1s0
dxxs1s0
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Demultiplexer (DMX)
19
1-to-4 Demultiplexer
Select input to output based on S1S0
3 input AND gate
Truth Table
ds1s0
ds1s0
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Creating State Machines

(1) states with same next state (look at the
columns of state table): AD adjacent
20
Legend:
input/output
(2) states that are next states of a common

state (look at the rows of state table) : AB
(2x), AC, DC adjacent
(3) states with same output for given input:
ABC adjacent
Assignment map
Code
State
00
01
11
10
State table
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Step 5: Transition Table
21
State table
Assign FFs per the

Assignment map
Code (Q1Q2)
State
00
01
11
10
Transition Table
Q1 Q2
D Flip-Flop
D
Q
Q
Q1 + Q 2 +
X=0
X=1
X=0
X=1
00
00
01
01
00
11
11
10
11
10
00
01
Q=present state FF, Q+=next desired state, Z=output

Clock
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22
Step 6: Find Next States and Decoders: Use K-maps

Transition
Table
Q 1 Q2
Q1 + Q2 +
X=0
X=1
X=0
X=1
00
00
01
01
00
11
11
10
11
10
00
01
K-maps
Q1 +
X
Q2 +
00
01
11
10
Q1Q2
00
01
11
10
Q1Q2
00
01
11
10
Q1Q2
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23
Step 7: Use K-maps Decoder (triple check your work!)

Q1+
X
Q2 +
00
01
11
10
Q1Q2
00
01
11
10
Q1Q2
XQ2
Z
X
00
01
11
10
Q1Q2
Q1 Q 2
D1 = Q1+ = X Q2 + Q1 Q2
D 2 = Q2+ = X
Z = X Q 1 Q2
Dont forget:
1) Q1 , Q2 are the outputs (current states) of the FFs,
2) Q1+, Q2+ are the inputs (next states) to the FFs,
3) Z is the final output of the design
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Step 8: Circuit !
Q1+ = XQ2 + Q1Q2
Q1Q2
Z = XQ1Q2
Q2+ = X
Q1+
SET
Q1
XQ2
CLR
Q1Q2
Q2
Q1
Q2
Q2+
SET
CLR
Q2
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25
VHDL
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VHDL: Overview
26
Model
Mathematical Description of a physical device
Simulation
Analysis (automated) of a model given a set of inputs
Digital Circuit Models
Structural: defines sub-models and how they are
interconnected (FFs, Gates, etc)
Behavioral: defines the behavior of the circuit (no
actual components)
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Levels of Abstraction: Behavioral, Structural, Physical
27
S <=AB
Behavioral
(Algorithms, Dataflow)
Structural
(Components,
interconnections)
Physical
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Combinational Circuits
28
Concurrent Statements
C<=A and B after 5 ns;
E<=C or D after 5 ns;
Order is not important
E<=C or D after 5 ns;
C<=A and B after 5 ns;
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Priority of Operators
29
Let A=110, B=111, C=011000, and D=111011

(A & not B or C ror 2 and D)="1010010)
Order: not, &, ror, or, and, =

1) not B = 000 --bit-by-bit complement
2) A & not B = 110000 --concatenation
3) C ror 2 = 000110 --rotate right 2
places
4) (A & not B) or (C ror 2) = 110110
--bit-by-bit or
5) (A & not B or C ror 2) and D = 110010
--bit-by-bit and
6) [(A & not B or C ror 2 and D) =
110010]=TRUE --with parentheses the
equality test is done last
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Example: 1-bit Full Adder

Co = A B + A Ci + B Ci; S=A + B
30
+ Ci
entity FullAdder is
port (A,B,Ci: in bit
Co,S: out bit
end FullAdder;
architecture Eq of FullAdder is
begin
S <= A xor B xor Ci;
Co <= (A and b) or (A and Ci) or (B
and Ci);
end Eq;
Use ( )to specify order of
precedence
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4 bit Ripple Carry Adder
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Fast Carry Adder or Carry Look-Ahead Adder

Problem: ripple carry adder is too slow
32
Propagation
delay on the order of number of bits

let gate delay = tg, 1-bit adder delay = 2tg (SOP
expressions for both sum and carry)
sum(i):= A(i) xor B(i) xor Carry;
carry := (A(i) and Cin) or (B(i) and
Cin) or (A(i) and B(i));
Instead or each stage, you can determine

If a carry is generated (A=1 and B=1) or
If a carry is propagated (A=1 or B=1 and carry =1)
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1-bit Carry Look-Ahead Adder
33
entity CLA1 is
port(A,B,C1: in std_logic;
P,G,S: out std_logic);
end CLA1;
architecture behav of CLA1 is
begin
S <= A xor B xor C1;
P <= A or B; --A xor B is more accurate
G <= A and B;
end behav;
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34
4-bit Ripple Carry Adder
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35
Use 4-bit modules in hierachical structure to add large number of

bits
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Sequential Statements
36
What does this process do?

process (A, B)
begin
C <= A and B;
Not_C <= not C;
end process
C never gets updated.
Add C in the sensitivity list
If you use variables, then assignment is
instantaneous
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Q: What does this model?
37
--------------------------------------------
process(D, G)
begin
if (G='1') then
Q <= D;
end if;
end process;
-------------------------------------------EE 3610 Digital Systems
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D Flip Flop
entity DFF is
port (D, CLK, CLR: in bit;
Q: out bit; QN: out bit:='1');
CLR
---intialize Q' to '1' since bit

are intialized to '0' by default
signals
end DFF
architecture so of DFF is
begin
process (CLK,CLR)
begin
if CLR='0' then
Rising Edge of the
Q <='0'; QN<='1';
Clock
else if CLK'event and CLK='1' then
Can also use
Q <= D after 10 ns;
if rising_edge(clk)) then
QN <= not D after 10 ns;
end if;
end if;
end process;
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State Machines
39
Rather than assigning state codes, let VHDL

Compiler do it
Enumerated Types
type state_type is(state A, state B,...);
signal present_state, next_state:state_type
Now we can write,

present_state <= state A;
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MUX: Using when and else Concurrently
40
F <= I0 when A='0' else B;
F <= I0
I1
I2
I3
when
when
when
when
B='00' else
B='01' else
B='10' else
B='11';
not necessary
bit_array (1 down to 0)
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Arrays
41
All arrays must have a new "type" explicitly defined

type register_file is array (0 to 255) of
bit_vector (15 downto 0);
signal reg0: register_file
Access each element using parentheses

reg0(1)<=reg0(2);--cycle
Type can be unconstained (unknown dimension):

1) low and high bound are defined when a
signal/variable is delcared
2) index must be an integral type: natural, positive
type intvec is array(natural range <>) of integer;
signal intvec5: intvec(1 to 5) := (3,26,8,90,1);

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Loops: Examples
42
32 bit Ripple Carry Adder

process(A,B,Cin)
variable carry: bit; sum: bit_vector (32
downto 0)
begin
carry := Cin;
loop1 for i in 0 to 31 loop
sum(i):= A(i) xor B(i) xor Carry;
carry := (A(i) and Cin) or (B(i) and
Cin) or (A(i) and B(i));
Cin := carry;
end loop loop1;
Cout <= carry;
S <= sum;
end process;
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Read Only Memory (ROM)
43
1. Each output pattern stored in the ROM is called a

word
2. Each input combination serves as an address which
can select one of the words which is stored in the
memory.
3. We defined a ROM (2n x m ROM), means an
array of 2n words and each word is m bits long.
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Usefulness of ROM
Figure
9.20
8-Word
X 4-Bit
ROM
ROM can
model
anyAn
n-input,
m-output
combinational
44
logic problem
Example: BCD to 7-Segment Display
Inputs: 4 bit BCD code
Outputs: 7 control signals for the display
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VHDL for ROM: declare constants

9.20 An 8-Word X 4-Bit ROM
library Figure
ieee;
45
use ieee.std_logic_1164.all;
entity rom16x8 is
port(addr: in integer range 0 to 15;---can also have bits
here instead
data: out std_ulogic_vector(7 downto 0));
end entity;
architecture sevenseg of rom16x8 is
type rom_array is array (0 to 15) of std_ulogic_vector (7
downto 0);
constant rom: rom_array := ( 11111011, 00010010,
10011011, 10010011, 01011011, 00111010,
11111011, 00010010, 10100011, 10011010,
01111011, 00010010, 10101001, 00110110,
11011011, 01010010);
begin
data <= rom(addr);-may have to use to to_integer if bits
end architecture;
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46
Vector/Numeric
Conversions
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Vector/Numeric Conversions
47
unsigned_vect
<= to_unsigned
(int, 8) FPGA
Figure 9.32
Layout of a Typical
int <= to_integer (unsigned_vect);
unsigned_vect <= unsigned (vect);
vect <= std_logic_vector (unsigned_vect);
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48
Registers
and Counters
in VHDL
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Register
49
-- shift register
process (clk, reset)
begin
if reset = '1' then
tsr <= "111111111";
elsif rising_edge (clk) then
if load = '1' then
tsr <= tbr & '0';
elsif shift = '1' then
tsr <= '1' & tsr(8 downto 1);
end if;
end if;
end process;
tsmt <= tsr(0);
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Counter
50
--Timer
Process (clk)
begin
if rising_edge (clk) then
if full_bit = '1' then t <= 5208;
else t <= t-1;
end if;
end if;
end process;
timeout <= '1' when t = 0 else '0';
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51
State Machine
Charts
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State Machine Chart: Example
52
X
A
Z1=X
X
Z1=X
X
0
B
X
Z1
Z1
Z2
C/Z2
1
0
State Box
Condition
Conditional Output
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Binary Multiplier Control

4-bit Binary Multiplier
21
SM Chart for Multiplier Controller
State Machine for Multiplier Controller
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54
Inside the FPGA
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Field Programmable Gate Arra (FPGA)
55
FPGAs contain
an 9.32
array Layout
of logic cells
configurable
logic blocks
Figure
ofcalled
a Typical
FPGA
CLB
Programmable
Interconnect
Area
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SIDE NOTES: INSIDE THE FPGA
56
CLB=Configurable Logic Block=4 Slices

Slice=> two Look Up Table (LUT)s and two Flip Flops
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Xilinx's CLB
57
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LUT Implementation: Shift Register
58
16:1 MUX
16:1 Addressable Shift Register LUT

(64-bit Shift Register is max possible)
Address (A[3:0]):
(1) Dynamically changes the length of the shift register
(2) Asynchronous path to D (output)
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LUT Implementation: Shift Register
59
Shift Register LUT (SRL) Structure
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60
Debouncer
and
Single Pulser
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Debouncing Mechanical Switches
61
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Single Pulser: State Machine
62
Use two flipflops

to provide debouncing and
synchronization
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Single Pulser: VHDL
63
entity spulser is
port(reset, SYNCPRESS:in std_logic;
SP: out std_logic);
end spulser;
architecture behav of spulser is
type state_type is (S0,S1);
signal pstate, nstate:state_type;
begin
------------STATE REGISTER--------------------------------process(clk, reset) ----without reset in the sensitivity list,
--it's a sync process
begin
if reset='1' then
pstate <= S0;
elsif rising_edge(clk) then -- rising edge of clock
pstate <= nstate;
end if;
end process;
-------------------------------------------------------------EE 3610 Digital Systems
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Single Pulser: VHDL
64
------------STATE Controller--------------------------------process (pstate, SYNCPRESS)

begin
SP <= '0';
case pstate is
when S0 =>
if SYNCPRESS = '0' then nstate <= S0;
else
nstate <= S1; SP='1';
end if;
when S1 =>
if SYNCPRESS = '1' then nstate <= S1;
else
nstate <= S0;
end if;
end process
end behav;
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EE 3610: Digital Systems

EE 3610 Digital Systems

EE 3610 Digital Systems

Low Level Modules: Gates

Functions: done in class

EE 3610 Digital Systems

Combinational Logic (text, p4):

Types of Digital System

Full Adder (done in class)

Full Adder using K-Map

EE 3610 Digital Systems

Implementation of Logic Gates

Logic Devices: NAND, NOR

EE 3610 Digital Systems

Implementation of Logic Gates

EE 3610 Digital Systems

EE 3610 Digital Systems

EE 3610 Digital Systems

SR Latch (Set-Reset Latch)

NOR Truth Table

3) S=0, R=0: latch, no

Master-Slave D Latch: D Flip-Flop (FF)

What happens to Qs (output

EE 3610 Digital Systems

Essence of D Flip Flop

D Flip-Flop(Synchronous 1-bit memory)

Note: propagation delay between D and Q is omitted

T Flip Flop: Tie J and K to high

Serial In Parallel Out (SIPO) 4 bit register

EE 3610 Digital Systems

Select input to output based on S1S0

Creating State Machines

(2) states that are next states of a common

EE 3610 Digital Systems

Creating State Machines

Assign FFs per the

Q=present state FF, Q+=next desired state, Z=output

Creating State Machines

Step 6: Find Next States and Decoders: Use K-maps

EE 3610 Digital Systems

Creating State Machines

Step 7: Use K-maps Decoder (triple check your work!)

Creating State Machines

EE 3610 Digital Systems

EE 3610 Digital Systems

EE 3610 Digital Systems

Levels of Abstraction: Behavioral, Structural, Physical

EE 3610 Digital Systems

Let A=110, B=111, C=011000, and D=111011

Order: not, &, ror, or, and, =

Example: 1-bit Full Adder

4 bit Ripple Carry Adder

EE 3610 Digital Systems

Fast Carry Adder or Carry Look-Ahead Adder

delay on the order of number of bits

Instead or each stage, you can determine

1-bit Carry Look-Ahead Adder

EE 3610 Digital Systems

4-bit Carry Look-Ahead Adder

4-bit Ripple Carry Adder

4-bit Carry Look-Ahead Adder

EE 3610 Digital Systems

16-bit Carry Look-Ahead Adder