Data Sheet
FEATURES
APPLICATIONS
14 Bits
SingleEnded
Inputs
AD7608
AD7606
AD7606-6
AD7606-4
AD7607
True
Differential
Inputs
AD7609
Number of
Simultaneous
Sampling Channels
8
8
6
4
8
CLAMP
CLAMP
V2
CLAMP
V2GND
CLAMP
V3
V3GND
V4
V4GND
CLAMP
CLAMP
CLAMP
CLAMP
V5
CLAMP
V5GND
CLAMP
V6
CLAMP
V6GND
CLAMP
V7
CLAMP
V7GND
CLAMP
V8
CLAMP
V8GND
CLAMP
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
1M
RFB
SECONDORDER LPF
REGCAP
REGCAP
2.5V
LDO
2.5V
LDO
REFCAPB REFCAPA
T/H
REFIN/REFOUT
SECONDORDER LPF
T/H
2.5V
REF
SECONDORDER LPF
T/H
REF SELECT
AGND
OS 2
OS 1
OS 0
SECONDORDER LPF
T/H
SERIAL
8:1
MUX
SECONDORDER LPF
T/H
16-BIT
SAR
DIGITAL
FILTER
PARALLEL/
SERIAL
INTERFACE
DOUTA
DOUTB
RD/SCLK
CS
PAR/SER/BYTE SEL
VDRIVE
SECONDORDER LPF
T/H
PARALLEL
DB[15:0]
AD7606
SECONDORDER LPF
SECONDORDER LPF
T/H
CLK OSC
CONTROL
INPUTS
T/H
AGND
BUSY
FRSTDATA
08479-001
V1
V1GND
AVCC
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD7606/AD7606-6/AD7606-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 4
Terminology .................................................................................... 21
Layout Guidelines....................................................................... 32
Converter Details........................................................................ 22
REVISION HISTORY
1/12Rev. B to Rev. C
Changes to Analog Input Ranges Section ................................... 22
10/11Rev. A to Rev. B
Changes to Input High Voltage (VINH) and Input Low Voltage
(VINL) Parameters and Endnote 6, Table 2 ..................................... 4
Changes to Table 3 ............................................................................ 7
Changes to Table 4 .......................................................................... 11
Changes to Pin 32 Description, Table 6 ....................................... 13
Changes to Analog Input Clamp Protection Section................. 22
Changes to Typical Connection Diagram Section ..................... 25
8/10Rev. 0 to Rev. A
Changes to Note 1, Table 2 .............................................................. 6
5/10Revision 0: Initial Version
Rev. C | Page 2 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
GENERAL DESCRIPTION
The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous
sampling, analog-to-digital data acquisition systems (DAS) with
eight, six, and four channels, respectively. Each part contains
analog input clamp protection, a second-order antialiasing filter,
a track-and-hold amplifier, a 16-bit charge redistribution successive
approximation analog-to-digital converter (ADC), a flexible
digital filter, a 2.5 V reference and reference buffer, and high
speed serial and parallel interfaces.
Patent pending.
Rev. C | Page 3 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
SPECIFICATIONS
VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR) 2, 3
tGROUP DELAY
DC ACCURACY
Resolution
Differential Nonlinearity2
Integral Nonlinearity2
Total Unadjusted Error (TUE)
Positive Full-Scale Error2, 5
Positive Full-Scale Error Drift
Positive Full-Scale Error Matching2
Bipolar Zero Code Error2, 6
Bipolar Zero Code Error Drift
Bipolar Zero Code Error Matching2
Negative Full-Scale Error2, 5
Negative Full-Scale Error Drift
Negative Full-Scale Error Matching2
Test Conditions/Comments
fIN = 1 kHz sine wave unless otherwise noted
Oversampling by 16; 10 V range; fIN = 130 Hz
Oversampling by 16; 5 V range; fIN = 130 Hz
No oversampling; 10 V Range
No oversampling; 5 V range
No oversampling; 10 V range
No oversampling; 5 V range
No oversampling; 10 V range
No oversampling; 5 V range
Min
Typ
94
93
88.5
87.5
88
87
95.5
94.5
90
89
90
89
90.5
90
107
108
Max
95
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
110
106
95
dB
dB
dB
3 dB, 10 V range
3 dB, 5 V range
0.1 dB, 10 V range
0.1 dB, 5 V range
10 V Range
5 V Range
23
15
10
5
11
15
kHz
kHz
kHz
kHz
s
s
No missing codes
10 V range
5 V range
External reference
Internal reference
External reference
Internal reference
10 V range
5 V range
10 V range
5 V range
10 V range
5 V range
10 V range
5 V range
External reference
Internal reference
External reference
Internal reference
10 V range
5 V range
Rev. C | Page 4 of 36
16
0.5
0.5
6
12
8
8
2
7
5
16
1
3
10
5
1
6
8
8
4
8
5
16
0.99
2
32
32
40
6
12
8
22
32
32
40
Bits
LSB 4
LSB
LSB
LSB
LSB
LSB
ppm/C
ppm/C
LSB
LSB
LSB
LSB
V/C
V/C
LSB
LSB
LSB
LSB
ppm/C
ppm/C
LSB
LSB
Data Sheet
Parameter
ANALOG INPUT
Input Voltage Ranges
Analog Input Current
Input Capacitance 7
Input Impedance
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
Input Capacitance7
Reference Output Voltage
Reference Temperature Coefficient
LOGIC INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)7
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating-State Leakage Current
Floating-State Output Capacitance7
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
AVCC
VDRIVE
ITOTAL
Normal Mode (Static)
AD7606/AD7606-6/AD7606-4
Test Conditions/Comments
Min
RANGE = 1
RANGE = 0
10 V; see Figure 31
5 V; see Figure 31
Max
Unit
10
5
V
V
A
A
pF
M
2.525
1
V
A
pF
V
5.4
2.5
5
1
Typ
2.475
REF SELECT = 1
REFIN/REFOUT
2.5
7.5
2.49/
2.505
10
ppm/C
0.7 VDRIVE
0.3 VDRIVE
2
V
V
A
pF
0.2
20
V
V
A
pF
5
ISOURCE = 100 A
ISINK = 100 A
VDRIVE 0.2
1
5
Twos complement
All eight channels included; see Table 3
4
1
200
s
s
kSPS
5.25
5.25
V
V
16
14
12
22
20
17
mA
mA
mA
20
18
15
5
2
27
24
21
8
6
mA
mA
mA
mA
A
Standby Mode
Shutdown Mode
Rev. C | Page 5 of 36
AD7606/AD7606-6/AD7606-4
Parameter
Power Dissipation
Normal Mode (Static)
Normal Mode (Operational) 8
Data Sheet
Test Conditions/Comments
AD7606
fSAMPLE = 200 kSPS
AD7606
AD7606-6
AD7606-4
Standby Mode
Shutdown Mode
Min
Typ
Max
Unit
80
115.5
mW
100
90
75
25
10
142
126
111
42
31.5
mW
mW
mW
mW
W
Temperature range for the B version is 40C to +85C. The AD7606 is operational up to 125C with throughput rates 160 kSPS, and the SNR typically reduces by
0.7 dB at 125C.
See the Terminology section.
3
This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB
and THD by 3 dB.
4
LSB means least significant bit. With 5 V input range, 1 LSB = 152.58 V. With 10 V input range, 1 LSB = 305.175 V.
5
These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from
the external reference.
6
Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section.
7
Sample tested during initial release to ensure compliance.
8
Operational power/current figure includes contribution when running in oversampling mode.
1
Rev. C | Page 6 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
Unit
9.7
9.4
10.7
s
s
4.15
9.1
18.8
39
78
158
315
100
s
s
s
s
s
s
s
s
s
s
tCONV 2
3.45
4.15
3.45
7.87
16.05
33
66
133
257
tWAKE-UP STANDBY
9.1
18.8
39
78
158
315
100
tWAKE-UP SHUTDOWN
Internal Reference
30
30
ms
External Reference
13
13
ms
7.87
16.05
33
66
133
257
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
t5 3
50
20
20
t11
t12
4
3
2
50
20
20
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ms
25
25
ns
40
25
25
0
t6
t7
PARALLEL/BYTE READ
OPERATION
t8
t9
t10
4
3
2
45
25
25
0
25
25
ns
0
0
0
0
ns
ns
16
21
25
32
15
22
19
24
30
37
15
22
ns
ns
ns
ns
ns
ns
Rev. C | Page 7 of 36
Description
1/throughput rate
Parallel mode, reading during or after conversion; or
serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a
conversion using DOUTA and DOUTB lines
Serial mode reading after a conversion; VDRIVE = 2.7 V
Serial mode reading after a conversion; VDRIVE = 2.3 V,
DOUTA and DOUTB lines
Conversion time
Oversampling off; AD7606
Oversampling off; AD7606-6
Oversampling off; AD7606-4
Oversampling by 2; AD7606
Oversampling by 4; AD7606
Oversampling by 8; AD7606
Oversampling by 16; AD7606
Oversampling by 32; AD7606
Oversampling by 64; AD7606
STBY rising edge to CONVST x rising edge; power-up
time from standby mode
STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
Maximum delay allowed between CONVST A, CONVST
B rising edges
Maximum time between last CS rising edge and BUSY
falling edge
Minimum delay between RESET low to CONVST x high
CS to RD setup time
CS to RD hold time
RD low pulse width
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
AD7606/AD7606-6/AD7606-4
Parameter
t13
Data Sheet
Unit
16
20
25
30
19
24
30
37
ns
ns
ns
ns
16
21
25
32
19
24
30
37
t144
t15
t16
t17
22
22
ns
ns
ns
ns
ns
ns
ns
23.5
17
14.5
11.5
20
15
12.5
10
MHz
MHz
MHz
MHz
15
20
30
18
23
35
ns
ns
ns
17
23
27
34
20
26
32
39
ns
ns
ns
ns
ns
ns
22
ns
6
6
6
6
t18
t19 4
t20
t21
t22
t23
0.4 tSCLK
0.4 tSCLK
7
0.4 tSCLK
0.4 tSCLK
7
22
FRSTDATA OPERATION
t24
15
20
25
30
18
23
30
35
ns
ns
ns
ns
ns
15
20
25
30
18
23
30
35
ns
ns
ns
ns
16
20
25
30
19
23
30
35
ns
ns
ns
ns
t25
t26
Rev. C | Page 8 of 36
Description
Delay from CS until DB[15:0] three-state disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data access time after RD falling edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data hold time after RD falling edge
CS to DB[15:0] hold time
Delay from CS rising edge to DB[15:0] three-state
enabled
Frequency of serial read clock
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Delay from CS until DOUTA/DOUTB three-state
disabled/delay from CS until MSB valid
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE = 2.3 V to 2.7 V
Data access time after SCLK rising edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
SCLK low pulse width
SCLK high pulse width
SCLK rising edge to DOUTA/DOUTB valid hold time
CS rising edge to DOUTA/DOUTB three-state enabled
Delay from CS falling edge until FRSTDATA threestate disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Delay from CS falling edge until FRSTDATA high,
serial mode
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Delay from RD falling edge to FRSTDATA high
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data Sheet
AD7606/AD7606-6/AD7606-4
Limit at TMIN, TMAX
(0.1 VDRIVE and
0.9 VDRIVE
Logic Input Levels)
Min
Typ
Max
Parameter
t27
Unit
19
24
22
29
ns
ns
17
22
24
20
27
29
ns
ns
ns
Description
Delay from RD falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25V
VDRIVE = 2.3 V to 2.7V
Delay from 16th SCLK falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25V
VDRIVE = 2.3 V to 2.7V
Delay from CS rising edge until FRSTDATA threestate enabled
t28
t29
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N tCONV) + ((N 1) 1 s)). N is the oversampling ratio. For the AD7606-6,
tCONV = 3 s; and for the AD7606-4, tCONV = 2 s.
3
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
4
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
1
2
Timing Diagrams
t5
CONVST A,
CONVST B
tCYCLE
CONVST A,
CONVST B
t2
t3
tCONV
t1
BUSY
t4
CS
t7
08479-002
tRESET
RESET
t5
CONVST A,
CONVST B
tCYCLE
CONVST A,
CONVST B
t2
t3
tCONV
t1
BUSY
t6
CS
t7
08479-003
tRESET
RESET
Rev. C | Page 9 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
CS
t8
t16
t13
t14
DATA:
DB[15:0]
INVALID
t24
FRSTDATA
V1
V2
t26
V3
t17
t15
V4
V7
V8
t27
t29
08479-004
RD
t9
t11
t10
t12
CS AND RD
t16
t13
DATA:
DB[15:0]
V2
V3
V4
V5
V6
V7
t17
V8
08479-005
V1
FRSTDATA
CS
t20
t19
t18
DOUTA,
DOUTB
DB15
t22
DB14
DB13
t23
DB1
DB0
t25
t29
t28
FRSTDATA
CS
t8
t9
t10
t16
t13
DATA: DB[7:0]
INVALID
HIGH
BYTE V1
t26
FRSTDATA
t24
t14
t15
LOW
BYTE V1
HIGH
BYTE V8
t27
Rev. C | Page 10 of 36
t17
LOW
BYTE V8
t29
08479-007
RD
t11
08479-006
t21
SCLK
Data Sheet
AD7606/AD7606-6/AD7606-4
THERMAL RESISTANCE
Table 4.
Parameter
AVCC to AGND
VDRIVE to AGND
Analog Input Voltage to AGND1
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
B Version
Storage Temperature Range
Junction Temperature
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec)
Pb-Free Temperature, Soldering Reflow
ESD (All Pins Except Analog Inputs)
ESD (Analog Input Pins Only)
1
Rating
0.3 V to +7 V
0.3 V to AVCC + 0.3 V
16.5 V
0.3 V to VDRIVE + 0.3 V
0.3 V to VDRIVE + 0.3 V
0.3 V to AVCC + 0.3 V
10 mA
ESD CAUTION
40C to +85C
65C to +150C
150C
240 (+0)C
260 (+0)C
2 kV
7 kV
Rev. C | Page 11 of 36
JA
45
JC
11
Unit
C/W
AD7606/AD7606-6/AD7606-4
Data Sheet
64 63 62 61 60 59 58
V1GND
V1
V2
V3
V2GND
V4
V3GND
V5
V4GND
V6
V5GND
V6GND
V7
V7GND
V8
V8GND
AVCC 1
ANALOG INPUT
48
PIN 1
AGND 2
OS 0 3
AVCC
47
AGND
46
REFGND
POWER SUPPLY
OS 1 4
45
REFCAPB
GROUND PIN
OS 2 5
44
REFCAPA
AD7606
43
REFGND
TOP VIEW
(Not to Scale)
42
REFIN/REFOUT
41
AGND
CONVST A 9
40
AGND
CONVST B 10
39
REGCAP
RESET 11
38
AVCC
RD/SCLK 12
37
AVCC
CS 13
36
REGCAP
BUSY 14
35
AGND
FRSTDATA 15
DB0 16
34
REF SELECT
33
DB15/BYTE SEL
48
AVCC
47
AGND
46
REFGND
DATA OUTPUT
PAR/SER/BYTE SEL 6
STBY 7
DIGITAL OUTPUT
RANGE 8
DIGITAL INPUT
REFERENCE INPUT/OUTPUT
DB13
V1GND
08479-008
DB12
V2
DB14/HBEN
DB10
DB11
V2GND
DB9
V3GND
V3
AGND
AGND
DB8/DOUTB
DB7/DOUTA
VDRIVE
DB6
DB5
DB4
DB3
DB2
DB1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58
V1
AGND
V4
V4GND
V5
V5GND
V6
V6GND
AGND
AGND
57 56 55 54 53 52 51 50 49
AVCC 1
PIN 1
AGND 2
OS 0 3
OS 1 4
45
REFCAPB
GROUND PIN
OS 2 5
44
REFCAPA
REFGND
PAR/SER/BYTE SEL 6
AD7606-6
43
STBY 7
TOP VIEW
(Not to Scale)
42
REFIN/REFOUT
41
AGND
CONVST A 9
40
AGND
CONVST B 10
39
REGCAP
RESET 11
38
AVCC
RD/SCLK 12
37
AVCC
CS 13
36
REGCAP
BUSY 14
35
AGND
FRSTDATA 15
DB0 16
34
REF SELECT
33
DB15/BYTE SEL
Rev. C | Page 12 of 36
DB14/HBEN
DB13
DB12
DB10
DB11
DB9
AGND
DB8/DOUTB
DB7/DOUTA
VDRIVE
DB6
DB5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DB4
REFERENCE INPUT/OUTPUT
RANGE 8
DB3
DIGITAL INPUT
DB2
DIGITAL OUTPUT
DB1
DATA OUTPUT
08479-009
ANALOG INPUT
64 63 62 61 60 59 58
V1GND
V1
V2
AGND
V2GND
AGND
AGND
V3
AGND
V4
V3GND
V4GND
AGND
AGND
AGND
AD7606/AD7606-6/AD7606-4
AGND
Data Sheet
57 56 55 54 53 52 51 50 49
AVCC 1
ANALOG INPUT
48
PIN 1
AGND 2
OS 0 3
AVCC
47
AGND
46
REFGND
POWER SUPPLY
OS 1 4
45
REFCAPB
GROUND PIN
OS 2 5
44
REFCAPA
REFGND
DATA OUTPUT
PAR/SER/BYTE SEL 6
AD7606-4
43
STBY 7
TOP VIEW
(Not to Scale)
42
REFIN/REFOUT
41
AGND
CONVST A 9
40
AGND
CONVST B 10
39
REGCAP
RESET 11
38
AVCC
RD/SCLK 12
37
AVCC
CS 13
36
REGCAP
BUSY 14
35
AGND
FRSTDATA 15
DB0 16
34
REF SELECT
33
DB15/BYTE SEL
DIGITAL OUTPUT
RANGE 8
DIGITAL INPUT
REFERENCE INPUT/OUTPUT
08479-010
DB14/HBEN
DB13
DB12
DB10
DB11
DB9
AGND
DB8/DOUTB
DB7/DOUTA
VDRIVE
DB6
DB5
DB4
DB3
DB2
DB1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Type 1
P
AD7606
AVCC
Mnemonic
AD7606-6
AVCC
AD7606-4
AVCC
2, 26, 35,
40, 41, 47
AGND
AGND
AGND
5, 4, 3
DI
OS [2:0]
OS [2:0]
OS [2:0]
DI
PAR/SER/
BYTE SEL
PAR/SER/
BYTE SEL
PAR/SER/
BYTE SEL
DI
STBY
STBY
STBY
Description
Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to
the internal front-end amplifiers and to the ADC core. These supply pins
should be decoupled to AGND.
Analog Ground. These pins are the ground reference points for all analog
circuitry on the AD7606. All analog input signals and external reference
signals should be referred to these pins. All six of these AGND pins should
connect to the AGND plane of a system.
Oversampling Mode Pins. Logic inputs. These inputs are used to select the
oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control
bit. See the Digital Filter section for more details about the oversampling
mode of operation and Table 9 for oversampling bit decoding.
Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to
a logic low, the parallel interface is selected. If this pin is tied to a logic high,
the serial interface is selected. Parallel byte interface mode is selected when
this pin is logic high and DB15/BYTE SEL is logic high (see Table 8).
In serial mode, the RD/SCLK pin functions as the serial clock input. The
DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When
the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to
ground.
In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select
the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN
pin. DB[7:0] transfer the 16-bit conversion results in two RD operations,
with DB0 as the LSB of the data transfers.
Standby Mode Input. This pin is used to place the AD7606/AD7606-6/
AD7606-4 into one of two power-down modes: standby mode or shutdown
mode. The power-down mode entered depends on the state of the RANGE
pin, as shown in Table 7. When in standby mode, all circuitry, except the onchip reference, regulators, and regulator buffers, is powered down. When
in shutdown mode, all circuitry is powered down.
Rev. C | Page 13 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
Pin No.
8
Type 1
DI
AD7606
RANGE
Mnemonic
AD7606-6
RANGE
AD7606-4
RANGE
9, 10
DI
CONVST A,
CONVST B
CONVST A,
CONVST B
CONVST A,
CONVST B
11
DI
RESET
RESET
RESET
12
DI
RD/SCLK
RD/SCLK
RD/SCLK
13
DI
CS
CS
CS
14
DO
BUSY
BUSY
BUSY
15
DO
FRSTDATA
FRSTDATA
FRSTDATA
Description
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a
logic high, the analog input range is 10 V for all channels. If this pin is tied to
a logic low, the analog input range is 5 V for all channels. A logic change
on this pin has an immediate effect on the analog input range. Changing
this pin during a conversion is not recommended for fast throughput rate
applications. See the Analog Input section for more information.
Conversion Start Input A, Conversion Start Input B. Logic inputs. These
logic inputs are used to initiate conversions on the analog input channels.
For simultaneous sampling of all input channels, CONVST A and CONVST B
can be shorted together, and a single convert start signal can be applied.
Alternatively, CONVST A can be used to initiate simultaneous sampling: V1,
V2, V3, and V4 for the AD7606; V1, V2, and V3 for the AD7606-6; and V1
and V2 for the AD7606-4. CONVST B can be used to initiate simultaneous
sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606;
V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is
possible only when oversampling is not switched on. When the CONVST A or
CONVST B pin transitions from low to high, the front-end track-and-hold
circuitry for the respective analog inputs is set to hold.
Reset Input. When set to logic high, the rising edge of RESET resets the
AD7606/AD7606-6/AD7606-4. The part should receive a RESET pulse after
power-up. The RESET high pulse should typically be 50 ns wide. If a RESET
pulse is applied during a conversion, the conversion is aborted. If a RESET
pulse is applied during a read, the contents of the output registers reset
to all zeros.
Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/
Serial Clock Input When the Serial Interface Is Selected (SCLK). When both
CS and RD are logic low in parallel mode, the output bus is enabled.
In serial mode, this pin acts as the serial clock input for data transfers.
The CS falling edge takes the DOUTA and DOUTB data output lines out
of three-state and clocks out the MSB of the conversion result. The rising
edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB
serial data outputs. For more information, see the Conversion Control
section.
Chip Select. This active low logic input frames the data transfer. When
both CS and RD are logic low in parallel mode, the DB[15:0] output bus is
enabled and the conversion result is output on the parallel data bus lines.
In serial mode, CS is used to frame the serial read transfer and clock out
the MSB of the serial output data.
Busy Output. This pin transitions to a logic high after both CONVST A and
CONVST B rising edges and indicates that the conversion process has started.
The BUSY output remains high until the conversion process for all channels
is complete. The falling edge of BUSY signals that the conversion data is
being latched into the output data registers and is available to read after
a Time t4. Any data read while BUSY is high must be completed before the
falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have
no effect while the BUSY signal is high.
Digital Output. The FRSTDATA output signal indicates when the first channel,
V1, is being read back on the parallel, byte, or serial interface. When the
CS input is high, the FRSTDATA output pin is in three-state. The falling
edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling
edge of RD corresponding to the result of V1 then sets the FRSTDATA pin
high, indicating that the result from V1 is available on the output data bus.
The FRSTDATA output returns to a logic low following the next falling edge
of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because
this clocks out the MSB of V1 on DOUTA. It returns low on the 16th SCLK
falling edge after the CS falling edge. See the Conversion Control section
for more details.
Rev. C | Page 14 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
Pin No.
22 to 16
Type 1
DO
AD7606
DB[6:0]
Mnemonic
AD7606-6
DB[6:0]
AD7606-4
DB[6:0]
23
VDRIVE
VDRIVE
VDRIVE
24
DO
DB7/DOUTA
DB7/DOUTA
DB7/DOUTA
25
DO
DB8/DOUTB
DB8/DOUTB
DB8/DOUTB
31 to 27
DO
DB[13:9]
DB[13:9]
DB[13:9]
32
DO/DI
DB14/
HBEN
DB14/
HBEN
DB14/
HBEN
33
DO/DI
DB15/
BYTE SEL
DB15/
BYTE SEL
DB15/
BYTE SEL
34
DI
REF SELECT
REF SELECT
REF SELECT
36, 39
REGCAP
REGCAP
REGCAP
Description
Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these
pins act as three-state parallel digital input/output pins. When CS and RD
are low, these pins are used to output DB6 to DB0 of the conversion result.
When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. When
operating in parallel byte interface mode, DB[7:0] outputs the 16-bit conversion result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB.
Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin
determines the operating voltage of the interface. This pin is nominally at the
same supply as the supply of the host interface (that is, DSP and FPGA).
Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA).
When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital
input/output pin. When CS and RD are low, this pin is used to output DB7
of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions
as DOUTA and outputs serial conversion data (see the Conversion Control
section for more details). When operating in parallel byte mode, DB7 is
the MSB of the byte.
Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB).
When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital
input/output pin. When CS and RD are low, this pin is used to output
DB8 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions
as DOUTB and outputs serial conversion data (see the Conversion Control
section for more details).
Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these
pins act as three-state parallel digital input/output pins. When CS and RD
are low, these pins are used to output DB13 to DB9 of the conversion result.
When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND.
Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/
SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin.
When CS and RD are low, this pin is used to output DB14 of the conversion
result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606/
AD7606-6/AD7606-4 operate in parallel byte interface mode. In parallel
byte mode, the HBEN pin is used to select whether the most significant byte
(MSB) or the least significant byte (LSB) of the conversion result is output first.
When HBEN = 1, the MSB is output first, followed by the LSB.
When HBEN = 0, the LSB is output first, followed by the MSB.
In serial mode, this pin should be tied to GND.
Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL).
When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital
output pin. When CS and RD are low, this pin is used to output DB15 of the
conversion result. When PAR/SER/BYTE SEL = 1, the BYTE SEL pin is used to
select between serial interface mode and parallel byte interface mode
(see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the
AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1
and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode.
Internal/External Reference Selection Input. Logic input. If this pin is set to
logic high, the internal reference is selected and enabled. If this pin is set to
logic low, the internal reference is disabled and an external reference
voltage must be applied to the REFIN/REFOUT pin.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator.
These output pins should be decoupled separately to AGND using a 1 F
capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V.
Rev. C | Page 15 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
Pin No.
42
Type 1
REF
AD7606
REFIN/
REFOUT
Mnemonic
AD7606-6
REFIN/
REFOUT
AD7606-4
REFIN/
REFOUT
43, 46
44, 45
REF
REF
REFGND
REFCAPA,
REFCAPB
REFGND
REFCAPA,
REFCAPB
REFGND
REFCAPA,
REFCAPB
49
AI
V1
V1
V1
50, 52
AI GND
V1GND,
V2GND
V1GND,
V2GND
V1GND,
V2GND
51
AI
V2
V2
V2
53
54
V3
V3GND
V3
V3GND
AGND
AGND
V4
V4GND
AGND
AGND
AGND
AGND
57
AI/GND
AI GND/
GND
AI/GND
AI GND/
GND
AI
V5
V4
V3
58
AI GND
V5GND
V4GND
V3GND
59
60
AI
AI GND
V6
V6GND
V5
V5GND
V4
V4GND
61
62
AI/GND
AI GND/
GND
AI/GND
AI GND/
GND
V7
V7GND
V6
V6GND
AGND
AGND
V8
V8GND
AGND
AGND
AGND
AGND
55
56
63
64
1
Description
Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference
of 2.5 V is available on this pin for external use if the REF SELECT pin is set to
logic high. Alternatively, the internal reference can be disabled by setting
the REF SELECT pin to logic low, and an external reference of 2.5 V can be
applied to this input (see the Internal/External Reference section).
Decoupling is required on this pin for both the internal and external
reference options. A 10 F capacitor should be applied from this pin to
ground close to the REFGND pins.
Reference Ground Pins. These pins should be connected to AGND.
Reference Buffer Output Force/Sense Pins. These pins must be connected
together and decoupled to AGND using a low ESR, 10 F ceramic capacitor.
The voltage on these pins is typically 4.5 V.
Analog Input. This pin is a single-ended analog input. The analog input
range of this channel is determined by the RANGE pin.
Analog Input Ground Pins. These pins correspond to Analog Input Pin V1
and Analog Input Pin V2. All analog input AGND pins should connect to
the AGND plane of a system.
Analog Input. This pin is a single-ended analog input. The analog input
range of this channel is determined by the RANGE pin.
Analog Input 3. For the AD7606-4, this is an AGND pin.
Analog Input Ground Pin. For the AD7606-4, this is an AGND pin.
Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin.
Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an
AGND pin.
Analog Inputs. These pins are single-ended analog inputs. The analog
input range of these channels is determined by the RANGE pin.
Analog Input Ground Pins. All analog input AGND pins should connect to
the AGND plane of a system.
Analog Inputs. These pins are single-ended analog inputs.
Analog Input Ground Pins. All analog input AGND pins should connect to
the AGND plane of a system.
Analog Input Pins. For the AD7606-4, this is an AGND pin.
Analog Input Ground Pins. For the AD7606-4, this is an AGND pin.
Analog Input Pin. For the AD7606-4 and AD7606-6, this is an AGND pin.
Analog Input Ground Pin. For the AD7606-4 and AD7606-6, this is an
AGND pin.
P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, GND is ground.
Rev. C | Page 16 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
AVCC, VDRIVE = 5V
FSAMPLE = 200kSPS
TA = 25C
INTERNAL REFERENCE
10V RANGE
1.5
1.0
0.5
INL (LSB)
80
100
0
0.5
120
1.0
140
1.5
160
10k
20k
30k
40k
50k
60k
70k
80k
90k
100k
2.0
08479-011
180
1.0
60
40k
50k
60k
AVCC, VDRIVE = 5V
FSAMPLE = 200kSPS
TA = 25C
INTERNAL REFERENCE
10V RANGE
0.8
0.6
0.4
DNL (LSB)
AMPLITUDE (dB)
40
30k
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
5V RANGE
FSAMPLE = 200kSPS
FIN = 1kHz
16,384 POINT FFT
SNR = 89.48dB
THD = 108.65dB
20
20k
CODE
10k
08479-013
AMPLITUDE (dB)
2.0
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
10V RANGE
FSAMPLE = 200kSPS
FIN = 1kHz
16,384 POINT FFT
SNR = 90.17dB
THD = 106.25dB
80
100
0.2
0
0.2
120
0.4
140
0.6
160
10k
20k
30k
40k
50k
60k
70k
80k
90k
100k
1.0
08479-012
180
30k
40k
50k
60k
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
10V RANGE
FSAMPLE = 11.5kSPS
TA = 25C
FIN = 133Hz
8192 POINT FFT
OS BY 16
SNR = 96.01dB
THD = 108.05dB
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
5V RANGE
FSAMPLE = 200kSPS
TA = 25C
1.5
1.0
INL (LSB)
0.5
0
0.5
1.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (kHz)
5.5
2.0
0
8192
Rev. C | Page 17 of 36
08479-015
1.5
08479-031
AMPLITUDE (dB)
20k
CODE
10k
08479-014
0.8
AD7606/AD7606-6/AD7606-4
0.50
8
NFS/PFS CHANNEL MATCHING (LSB)
0.75
0.25
0
0.25
0.50
0.75
4
NFS ERROR
2
0
2
4
6
8192
10
40
20
35
50
65
80
10
15
8
PFS/NFS ERROR (%FS)
10
NFS ERROR (LSB)
20
10V RANGE
5
5V RANGE
0
5
10
10
20
35
50
65
80
TEMPERATURE (C)
08479-017
25
AVCC, VDRIVE = 5V
FSAMPLE = 200 kSPS
TA = 25C
EXTERNAL REFERENCE
SOURCE RESISTANCE IS MATCHED ON
THE VxGND INPUT
10V AND 5V RANGE
200kSPS
AVCC, VDRIVE = 5V
EXTERNAL REFERENCE
15
20k
40k
60k
80k
100k
120k
SOURCE RESISTANCE ()
20
1.0
0.8
BIPOLAR ZERO CODE ERROR (LSB)
15
10
5
0
5V RANGE
5
10V RANGE
10
200kSPS
AVCC, VDRIVE = 5V
EXTERNAL REFERENCE
25
10
20
35
50
TEMPERATURE (C)
65
80
0.6
0.4
0.2
0
5V RANGE
0.2
0.4
10V RANGE
0.6
200kSPS
AVCC, VDRIVE = 5V
EXTERNAL REFERENCE
0.8
08479-118
15
20
40
10
TEMPERATURE (C)
20
40
25
08479-019
CODE
10V RANGE
AVCC, VDRIVE = 5V
EXTERNAL REFERENCE
9
08479-016
1.00
PFS ERROR
1.0
40
25
10
20
35
50
65
TEMPERATURE (C)
Rev. C | Page 18 of 36
80
08479-023
DNL (LSB)
10
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
5V RANGE
FSAMPLE = 200kSPS
TA = 25C
08479-018
1.00
Data Sheet
AD7606/AD7606-6/AD7606-4
98
96
3
5V RANGE
94
92
SNR (dB)
1
10V RANGE
0
90
88
84
200kSPS
AVCC, VDRIVE = 5V
EXTERNAL REFERENCE
3
4
40
25
10
20
35
50
65
80
TEMPERATURE (C)
82
80
10
OS BY 64
OS BY 32
OS BY 16
OS BY 8
OS BY 4
OS BY 2
NO OS
AVCC, VDRIVE = 5V
FSAMPLE CHANGES WITH OS RATE
TA = 25C
INTERNAL REFERENCE
5V RANGE
100
1k
10k
100k
08479-020
86
2
08479-024
Data Sheet
Figure 26. SNR vs. Input Frequency for Different Oversampling Rates, 5 V Range
40
100
10V RANGE
AVCC, VDRIVE = +5V
50 FSAMPLE = 200kSPS
RSOURCE MATCHED ON Vx AND VxGND INPUTS
98
96
60
94
105k
48.7k
23.7k
10k
5k
1.2k
100
51
0
100
110
120
1k
10k
100k
84
82
80
10
80
105k
48.7k
23.7k
10k
5k
1.2k
100
51
0
INPUT FREQUENCY (Hz)
100k
08479-122
THD (dB)
70
10k
100
1k
10k
100k
50
60
120
1k
AVCC, VDRIVE = 5V
FSAMPLE CHANGES WITH OS RATE
TA = 25C
INTERNAL REFERENCE
10V RANGE
Figure 27. SNR vs. Input Frequency for Different Oversampling Rates, 10 V Range
5V RANGE
AVCC, VDRIVE = +5V
50 FSAMPLE = 200kSPS
RSOURCE MATCHED ON Vx AND VxGND INPUTS
110
OS BY 64
OS BY 32
OS BY 16
OS BY 8
OS BY 4
OS BY 2
NO OS
40
100
88
86
Figure 24. THD vs. Input Frequency for Various Source Impedances,
10 V Range
90
90
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
AD7606 RECOMMENDED DECOUPLING USED
FSAMPLE = 150kSPS
70 TA = 25C
INTERFERER ON ALL UNSELECTED CHANNELS
80
60
90
10V RANGE
100
5V RANGE
110
120
130
140
0
20
40
60
80
100
120
Figure 25. THD vs. Input Frequency for Various Source Impedances,
5 V Range
Rev. C | Page 19 of 36
140
160
08479-025
90
92
08479-121
SNR (dB)
80
08479-021
THD (dB)
70
AD7606/AD7606-6/AD7606-4
Data Sheet
22
100
10V RANGE
20
94
5V RANGE
92
90
88
86
84 AVCC, VDRIVE = 5V
TA = 25C
82 INTERNAL REFERENCE
FSAMPLE SCALES WITH OS RATIO
80
OFF
OS2
OS4
OS8
OS16
OS32
08479-026
OS64
OVERSAMPLING RATIO
18
16
14
12
AVCC, VDRIVE = 5V
10 TA = 25C
INTERNAL REFERENCE
FSAMPLE VARIES WITH OS RATE
8
NO OS
OS2
OS4
OS8
AVCC = 5.25V
AVCC = 5V
2.5000
2.4995
AVCC = 4.75V
2.4990
2.4980
40
25
10
20
35
50
65
80
TEMPERATURE (C)
08479-029
2.4985
2
0
2
4
6
10
10
10
08479-028
+85C
+25C
40C
130
120
10V RANGE
110
5V RANGE
100
90
80
AVCC, VDRIVE = 5V
INTERNAL REFERENCE
AD7606 RECOMMENDED DECOUPLING USED
FSAMPLE = 200kSPS
TA = 25C
70
60
0
100
200
300
400
500
600
Figure 31. Analog Input Current vs. Temperature for Various Supply Voltages
Rev. C | Page 20 of 36
700
800
OS64
140
2.5005
OS32
2.5010
OS16
OVERSAMPLING RATIO
08479-030
96
08479-027
98
Data Sheet
AD7606/AD7606-6/AD7606-4
TERMINOLOGY
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, at LSB below the first
code transition; and full scale, at LSB above the last code
transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Code Error
The deviation of the midscale transition (all 1s to all 0s) from
the ideal, which is 0 V LSB.
Bipolar Zero Code Error Match
The absolute difference in bipolar zero code error between any
two input channels.
Positive Full-Scale Error
The deviation of the actual last code transition from the ideal
last code transition (10 V 1 LSB (9.99954) and 5 V 1 LSB
(4.99977)) after bipolar zero code error is adjusted out. The
positive full-scale error includes the contribution from the
internal reference buffer.
Positive Full-Scale Error Match
The absolute difference in positive full-scale error between any
two input channels.
Negative Full-Scale Error
The deviation of the first code transition from the ideal first
code transition (10 V + LSB (9.99984) and 5 V + LSB
(4.99992)) after the bipolar zero code error is adjusted out.
The negative full-scale error includes the contribution from the
internal reference buffer.
Negative Full-Scale Error Match
The absolute difference in negative full-scale error between any
two input channels.
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2, excluding dc).
The ratio depends on the number of quantization levels in
the digitization process: the more levels, the smaller the
quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 16-bit converter, the signal-to-(noise + distortion)
is 98 dB.
V2 2 V3 2 V4 2 V5 2 V6 2 V7 2 V8 2 V9 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2 to V9 are the rms amplitudes of the second through ninth
harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
determined by a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb, where m, n = 0,
1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n is equal to 0. For example, the second-order
terms include (fa + fb) and (fa fb), and the third-order terms
include (2fa + fb), (2fa fb), (fa + 2fb), and (fa 2fb).
The calculation of the intermodulation distortion is per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in decibels (dB).
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but not
the converters linearity. PSR is the maximum change in fullscale transition point due to a change in power supply voltage
from the nominal value. The PSR ratio (PSRR) is defined as the
ratio of the power in the ADC output at full-scale frequency, f,
to the power of a 100 mV p-p sine wave applied to the ADCs
VDD and VSS supplies of Frequency fS.
PSRR (dB) = 10 log (Pf/PfS)
where:
Pf is equal to the power at Frequency f in the ADC output.
PfS is equal to the power at Frequency fS coupled onto the AVCC
supply.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between all input channels. It is measured by applying a full-scale
sine wave signal, up to 160 kHz, to all unselected input channels
and then determining the degree to which the signal attenuates
in the selected channel with a 1 kHz sine wave signal applied (see
Figure 28).
Rev. C | Page 21 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
THEORY OF OPERATION
CONVERTER DETAILS
VxGND
CLAMP
1M
SECONDORDER
LPF
RFB
08479-032
CLAMP
15
10
10
15
20
08479-033
ANALOG INPUT
Vx
RFB
1M
Rev. C | Page 22 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
R
R C
Vx
CLAMP
VxGND
CLAMP
1M
1M
08479-034
ANALOG
INPUT
SIGNAL
hold (that is, the delay time between the external CONVST x
signal and the track-and-hold actually going into hold) is well
matched, by design, across all eight track-and-holds on one
device and from device to device. This matching allows more
than one AD7606/AD7606-6/AD7606-4 device to be sampled
simultaneously in a system.
RFB
AD7606
RFB
AV , V
= 5V
5 F CC DRIVE
SAMPLE = 200kSPS
TA = 25C
10
5V RANGE
15
20
25
30
35
10V RANGE
40
+25
+85
0.1dB
10,303
9619
9326
3dB
24,365Hz
23,389Hz
22,607Hz
5V RANGE
40
+25
+85
0.1dB
5225
5225
4932
3dB
16,162Hz
15,478Hz
14,990Hz
40
100
1k
10k
100k
18
16
14
011...111
011...110
10V RANGE
ADC CODE
12
10
VIN
32,768
10V
VIN
5V CODE =
32,768
5V
10V CODE =
5V RANGE
8
6
4
000...001
000...000
111...111
REF
2.5V
REF
2.5V
LSB =
+FS (FS)
216
2
100...010
100...001
100...000
0
2
ANALOG INPUT
10k
100k
+FS
10V RANGE +10V
5V RANGE +5V
08479-036
4 AVCC, VDRIVE = 5V
FSAMPLE = 200kSPS
6
TA = 25C
8
10
1k
MIDSCALE
0V
0V
FS
10V
5V
LSB
305V
152V
08479-037
ATTENUATION (dB)
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7606/AD7606-6/
AD7606-4 allow the ADC to accurately acquire an input sine wave
of full-scale amplitude to 16-bit resolution. The track-and-hold
amplifiers sample their respective inputs simultaneously on the
rising edge of CONVST x. The aperture time for the track-and-
Rev. C | Page 23 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
INTERNAL/EXTERNAL REFERENCE
10F
REFCAPB
2.5V
REF
AD7606
AD7606
AD7606
REF SELECT
REF SELECT
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
100nF
100nF
100nF
ADR421
0.1F
VDRIVE
AD7606
AD7606
REFCAPA
08479-040
SAR
BUF
AD7606
REF SELECT
REF SELECT
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
10F
100nF
100nF
08479-039
REFIN/REFOUT
08479-038
The REF SELECT pin is a logic input pin that allows the user to
select between the internal reference and an external reference.
If this pin is set to logic high, the internal reference is selected
and enabled. If this pin is set to logic low, the internal reference
is disabled and an external reference voltage must be applied
to the REFIN/REFOUT pin. The internal reference buffer is
always enabled. After a reset, the AD7606/AD7606-6/AD7606-4
operate in the reference mode selected by the REF SELECT pin.
Decoupling is required on the REFIN/REFOUT pin for both
the internal and external reference options. A 10 F ceramic
capacitor is required on the REFIN/REFOUT pin.
Rev. C | Page 24 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
Power-Down Mode
Standby
Shutdown
POWER-DOWN MODES
Two power-down modes are available on the AD7606/AD7606-6/
AD7606-4: standby mode and shutdown mode. The STBY pin
controls whether the AD7606/AD7606-6/AD7606-4 are in
normal mode or in one of the two power-down modes.
ANALOG SUPPLY
VOLTAGE 5V1
1F
REFIN/REFOUT
100nF
100nF
REGCAP2
AVCC
VDRIVE
REFCAPA
10F
DB0 TO DB15
+
REFCAPB
REFGND
EIGHT ANALOG
INPUTS V1 TO V8
V1
V1GND
V2
V2GND
V3
V3GND
V4
V4GND
V5
V5GND
V6
V6GND
V7
V7GND
V8
V8GND
PARALLEL
INTERFACE
CONVST A, CONVST B
CS
RD
BUSY
AD7606
RESET
OS 2
OS 1
OS 0
OVERSAMPLING
REF SELECT
VDRIVE
PAR/SER SEL
RANGE
STBY
VDRIVE
AGND
1DECOUPLING
SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48).
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38.
SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
2DECOUPLING
Rev. C | Page 25 of 36
08479-041
MICROPROCESSOR/
MICROCONVERTER/
DSP
10F
DIGITAL SUPPLY
VOLTAGE +2.3V TO +5.25V
RANGE
1
0
AD7606/AD7606-6/AD7606-4
Data Sheet
CONVERSION CONTROL
V1 TO V4 TRACK-AND-HOLD
ENTER HOLD
V5 TO V8 TRACK-AND-HOLD
ENTER HOLD
CONVST A
t5
CONVST B
AD7606 CONVERTS
ON ALL 8 CHANNELS
BUSY
tCONV
CS/RD
V1
V2
V3
V7
V8
08479-042
DATA: DB[15:0]
FRSTDATA
Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B SignalsParallel Mode
Rev. C | Page 26 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
DIGITAL INTERFACE
The AD7606/AD7606-6/AD7606-4 provide three interface
options: a parallel interface, a high speed serial interface, and
a parallel byte interface. The required interface mode is selected
via the PAR/SER/BYTE SEL and DB15/BYTE SEL pins.
Table 8. Interface Mode Selection
PAR/SER/BYTE SEL
0
1
1
DB15
0
0
1
Interface Mode
Parallel interface mode
Serial interface mode
Parallel byte interface mode
INTERRUPT
BUSY 14
[33:24]
DB[15:0] [22:16]
DIGITAL
HOST
08479-043
CS 13
RD/SCLK 12
Figure 45. AD7606 Interface DiagramOne AD7606 Using the Parallel Bus,
with CS and RD Shorted Together
The rising edge of the CS input signal three-states the bus, and
the falling edge of the CS input signal takes the bus out of the
high impedance state. CS is the control signal that enables the
data lines; it is the function that allows multiple AD7606/
AD7606-6/ AD7606-4 devices to share the same parallel
data bus.
The CS signal can be permanently tied low, and the RD signal
can be used to access the conversion results as shown in Figure 4.
A read operation of new data can take place after the BUSY
signal goes low (see Figure 2); or, alternatively, a read operation
of data from the previous conversion process can take place
while BUSY is high (see Figure 3).
The RD pin is used to read data from the output conversion
results register. Applying a sequence of RD pulses to the RD pin
of the AD7606/AD7606-6/AD7606-4 clocks the conversion
results out from each channel onto the Parallel Bus DB[15:0] in
ascending order. The first RD falling edge after BUSY goes low
clocks out the conversion result from Channel V1. The next RD
falling edge updates the bus with the V2 conversion result, and so
on. On the AD7606, the eighth falling edge of RD clocks out the
conversion result for Channel V8.
Rev. C | Page 27 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
The CS falling edge takes the data output lines, DOUTA and DOUTB,
out of three-state and clocks out the MSB of the conversion
result. The rising edge of SCLK clocks all subsequent data bits
onto the serial data outputs, DOUTA and DOUTB. The CS input
can be held low for the entire serial read operation, or it can be
pulsed to frame each channel read of 16 SCLK cycles. Figure 46
shows a read of eight simultaneous conversion results using two
DOUT lines on the AD7606. In this case, a 64 SCLK transfer is used
to access data from the AD7606, and CS is held low to frame the
entire 64 SCLK cycles. Data can also be clocked out using just
one DOUT line, in which case it is recommended that DOUTA be
used to access all conversion data because the channel data is
output in ascending order. For the AD7606 to access all eight
conversion results on one DOUT line, a total of 128 SCLK cycles
is required. These 128 SCLK cycles can be framed by one CS
signal, or each group of 16 SCLK cycles can be individually
framed by the CS signal. The disadvantage of using just one
DOUT line is that the throughput rate is reduced if reading occurs
after conversion. The unused DOUT line should be left unconnected
in serial mode. For the AD7606, if DOUTB is to be used as a single
DOUT line, the channel results are output in the following order:
V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA
indicator returns low after V5 is read on DOUTB. For the AD7606-6
and the AD7606-4, if DOUTB is to be used as a single DOUT line,
the channel results are output in the following order: V4, V5, V6,
V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for
the AD7606-4.
Figure 6 shows the timing diagram for reading one channel of
data, framed by the CS signal, from the AD7606/AD7606-6/
AD7606-4 in serial mode. The SCLK input signal provides the
clock source for the serial read operation. The CS goes low to
access the data from the AD7606/AD7606-6/AD7606-4.
The falling edge of CS takes the bus out of three-state and clocks
out the MSB of the 16-bit conversion result. This MSB is valid
on the first falling edge of the SCLK after the CS falling edge.
The subsequent 15 data bits are clocked out of the AD7606/
AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on
the SCLK falling edge. To access each conversion result, 16 clock
cycles must be provided to the AD7606/AD7606-6/AD7606-4.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the CS input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
CS takes FRSTDATA out of three-state and sets the FRSTDATA
pin high, indicating that the result from V1 is available on the
DOUTA output data line. The FRSTDATA output returns to
a logic low following the 16th SCLK falling edge. If all channels
are read on DOUTB, the FRSTDATA output does not go high when
V1 is being output on this serial data output pin. It goes high
only when V1 is available on DOUTA (and this is when V5 is
available on DOUTB for the AD7606).
CS
64
DOUTA
DOUTB
V1
V2
V3
V4
V5
V6
V7
V8
Rev. C | Page 28 of 36
08479-044
SCLK
Data Sheet
AD7606/AD7606-6/AD7606-4
DIGITAL FILTER
tCYCLE
CONVST A
AND
CONVST B
DATA:
DB[15:0]
tCONV
19s
9s
4s
BUSY
OS = 0 OS = 2 OS = 4
t4
t4
t4
CS
08479-046
RD
Figure 47 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the
different oversampling rates. For example, a sampling frequency
of 10 kSPS yields a cycle time of 100 s. Figure 47 shows OS 2
and OS 4; for a 10 kSPS example, there is adequate cycle time to
further increase the oversampling rate and yield greater improvements in SNR performance. In an application where the initial
sampling or throughput rate is at 200 kSPS, for example, and
oversampling is turned on, the throughput rate must be reduced
to accommodate the longer conversion time and to allow for the
read. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the
BUSY high time. The falling edge of BUSY is used to update the
output data registers with the new conversion data; therefore, the
reading of conversion data should not occur on this edge.
CONVST A
AND
CONVST B
CONVERSION N
OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1
CONVERSION N + 1
BUSY
tOS_HOLD
08479-045
tOS_SETUP
OS x
OS
Ratio
No OS
2
4
8
16
32
64
Invalid
SNR 5 V Range
(dB)
89
91.2
92.6
94.2
95.5
96.4
96.9
SNR 10 V Range
(dB)
90
92
93.6
95
96
96.7
97
3 dB BW 5 V Range
(kHz)
15
15
13.7
10.3
6
3
1.5
Rev. C | Page 29 of 36
3 dB BW 10 V Range
(kHz)
22
22
18.5
11.9
6
3
1.5
Maximum Throughput
CONVST Frequency (kHz)
200
100
50
25
12.5
6.25
3.125
AD7606/AD7606-6/AD7606-4
Data Sheet
NO OVERSAMPLING
900 FSAMPLE = 200kSPS
AVCC = 5V
800 VDRIVE = 2.5V
928
887
700
600
1263
1000
783
800
600
400
500
200
0
300
97
100
0
CODE (LSB)
1400
OVERSAMPLING BY 16
FSAMPLE = 12.5kSPS
1200 AVCC = 5V
VDRIVE = 2.5V
NUMBER OF OCCURENCES
OVERSAMPLING BY 2
FSAMPLE = 100kSPS
1200 AVCC = 5V
VDRIVE = 2.5V
2
1
0
2
CODE (LSB)
131
0
0
3
1148
1000
804
800
08479-050
400
200
1453
1000
800
600
595
400
200
600
0
400
CODE (LSB)
08479-151
NUMBER OF OCCURENCES
OVERSAMPLING BY 8
FSAMPLE = 25kSPS
1200 AVCC = 5V
VDRIVE = 2.5V
08479-047
NUMBER OF OCCURENCES
1000
1400
NUMBER OF OCCURENCES
200
80
0
16
CODE (LSB)
1600
OVERSAMPLING BY 32
FSAMPLE = 6.125kSPS
1400 AVCC = 5V
VDRIVE = 2.5V
08479-048
NUMBER OF OCCURENCES
1262
1000
1200
1000
800
631
600
400
764
800
200
600
CODE (LSB)
400
19
CODE (LSB)
OVERSAMPLING BY 64
FSAMPLE = 3kSPS
1400 AVCC = 5V
VDRIVE = 2.5V
1679
1200
1000
800
600
400
369
200
0
CODE (LSB)
08479-153
0
3
NUMBER OF OCCURENCES
08479-049
NUMBER OF OCCURENCES
OVERSAMPLING BY 4
FSAMPLE = 50kSPS
1200 AVCC = 5V
VDRIVE = 2.5V
1417
08479-152
Data Sheet
AD7606/AD7606-6/AD7606-4
60
70
90
100
100
40
20
50
30
ATTENUATION (dB)
10
60
10k
100k
1M
10M
FREQUENCY (Hz)
08479-051
1k
20
40
50
60
70
100
100
1k
10k
100k
AVCC = 5V
VDRIVE = 5V
TA = 25C
10V RANGE
OS BY 64
20
ATTENUATION (dB)
50
60
70
80
1M
10M
FREQUENCY (Hz)
08479-052
90
100k
40
50
60
70
90
100
100
AVCC = 5V
VDRIVE = 5V
TA = 25C
10V RANGE
OS BY 8
20
50
60
70
80
10k
100k
1M
10M
08479-053
90
FREQUENCY (Hz)
10k
100k
1M
40
1k
1k
FREQUENCY (Hz)
30
100
100
30
80
10
10M
10k
1M
FREQUENCY (Hz)
40
1k
10M
AVCC = 5V
VDRIVE = 5V
TA = 25C
10V RANGE
OS BY 32
30
100
100
1M
90
AVCC = 5V
VDRIVE = 5V
TA = 25C
10V RANGE
OS BY 4
10
100k
80
10k
30
90
100
1k
80
ATTENUATION (dB)
50
FREQUENCY (Hz)
70
ATTENUATION (dB)
40
08479-155
20
30
80
AVCC = 5V
VDRIVE = 5V
TA = 25C
10V RANGE
OS BY 2
10
ATTENUATION (dB)
20
10M
08479-156
AVCC = 5V
VDRIVE = 5V
TA = 25C
10V RANGE
OS BY 16
10
08479-154
ATTENUATION (dB)
AD7606/AD7606-6/AD7606-4
Data Sheet
LAYOUT GUIDELINES
The printed circuit board that houses the AD7606/AD7606-6/
AD7606-4 should be designed so that the analog and digital
sections are separated and confined to different areas of the board.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the case of the
split plane, the digital and analog ground planes should be
joined in only one place, preferably as close as possible to the
AD7606/AD7606-6/AD7606-4.
08479-054
Rev. C | Page 32 of 36
08479-055
The power supply lines to the AVCC and VDRIVE pins on the
AD7606/AD7606-6/AD7606-4 should use as large a trace as
possible to provide low impedance paths and reduce the effect
of glitches on the power supply lines. Where possible, use supply
planes and make good connections between the AD7606 supply
pins and the power tracks on the board. Use a single via or multiple
vias for each supply pin.
Data Sheet
AD7606/AD7606-6/AD7606-4
U2
U1
08479-056
AVCC
Rev. C | Page 33 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7
3.5
0
0.08
COPLANARITY
VIEW A
16
33
32
17
VIEW A
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
ORDERING GUIDE
Model 1, 2, 3
AD7606BSTZ
AD7606BSTZ-RL
AD7606BSTZ-6
AD7606BSTZ-6RL
AD7606BSTZ-4
AD7606BSTZ-4RL
EVAL-AD7606EDZ
EVAL-AD7606-6EDZ
EVAL-AD7606-4EDZ
CED1Z
Temperature Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
Package Description
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board for the AD7606
Evaluation Board for the AD7606-6
Evaluation Board for the AD7606-4
Converter Evaluation Development
Package Option
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
Rev. C | Page 34 of 36
Data Sheet
AD7606/AD7606-6/AD7606-4
NOTES
Rev. C | Page 35 of 36
AD7606/AD7606-6/AD7606-4
Data Sheet
NOTES
Rev. C | Page 36 of 36