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Combinational Logic

Design with Verilog


always blocks
A/Prof Lindsay Kleeman
Monash University

ECE2072 Digital Systems

Slide 1

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ECE2072 Digital Systems

Slide 2

Outcomes
Design simple combinational logic with always
blocks.
Appreciate high level design approaches.
Avoid common problems.

ECE2072 Digital Systems

Slide 3

Intro to always blocks


An always block allows high level design of logic
based on behavioural descriptions, not just logic
equations.
Each always block represents parallel hardware
logic. There can be many within a module.
Always blocks can produce combinational or
sequential logic.
Structure:
always @(sensitivity list) begin
statements (eg if, case )
end
ECE2072 Digital Systems

Slide 4

Example
module MyModule(Z, A, B);
output reg Z;
All output signals of an always
input A, B;

block need a reg declaration.

(A, B) is the sensitivity list


always @(A,B)
if (A && !B) Z=1b1;
Body of always block
else Z = 1b0;
Consists of
endmodule
sequential
statements

ECE2072 Digital Systems

Slide 5

Sensitivity List
Tells the always block when it executes in a
simulation.
When a signal changes in a sensitivity list the
simulator runs the statements in the block
Eg in previous example any change in A or B will
trigger the block.

ECE2072 Digital Systems

Slide 6

Body
Sequential statement(s) execute to the end of the
block.
New values of signals at the end of the block after all
statements are used to update the outputs of the
block.
A signal should only be updated in one always
block.
SYNTHESIS tries to find hardware that matches the
behaviour of the sequential statements in the block.

ECE2072 Digital Systems

Slide 7

Example: 5:1 MUX


module MUX5to1(Z, Sel, Inputs);
output reg Z;
input [2:0] Sel;
input [4:0] Inputs;
always @(Sel, Inputs)
case (Sel)
0: Z= Inputs[0];
1: Z= Inputs[1];
2: Z= Inputs[2];
3: Z= Inputs[3];
4: Z= Inputs[4];
endcase;
endmodule;

ECE2072 Digital Systems

Whoops!
What happens
When Sel is 5
=> Latch inferred

Slide 8

Example: 5:1 MUX


module MUX5to1(Z, Sel, Inputs);
output reg Z;
input [2:0] Sel;
input [4:0] Inputs;
always @(Sel, Inputs)
case (Sel)
0: Z= Inputs[0];
1: Z= Inputs[1];
2: Z= Inputs[2];
3: Z= Inputs[3];
default: Z= Inputs[4]; // covers all input combns
endcase;
endmodule;

ECE2072 Digital Systems

Slide 9

Input Combinations
Combinational functions need to cover all input
combinations in always blocks.
Failing to cover all input combinations results in
inferred latches since the uncovered input
combination has to be preserved between sensitivity
list triggers.
Solutions:
Use default and else in case and if statements
Use assignment of default value at start of always
block.

ECE2072 Digital Systems

Slide 10

High Level Example


Design combinational logic circuit to convert a 5 bit
representation of the hours in a 24 hour clock to two
BCD digits.
Use a single always block in Verilog.
hr1
Hrs24toBCD

hrs

4
hr0

5
4

ECE2072 Digital Systems

Slide 11

Hrs24toBCD
module Hrs24toBCD(hrs, hr1, hr0);
input [4:0] hrs;
output reg [3:0] hr1, hr0;
always @(
) begin

end
endmodule
ECE2072 Digital Systems

Slide 12

Hrs24toBCD
module Hrs24toBCD(hrs, hr1, hr0);
input [4:0] hrs;
output reg [3:0] hr1, hr0;
always @( hrs
) begin // sensitivity list
hr1 = 4d0;
hr0 = hrs[3:0]; // default values covers all input combinations
if (hrs > 5d9) begin
hr1 = 4d1;
hr0 = hrs[3:0] 4d10;
if (hrs > 5d19) begin
hr1 = 4d2;
hr0 = {2b00, hrs[1:0]}; // optimised version of hrs-20
end
end
end
endmodule
ECE2072 Digital Systems

Slide 13