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PIC MICROCONTROLLERS

P R I N C I P L E S A N D A P P L I C AT I O N S O F M I C R O C O N T R O L L E R S
LECTURE #3

BY
SANIRA LASANTHA
ICBT KANDY CAMPUS
ACKNOWLEDGEMENT

DR. MALITHA WIJESUNDARA


D E A N - A C A D E M I C A F FA I R S
SLIIT

History of PIC
In 1988 General Instruments sold off their microelectronics division to Arizona
Microchip Technology.
After Microchip took over they came up with a new range of micro controllers
based on a Peripheral Interface Controller (PIC) that General Instruments had
introduced in mid 1970s which was based on the Harvard Architecture.
Their base range PIC16C5XX and currently PIC10FXXX and PIC12CXXX families
have 33 instructions and 12-bit program store with parallel ports and 8-bit
timer/counter.

The execution unit was 8-bit to match the 8-bit data store.

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Mid-range and Extendedrange PIC MCUs


By 1992 the mid-range PIC16CXXX family appeared. This has a 14-bit
Program Store, which facilitates accessing of larger Data Stores. Two
more instructions were added to the 33 instructions of the base-range.

16 series features 16-bit timers , A/D converters, and serial ports,


together with interrupt handling capabilities.

There is an extended range PIC18XXXX family introduced in 1999 with a


16-bit core and an additional 42 instructions, many of which are to
support high level language compiler needs.

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Objectives
Understand the mid-range Harvard-based Microchip PIC
microcontroller architecture

Appreciate the function, structure and memory map of the separate


Program and Data stores
Appreciate the principle of banking in the Data store and its
relationship to RP0 control bit and status register

Be able to interpret the Status register bits that control memory paging
and hold the C, DC and Z flags
Know how to manipulate the contents of the Program Counter in
conjunction with the PCLATCH special purpose register

Recognise the interaction between the clock phases and the internal
sequence of micro-operations.

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PIC16F84
From a software point of view, all members of a single family of PIC MCUs are
identical. What usually differ are the extended I/O facilities.

In 1994 the PIC16C83/4 were introduced to the mid range family. They became
popular because they were the first PIC micro controllers to use EEPROM.

In 1996 PIC16F83/4 superseded the PIC16C83/4 with Flash-EEPROM technology


for the Program Store.

PIC16F627/8 introduced in 2002 is now the recommended MCU for 18-pin


designs.

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Fetch Unit
The fetch unit is primarily concerned
with fetching instructions from
Program store down to the Pipeline.

The location of each instruction is


maintained by the Program Counter.

Each instruction is presented in turn


to the decoding circuitry, which
activates the appropriate logic in the
execute unit in the correct sequence.

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Program Store
Central to the fetch unit is the Program Store.
On power-on the operating program has to be available in Program
Store.
Program Memory is some kind of ROM.
Most PIC MCUs use some kind of EEPROM.

The F series uses Flash EEPROM.


In PIC16F84, 1024 instructions can be stored.
Each instruction comprises 14 binary bits.

PIC 16F876/7 has a capacity of 8192 instructions.

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Program Counter
PC points to the instruction being fetched at any instance.
The 13-bit register normally increments after each fetch.
However, instructions such as goto that will cause execution of the
program to jump to another part of the Program store.
Thus the PCs normal up count can be overridden.
In addition the programmer has access to the PC
Although with the 13-bit register 213 = 8192 addresses can be
accessed, in PIC16F84, only the lower 10 bits (1010=1024) are actually
connected.
The first instruction is always at h000. This is known as the reset
vector.
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Pipeline
Two 14-bit registers implement the pipeline.
Top of the pipeline holds the instruction that has just been fetched
from the Program Store. (nth fetch)
The bottom register feeds the decoder circuits and is the instruction
that is in the process of being executed. (n-1th fetch)
This pipeline action assumes that the instruction execution sequence
is linear.
For instructions that requires a jump to another part of the Program
store, instruction currently at the top of the pipeline needs to be
replaced by the far instruction.
This process is known as flushing and adds an extra machine cycle to
the execution time.
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Instruction Decoder
Instruction decoder uses logic circuitry to decode each field of the 14-bit instruction
and gate the appropriate addresses and data to the correct execution units circuitry
and configure the ALU.

ALL PIC MCU families have and integral oscillator that generates the internal timerelated sequences of micro-operations commanded by the Instruction decoder.

The timing element is typically an external quartz crystal connected across the OSC1
and OSC2 pins, and this determines the clock frequency fOSC.

Mid range devices are limited to an upper frequency of 20MHz, but some early
members were limited to 4 to 10MHz.

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Instruction Decoder
Four oscillator pulses are used as part of decoding logic to activate
internal processes in time dependent sequences.

This means that an instruction cycle takes 4 external clock cycles.


Therefore, the instruction cycle rate is fOSC /4 .
Therefore if you have a 4MHz crystal the instruction cycle rate is 1MHz
(one million instructions per second), corresponding to a period of 1s.

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Internal clock sequencing


waveforms

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Clock related sequence of


operations in the fetch unit
Q1:

Increment the Program Counter and copy onto the Program store address bus.

Q4:

Read the instruction code off program stores data bus into Instruction register 1
and at the same time move the previous instruction down the Pipeline into
Instruction register 2, where it is presented to the Instruction decoder.

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Stack
Eight 13-bit registers are stacked together and are connected to the
program counter.

Stack is used to hold past states of the Program Counter to remember


the jumping-off point when a subroutine is called up.

We shall discuss this in detail later on.

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Execute Unit
The 8-bit execute unit is responsible for reading a datum from the Data
store or literal datum from the instruction and processing this byte as
commanded by the Instruction decoder using the ALU.

The outcome is placed either in the Working register or back in the Data
store, overwriting the original datum. (again this is done as indicated by
the instruction and decoded by the ID)

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ALU

Central to the execute unit is the ALU.

ALU processes data from up to two sources.

One of these is the 8-bit Working register.

The other one can be:


A byte directly from a specified file in the data store. For instance addwf h20, f
Adds the contents of the Working register to the byte in File h20.
A literal byte held as part of the instruction code. For instance
addlw 5 adds the literal 5 to the Working register.

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Outcome of the former case can be directed back to the Data store if destination byte is 0 or in
to the Working register if destination byte is 1.

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Status Register
Associated with the ALU is the Status register which holds three flag bits
used to tell the software something about the outcome from an
instruction.

For instance, if there was a carry-out from an addition or if the out come
is zero.

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Carry Flag
Bit 0 of the status register is the C flag. This primarily holds the carry out from
the last addition operation. Subtraction operations activate this bit as the
complement of the borrow out.
Example:
24-12=12 with borrow = 1
12-24=88 with borrow = 0
C also functions as the input/output bit for the rotate instructions.
The label (R/W ?) Indicates that this bit can be read from or written to and has
an uncertain value on Power on reset; its value does not alter on any other type
of reset.

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Digit Carry Flag


Bit 1 of the status register.

This hold the carry out from the lower nybble to upper nybble; that is
from bit 3 to bit 4.

In the same manner DC holds the complement of the borrow out from
bit 3 to bit 4.
Knowledge of carry activity between upper nybble and lower nybble is
useful when dealing with BCD data.

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Zero Flag
Bit 2 of the Status register is the Z flag. This is set whenever the outcome
of the instruction is zero, otherwise it is cleared.

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Power Down and Time Out


Flags
PD(Power Down) is cleared when the sleep instruction is executed.
The sleep instruction is used to disable the oscillator and place the MCU
in a low current (typically less than 1A) stand by mode.
TO (Time Out) is cleared when Watchdog timer times out.
Both these flags can only be read. They cannot be directly altered by the
program, and they are set to 1 on Power-on reset.

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Register File Page (Bank) select


RP0
All previous status bits are known as flags.

Bit 5 is rather different.


RP0 is used by the programmer to change the state of the processor.

This functions as a switch.

In order to understand this, let us look at the Data store in a little more
detail.

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PIC16F84 Data store


Assume that the PIC16F84 Data store is a filing cabinet, which in this
case has two drawers (banks). In each drawer there are a number of files.
Each file hold 8-bits of data.

There are two type of Files in this cabinet. Some of these files have
special significance. These are known as special-purpose registers. SPRs
are used to control and monitor the state of the microcontroller and its
peripheral devices.

Example:

File 3 is the status register


File 6 is Parallel Port B

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RP0
The remaining files can be given relevant names by the programmer and used
for general-purpose storage.
The PIC16F84 has 68 of these General Purpose Registers (GPRs) addressed from
File h0C through File h4F.

We have seen earlier that only seven bits are reserved for the address in the 14
bit instruction. Which means only 27 addressed can be accessed.
In order to overcome this restriction PIC16F84 uses an 8th bit called Register
Page 0 (RP0). With this bit, we could go up to 256 addresses. When RP0 is 0 then
Bank 0 is enabled for access and when RP0 is 1 then bank 1 is accessed.

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Mirrored GPRs and SPRs


In PIC16F84 all GPRs are mirrored in both banks.

In the newer PIC16F628 16 of GPRs are common to both banks. This is


for faster access. You dont have to switch pages (banks) before
accessing.

Most of the more commonly used SPRs are also mirrored. For example
the status register.

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Indirect Addressing
Normal Direct addressing carries the address of the operand as an integral part of the
instruction.
In embedded computing, where program is stored in ROM this address becomes fixed
which cannot be modified at runtime.
An alternative would be to hold the address in File Select Register (FSR) at File 04 in the
Data store.
Whenever the data store address is b0000000 8-bit contents of the FSR is switched to
the Data stores address bus.

With indirect addressing the operand location is no longer fixed. It is a variable in the File
Select Register (FSR). Therefore the location can be altered in runtime.

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Registers related to indirect


addressing
INDF, File 0
The null address is named INDirect File. b0000000
As INDF is simply used to trigger Indirect addressing.
You cannot store data in INDF.
FSR, File 4

The File Select Register hold the 8-bit Indirect address used when the
instruction actually refers to the null address.

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Timer
All PIC MCU families have at least a basic timer/counter known as Timer0
(TMR0). The read/write TMR0 counter register at File 1 can be clocked from the
outside world via the T0CKI (Timer 0 ClocK In) pin, which is shared with the RA4
Port A pin.
Alternatively the source can be the internal Q4 phase clock which is one quarter
of the crystal frequency.
Either clock source can be frequency divided by a 8-bit Prescaler Counter.

The divide ratio is controlled by the lower three prescaling bits of the Option
register at file h81 labeled PS2:PS1:PS0.

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More on Timer
If the lower 3 bits (PS2:PS1:PS0) were 111 the ratio is then 2PS+1 which means
27+1 = 28 = 256 the counter will increment at f/256 where f is the source
frequency.
The prescaler register can be disconnected by setting the bit 3 of OPTION_REG
to 1. This will give a direct connection between the pulse source and the counter.

Writing to Timer 0 register also zeros the Prescaler register.


With PSA bit set to 1 the prescaler register acts as a postscaler to the Watchdog
timer. Watchdog timer is designed to reset the MCU unless the periodically
preset by the users program with the instruction clrwdt (CLeaR WatchDog
Timer).

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More on Timer
If the prescaler is assigned to the timer then the watchdog circuit will
eventually timeout after approximately 18ms. With PSA set to 1, 2PS *
18ms Watchdog timeouts are required before the processor is reset.

If the watchdog timer times out, TO bit in the status register will be
cleared.

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Registers related to Timer 0


TMR0, File 1

Sometimes known as the Real-Time Clock/Counter (RTCC) is an 8-bit up


counter register that keeps tally of clock events.

It may be preset to any byte value by moving data from W, and read at
any time. When it overflows from hff to h00 it sets the T-ID in the
INTCON (INTerrupt CONtrol) register. This may be used to generate an
interrupt.

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Registers related to Timer 0


OPTION_REG, File h81
Six bits in this register in Bank 1 at File h81 are used in conjunction with
the timer.
PS2, PS1, PS0 to set the prescale ratio 2PS+1
Or postscale ratio 2PS for the watchdog timer.
T0SE (Timer 0 Set Edge) at bit 4 allows the programmer to select the rising (0)
or the falling edge (1) of the clock pulse to increment the counter.

T0CS (Timer 0 Clock Select) at bit 5 allows you to select the internal clock or a
transition at T0CKI pin.

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Program Counter
Occasionally it may be necessary for a program to modify the PC. To
allow for this, the lower byte of the PC is directly accessible as the
Program Counter Low (PCL) byte SPR.

In order to be able to change all 13 bits an additional SPR is required.

The Program Counter LATch High register (PCLATH) will not alter the top
byte of the PC, but when the PCL is written to, the new state of the
PCLATH simultaneously becomes the new top half of the 13-bit PC.

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Program Counter

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Registers used to altering PC


PCL, File 2

The Program Counter Low byte is the lower 8-bits of the PC


PCLATH, File h0A

The Program Counter LATch High byte SPR is a holding register carrying
data destined to be loaded in to the top half of the PC. This occurs at the
same time as the data is written to PCL register, allowing a simultaneous
updating of the complete 13 bits.

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Parallel Input/Output Ports


PIC16F84 has 13 I/O lines. (Compared to 33 on PIC16F877)

Port A has five I/O lines mapped into the Data store address space at File 5.
(RA4,.,RA0)
Port B has 8 I/O lines at File 6. (RB7,,RB0)
Each port can be configured for input or output.
Two registers in Bank 1 (TRISA and TRISB) are the corresponding data
direction registers for Port A and Port B.
TRIS stands for TRIState.

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Registers associated with


parallel I/O
PORTA, File 05
Unseen upper 3 bits are read as zero

TRISA, File h85


1 for input
0 for output
Any type of reset will set the port pins to input.

PORTB, File h85


TRISB, File h86

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Data EEPROM
PIC16F84 has 64 bytes of non-volatile EEPROM memory.

This is not part of the volatile Data store, and is accessed via SPRs as a
peripheral device.

Any byte can be addressed and then read from or written to via the
EEDATA register, as addressed by the EEADR register and controlled by
the EECON1 and EECON2 control file registers.

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Registers related to Data


EEPROM
EEDATA, File h08
Holds data after read action

EECON2, File h89


EEPROM CONtrol 2 is not a physical register and reads as zero.

Or before write action

EEADR, File h09

This address is used as the target for write cycle unlocking


sequence which is implemented by moving h55 followed
directly by hAA into this virtual location.

Address of the target location

EECON1, File h88


Holds the control and status bits that:
Trigger an EEPROM read
Enable a Write action
Trigger an EEPROM Write

Signals a premature end of Write Cycle


Signals a Write cycle has completed.

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Interrupts
Interrupt control register at File h08 holds the mask and the
status bits controlling the response of the MCU interrupts. Operation of
interrupts will be discussed later.

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Thank You

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