MIxed Signal Simulation Lab Manual I M.tech II Sem

I M.
Tech II Semester (VLSI) Mixed Signal Simulation Lab
Exp No: 1
CMOS INVERTER
Aim:
a) To construct the CMOS Inverter in Tanner EDA v13.1 and to do the Transient
Analysis.
b) To analyze the response with appropriate wave forms and to verify the Spice code.
Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.
Department of Electronics and Communication Engineering

Ramachandra College of Engineering: ELURU
I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab
Schematic Diagram:
Fig (a): CMOS Inverter

Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Apr 16 11:43:07 2010
* Design:
adm705-1
* Cell:
Cell3
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\Administrator\Desktop\adm705-1
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out N_2 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out N_2 Vdd N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(Out)
.PRINT TRAN V(N_2)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_1 0 5 0.5
.print dc v(MNMOS_1,Gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

Output responses:
Fig (b): CMOS Inverter Waveforms

DC Analysis:
Result:
The CMOS Inverter is constructed in Tanner EDA v13.1, the spice code is
generated and waveforms are verified.

Exp No: 2
LOGIC GATES
Aim:
a) To construct the following Logic Gates in Tanner EDA v13.1 and to do the
Transient Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.
(i) NAND (ii) NOR (iii) OR (iv) AND (v) Ex-OR (vi) Ex-NOR
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
(i) NAND Gate:
Fig : NAND Gate Schematic

Tanner Spice Code:

* Export time:
Fri Mar 26 11:08:22 2010
* Design:
Prasad
* Cell:
Cell0
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\user\Desktop\705\Prasad
.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Tools
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out In1 N_4 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_4 In Gnd N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out In Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out In1 Vdd N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
.tran 350ns 500ns
.dc lin source VVoltageSource_2 0 5 0.5 sweep lin source VVoltageSource_3 0 5 0.5
.print dc v(MPMOS_1,Gnd)
.end

Output responses:
INPUT A
INPUT B
OUTPUT
Fig : NAND Gate Waveforms

(ii) NOR Gate:
Fig :NOR Gate Schematic

Tanner Spice Code:

* Export time:
Fri Mar 26 12:26:28 2010
* Design:
Prasad
* Cell:
Cell3
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out In1 Gnd N_2 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out In Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_4 In Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out In1 N_4 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
.tran 350ns 500ns
.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5
.print dc v(MPMOS_2,gnd)
.end

Output responses:
Fig : NOR Gate Waveforms

(iii) AND Gate:
Fig : AND Gate Schematic
Tanner Spice Code:

* Export time:
Fri Mar 26 11:32:44 2010
* Design:
Prasad
* Cell:
Cell1

* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_4 In1 N_2 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MNMOS_3 Out N_4 Gnd N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MPMOS_2 N_4 In1 Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
.tran 350ns 500ns
.print dc v(MPMOS_3,gnd)
.end

Output responses:
Fig : AND Gate Waveforms


Layout Diagram of AND gate:

Layout Net list of AND:
* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: Layout1
* Cell: Core Version 1.01
* Extract Definition File: lights.ext
* Extract Date and Time: 07/27/2010 - 09:56
.include lights.md
* NODE NAME ALIASES
*
1 = Vdd (-50 , 4)
*
1 = U1/NAND2C_1/Vdd (0 , 70)
*
1 = U1/NAND2C_2/Vdd (34 , 70)
*
2 = Gnd (41 , 4)
*
2 = U1/NAND2C_1/Gnd (0 , 12)
*
2 = U1/NAND2C_2/Gnd (34 , 12)
*
3 = Out (49 , 82.5)
*
3 = U1/NAND2C_2/Out1 (19 , 36)
*
4 = a (-50 , 82.5)
*
4 = U1/NAND2C_1/A (-31 , 54)
*
5 = U1/NAND2C_1/Out1 (-15 , 36)
*
5 = U1/NAND2C_2/A (3 , 54)
*
5 = U1/NAND2C_2/B (11 , 47)
*
6 = b (-50 , 4.5)
*
6 = U1/NAND2C_1/B (-23 , 47)
*
7 = U1/NAND2C_2/Out2 (27 , 38)
*
8 = U1/NAND2C_1/Out2 (-7 , 38)
M1 Vdd U1/NAND2C_1/Out1 Out Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M2 Out U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M3 U1/NAND2C_2/Out2 Out Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p
PS=34u
M4 Vdd b U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M5 U1/NAND2C_1/Out1 a Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M6 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p
PD=68u AS=84p PS=34u
M7 Gnd U1/NAND2C_1/Out1 10 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u


M8 10 U1/NAND2C_1/Out1 Out Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M9 U1/NAND2C_2/Out2 Out Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p
PS=47u
M10 Gnd b 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M11 9 a U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M12 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u AD=148p
* Total Nodes: 10
* Total Elements: 12
* Total Number of Shorted Elements not written to the SPICE file: 4
* Output Generation Elapsed Time: 0.016 sec
* Total Extract Elapsed Time: 2.328 sec
.END

(iv) OR Gate:
Fig : OR Gate Schematic

Tanner Spice Code:

* Export time:
Fri Mar 26 12:18:24 2010
* Design:
Prasad
* Cell:
Cell2
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Root path:
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_4 In1 Gnd N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
MPMOS_2 N_4 In1 N_2 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
.tran 350ns 500ns
.print dc v(MNMOS_3,gnd)
.end

Output responses:
Fig : OR Gate Waveforms

Layout Diagram of OR Gate:

OR Layout Net List:

* TDB File: Layout1
.include lights.md
* NODE NAME ALIASES
*
1 = U1/NAND2C_3/Out2 (44 , 46)
*
2 = a (-67 , 90.5)
*
2 = U1/NAND2C_1/A (-48 , 62)
*
2 = U1/NAND2C_1/B (-40 , 55)
*
3 = U1/NAND2C_1/Out1 (-32 , 44)
*
3 = U1/NAND2C_3/A (20 , 62)
*
4 = b (-67 , 4.5)
*
4 = U1/NAND2C_2/A (-14 , 62)
*
4 = U1/NAND2C_2/B (-6 , 55)
*
5 = U1/NAND2C_2/Out2 (10 , 46)
*
6 = U1/NAND2C_1/Out2 (-24 , 46)
*
7 = Out (66 , 90.5)
*
7 = U1/NAND2C_3/Out1 (36 , 44)
*
8 = Vdd (-67 , 4)
*
8 = U1/NAND2C_1/Vdd (-17 , 78)
*
8 = U1/NAND2C_2/Vdd (17 , 78)
*
8 = U1/NAND2C_3/Vdd (17 , 78)
*
11 = Gnd (58 , 4)
*
11 = U1/NAND2C_1/Gnd (-17 , 20)
*
11 = U1/NAND2C_2/Gnd (17 , 20)
*
11 = U1/NAND2C_3/Gnd (17 , 20)
*
12 = U1/NAND2C_2/Out1 (2 , 44)
*
12 = U1/NAND2C_3/B (28 , 55)
M1 Vdd U1/NAND2C_2/Out1 Out Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M2 U1/NAND2C_3/Out2 Out Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p
PS=34u
M3 U1/NAND2C_3/Out2 Out Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p
PS=47u
M4 Out U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u


M5 Vdd b U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M6 U1/NAND2C_2/Out1 b Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M8 Vdd a U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M9 U1/NAND2C_1/Out1 a Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
PS=30u
M12 13 U1/NAND2C_1/Out1 Out Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M13 Gnd b 10 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M14 10 b U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M16 Gnd a 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M17 9 a U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
* Total Nodes: 13
.END

(v) Ex-OR Gate:
Fig : Ex-OR Gate Schematic

Tanner Spice Code:

*-------- Devices: SPICE.ORDER > 0 -------MNMOS_3 N_2 N_3 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_4 N_3 In2 Gnd N_18 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MNMOS_6 N_7 In1 N_2 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
PD=6.8u
MNMOS_2 N_7 N_8 N_5 N_15 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_9 N_8 Vdd N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MPMOS_3 N_7 In1 N_9 N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MPMOS_5 N_7 N_3 N_9 N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
PD=6.8u
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(Out)
.tran 350ns 500ns
.end

Output responses:
INPUT A
INPUT B
OUTPUT
Fig : Ex-OR Gate Waveforms

(vi) Ex-NOR Gate:
Fig : Ex-NOR Gate Schematic

Tanner Spice Code:

*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_26 In1 Gnd N_15 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out N_26 N_4 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_19 N_14 Gnd N_11 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
PD=6.8u
MNMOS_6 Out In1 N_19 N_9 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
PD=6.8u
MPMOS_3 Out In1 N_3 N_6 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
MPMOS_5 Out N_14 N_3 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
PD=6.8u
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(Out)
.tran 350ns 500ns
.end

Output responses:
INPUT A
INPUT B
OUTPUT
Fig : Ex-NOR Gate Waveforms
Result:
The Logic Gates are constructed in Tanner EDA v13.1, the spice code is
generated and wave forms are verified.

Exp No: 3
HALF ADDER
Aim:
a) To construct the Half Adder in Tanner EDA v13.1 and to do the Transient
Analysis.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig (a): Half Adder Schematic
Tanner Spice Code:

* Export time:
Fri Apr 16 11:24:00 2010
* Design:
adm705-1

* Cell:
Cell2
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\Administrator\Desktop\adm705-1

*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt NAND2C A B Out1 Out2 Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM
* Revision: 2
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u


MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt XNOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XNOR2 / View: Main / Page:
* Info: 2 Input NOR
* Date: 7/18/2008 3:58:48 AM
* Revision: 4
*-------- Devices: SPICE.ORDER > 0 -------MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM5p 3 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
PD=6.8u
MM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt XOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XOR2 / View: Main / Page:
* Info: 2 Input NOR
* Date: 7/18/2008 1:30:51 AM
* Revision: 3
*-------- Devices: SPICE.ORDER == 0 -------XXinv N_1 Out Gnd Vdd INV

XXxnor A B N_1 Gnd Vdd XNOR2
.ends

*-------- Devices: SPICE.ORDER == 0 -------XINV_1 N_1 carry Gnd Vdd INV
XNAND2C_1 In1 In2 N_1 N_2 Gnd Vdd NAND2C
XXOR2_1 In1 In2 sum Gnd Vdd XOR2
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_3 Vdd Gnd DC 5
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(carry)
.PRINT TRAN V(sum)
.tran 350ns 500ns
.print dc v(XINV_1,GND)
.print dc v(XXOR2_1,GND)
.end

Output responses:
Result:
The Half Adder is constructed in Tanner EDA v13.1, the spice code is generated and
wave forms are verified.

Exp No: 4
FULL ADDER
Aim:
a) To construct the Full Adder in Tanner EDA v13.1 and to do the Transient
Analysis.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig (a): Full Adder Schematic1
Fig (b): Full Adder Schematic2

Tanner Spice Code:

*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: INV / View: Main / Page:
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
* Date: 6/14/2007 1:47:11 AM
* Revision: 2
PD=6.8u
PD=6.8u
PD=6.8u
.ends
.subckt NAND3C A B C Out1 Out2 Gnd Vdd
* Designed by: Author
* Organization: Organization

* Info: Info
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out1 C 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 2 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
PD=6.8u
PD=6.8u
MP3 Out1 C Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
PD=6.8u
.ends
.subckt XNOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XNOR2 / View: Main / Page:
* Info: 2 Input NOR
* Date: 7/18/2008 3:58:48 AM
* Revision: 4
*-------- Devices: SPICE.ORDER > 0 -------MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
PD=6.8u
MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
PD=6.8u
MM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends


.subckt XOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XOR2 / View: Main / Page:
* Info: 2 Input NOR
* Date: 7/18/2008 1:30:51 AM
* Revision: 3
*-------- Devices: SPICE.ORDER == 0 -------XXinv N_1 Out Gnd Vdd INV
XXxnor A B N_1 Gnd Vdd XNOR2
.ends

*-------- Devices: SPICE.ORDER == 0 -------XXOR2_2 N_8 In3 sum Gnd Vdd XOR2
XNAND3C_1 N_1 N_2 N_3 carry N_4 Gnd Vdd NAND3C
XXOR2_1 In1 In2 N_8 Gnd Vdd XOR2
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(In3)
.PRINT TRAN V(sum)
.PRINT TRAN V(carry)
.tran 350ns 500ns
.dc lin source VVOLTAGESOURCE_1 0 5 0.5 sweep lin source VVOLTAGESOURCE_2 0
5 0.5 sweep lin source VVOLTAGESOURCE_3 0 5 0.5
.print dc v(XXOR2_2,GND)
.print dc v(XXOR2_2,GND) v(XNAND3C_1,GND)
.end

Output responses:
INPUT V(A)
INPUT
V(B)
INPUT V(C)
OUTPUT V(SUM)
OUTPUT V(CARRY)
Fig (b): Full Adder wave forms
Layout Diagram of Full adder:

Layout Net list:

* TDB File: Layout1
.include lights.md
* NODE NAME ALIASES

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1 = CARRY (125 , 142.5)

1 = U2/NAND2C_9/Out1 (87 , 96)
2 = SUM (125 , 56.5)
2 = U2/NAND2C_8/Out1 (53 , 96)
3 = U2/NAND2C_7/Out1 (19 , 96)
3 = U2/NAND2C_8/B (45 , 107)
4 = U2/NAND2C_9/Out2 (95 , 98)
5 = U2/NAND2C_8/Out2 (61 , 98)
6 = U2/NAND2C_7/Out2 (27 , 98)
10 = U2/NAND2C_6/Out1 (-15 , 96)
10 = U2/NAND2C_8/A (37 , 114)
11 = U2/NAND2C_5/Out1 (-49 , 96)
11 = U2/NAND2C_6/B (-23 , 107)
11 = U2/NAND2C_7/A (3 , 114)
11 = U2/NAND2C_9/B (79 , 107)
12 = U2/NAND2C_5/A (-65 , 114)
12 = U2/NAND2C_6/A (-31 , 114)
12 = U3/NAND2C_4/Out1 (53 , -22)
13 = U2/NAND2C_6/Out2 (-7 , 98)
14 = U2/NAND2C_5/Out2 (-41 , 98)
17 = U3/NAND2C_3/Out1 (19 , -22)
17 = U3/NAND2C_4/B (45 , -11)
18 = U3/NAND2C_4/Out2 (61 , -20)
19 = U3/NAND2C_3/Out2 (27 , -20)
22 = Vdd (-100 , -62)
22 = U2/A/Vdd (-68 , 130)
22 = U2/NAND2C_5/Vdd (-34 , 130)
22 = U2/NAND2C_6/Vdd (-34 , 130)
22 = U2/NAND2C_7/Vdd (34 , 130)
22 = U2/NAND2C_8/Vdd (68 , 130)
22 = U2/NAND2C_9/Vdd (68 , 130)
22 = U3/Cin/Vdd (-34 , 12)
22 = U3/NAND2C_1/Vdd (-42 , 12)
22 = U3/NAND2C_2/Vdd (-34 , 12)
22 = U3/NAND2C_3/Vdd (34 , 12)
22 = U3/NAND2C_4/Vdd (68 , 12)
23 = Gnd (109 , -62)
23 = U2/A/Gnd (-68 , 72)
23 = U2/NAND2C_5/Gnd (-34 , 72)
23 = U2/NAND2C_6/Gnd (-34 , 72)
23 = U2/NAND2C_7/Gnd (34 , 72)
23 = U2/NAND2C_8/Gnd (68 , 72)
23 = U2/NAND2C_9/Gnd (68 , 72)
23 = U3/Cin/Gnd (-34 , -46)
23 = U3/NAND2C_1/Gnd (-42 , -46)
23 = U3/NAND2C_2/Gnd (-34 , -46)
23 = U3/NAND2C_3/Gnd (34 , -46)

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
23 = U3/NAND2C_4/Gnd (68 , -46)

24 = U2/NAND2C_9/A (71 , 114)
24 = U3/NAND2C_1/Out1 (-57 , -22)
24 = U3/NAND2C_2/B (-23 , -11)
24 = U3/NAND2C_3/A (3 , -4)
25 = A (-100 , 142.5)
25 = U3/NAND2C_1/A (-73 , -4)
25 = U3/NAND2C_2/A (-31 , -4)
26 = Cin (-100 , -61.5)
26 = U2/NAND2C_5/B (-57 , 107)
26 = U2/NAND2C_7/B (11 , 107)
27 = B (-100 , 32.5)
27 = U3/NAND2C_1/B (-65 , -11)
27 = U3/NAND2C_3/B (11 , -11)
28 = U3/NAND2C_2/Out1 (-15 , -22)
28 = U3/NAND2C_4/A (37 , -4)
29 = U3/NAND2C_2/Out2 (-7 , -20)
30 = U3/NAND2C_1/Out2 (-49 , -20)
M1 Vdd U2/NAND2C_5/Out1 CARRY Vdd PMOS L=2u W=28u AD=84p PD=34u

AS=84p PS=34u
M2 CARRY U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M3 U2/NAND2C_9/Out2 CARRY Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M4 Vdd U2/NAND2C_7/Out1 SUM Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M5 SUM U2/NAND2C_6/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M6 U2/NAND2C_8/Out2 SUM Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p
PS=34u
M7 Vdd Cin U2/NAND2C_7/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
PS=30u
M11 9 U2/NAND2C_9/A CARRY Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M12 U2/NAND2C_9/Out2 CARRY Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
PS=30u
M14 8 U2/NAND2C_6/Out1 SUM Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u

M15 U2/NAND2C_8/Out2 SUM Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M16 Gnd Cin 7 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M17 7 U2/NAND2C_5/Out1 U2/NAND2C_7/Out1 Gnd NMOS L=2u W=28u AD=28p
M19 Vdd U2/NAND2C_5/Out1 U2/NAND2C_6/Out1 Vdd PMOS L=2u W=28u AD=84p
M20 U2/NAND2C_6/Out1 U2/NAND2C_5/A Vdd Vdd PMOS L=2u W=28u AD=84p
M22 Vdd Cin U2/NAND2C_5/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
PS=30u
M26 16 U2/NAND2C_5/A U2/NAND2C_6/Out1 Gnd NMOS L=2u W=28u AD=28p
M28 Gnd Cin 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M31 Vdd U3/NAND2C_3/Out1 U2/NAND2C_5/A Vdd PMOS L=2u W=28u AD=84p
M32 U2/NAND2C_5/A U3/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p
M34 Vdd B U3/NAND2C_3/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
M35 U3/NAND2C_3/Out1 U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=84p M36
U3/NAND2C_3/Out2 U3/NAND2C_3/Out1 Vdd Vdd PMOS L=2u W=28u M37 Gnd
U3/NAND2C_3/Out1 21 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
M38 21 U3/NAND2C_2/Out1 U2/NAND2C_5/A Gnd NMOS L=2u W=28u AD=28p
M39 U3/NAND2C_4/Out2 U2/NAND2C_5/A Gnd Gnd NMOS L=2u W=28u AD=148p
M40 Gnd B 20 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M43 Vdd U2/NAND2C_9/A U3/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p
M44 U3/NAND2C_2/Out1 A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M46 Vdd B U2/NAND2C_9/A Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M47 U2/NAND2C_9/A A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M49 Gnd U2/NAND2C_9/A 32 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u
M50 32 A U3/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M52 Gnd B 31 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M53 31 A U2/NAND2C_9/A Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p M54
U3/NAND2C_1/Out2 U2/NAND2C_9/A Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
* Total Nodes: 32
.END
Result:
The Full Adder is constructed in Tanner EDA v13.1, the spice code is generated and
wave forms are verified

Exp No: 5
D - FLIP FLOP
Aim:
a) To construct the D-Flip flop in Tanner EDA v13.1 and to do the Transient
Analysis.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig : D - Flip Flop Schematic

Tanner Spice Code:

* Export time:
Fri Apr 23 10:38:02 2010
* Design:
Prasad1
* Cell:
Cell1
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\Administrator\Desktop\Prasad1
*************** Subcircuits *****************
* Date: 6/14/2007 1:47:11 AM
* Revision: 2
PD=6.8u
PD=6.8u
PD=6.8u
.ends


*-------- Devices: SPICE.ORDER == 0 -------XNAND2C_1 D Clk N_5 N_8 Gnd Vdd NAND2C
XNAND2C_2 Clk N_1 N_3 N_7 Gnd Vdd NAND2C
XNAND2C_3 N_5 QBar Q N_6 Gnd Vdd NAND2C
XNAND2C_4 Q N_3 QBar N_4 Gnd Vdd NAND2C
XNAND2C_5 D D N_1 N_2 Gnd Vdd NAND2C
VVoltageSource_2 Clk Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_1 D Gnd BIT({0100101111} )
.PRINT TRAN V(D)
.PRINT TRAN V(Clk)
.PRINT TRAN V(Q)
.PRINT TRAN V(QBar)
.tran 350ns 500ns
.dc lin source VVoltageSource_2 0 5 0.5
.print dc v(Q,Gnd)
.end

Output responses:
Fig (b): D-Flip flop waveforms

Layout Diagram:
Layout Net list:

* TDB File: Layout1
.include lights.md
* NODE NAME ALIASES
*
1 = U1/NAND2C_5/Out2 (78 , 54)
*
2 = U1/NAND2C_4/Out2 (44 , 54)
*
3 = U1/NAND2C_3/Out2 (10 , 54)
*
6 = q (100 , 12.5)
*
6 = U1/NAND2C_3/Out1 (2 , 52)
*
6 = U1/NAND2C_4/A (20 , 70)
*
7 = Vdd (-101 , 4)
*
7 = U1/NAND2C_1/Vdd (-51 , 86)
*
7 = U1/NAND2C_2/Vdd (-17 , 86)
*
7 = U1/NAND2C_3/Vdd (-17 , 86)
*
7 = U1/NAND2C_4/Vdd (51 , 86)
*
7 = U1/NAND2C_5/Vdd (85 , 86)
*
8 = d (-101 , 106.5)
*
8 = U1/NAND2C_1/A (-82 , 70)
*
8 = U1/NAND2C_5/A (54 , 70)
*
8 = U1/NAND2C_5/B (62 , 63)
*
9 = U1/NAND2C_1/Out1 (-66 , 52)
*
9 = U1/NAND2C_3/A (-14 , 70)
*
10 = U1/NAND2C_2/Out1 (-32 , 52)
*
10 = U1/NAND2C_4/B (28 , 63)
*
11 = U1/NAND2C_2/B (-40 , 63)
*
11 = U1/NAND2C_5/Out1 (70 , 52)
*
12 = clk (-101 , 4.5)
*
12 = U1/NAND2C_1/B (-74 , 63)
*
12 = U1/NAND2C_2/A (-48 , 70)
*
13 = U1/NAND2C_2/Out2 (-24 , 54)
*
14 = U1/NAND2C_1/Out2 (-58 , 54)
*
17 = Gnd (92 , 4)
*
17 = U1/NAND2C_1/Gnd (-51 , 28)
*
17 = U1/NAND2C_2/Gnd (-17 , 28)
*
17 = U1/NAND2C_3/Gnd (-17 , 28)
*
17 = U1/NAND2C_4/Gnd (51 , 28)
*
17 = U1/NAND2C_5/Gnd (85 , 28)
*
18 = qbar (100 , 98.5)
*
18 = U1/NAND2C_3/B (-6 , 63)
*
18 = U1/NAND2C_4/Out1 (36 , 52)


M1 Vdd d U1/NAND2C_2/B Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u
M2 U1/NAND2C_2/B d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u
M3 U1/NAND2C_5/Out2 U1/NAND2C_2/B Vdd Vdd PMOS L=2u W=28u AD=148p
M4 Vdd U1/NAND2C_2/Out1 qbar Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M5 qbar q Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u
M6 U1/NAND2C_4/Out2 qbar Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p
PS=34u
M7 Vdd qbar q Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u
M8 U1/NAND2C_3/Out2 q Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p
PS=34u
M9 Gnd d 5 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M10 5 d U1/NAND2C_2/B Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u
M11 U1/NAND2C_5/Out2 U1/NAND2C_2/B Gnd Gnd NMOS L=2u W=28u AD=148p
PS=30u
M13 4 q qbar Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u
M14 U1/NAND2C_4/Out2 qbar Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M15 U1/NAND2C_3/Out2 q Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p
PS=47u
M16 q U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M17 Vdd U1/NAND2C_2/B U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p
M18 U1/NAND2C_2/Out1 clk Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M20 Vdd clk U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M21 U1/NAND2C_1/Out1 d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M23 Gnd qbar 19 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M24 19 U1/NAND2C_1/Out1 q Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M25 Gnd U1/NAND2C_2/B 16 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u
M26 16 clk U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u

M28 Gnd clk 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M29 15 d U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
* Total Nodes: 19
.END
Result:
The D-Flip flop is constructed in Tanner EDA v13.1, the spice code is generated and
waveforms are verified.

Exp No: 6
CURRENT MIRROR
Aim:
a) To construct the Current Mirror in Tanner EDA v13.1 and to do the
Voltage Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice
code of the designed circuit.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig (a): Current Mirror Schematic
Tanner Spice Code:


* Export time:
Fri Jun 11 12:15:48 2010
* Design:
msl
* Cell:
Cell8
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\user11\Desktop\msl
.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib " TT
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_2 Out N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_1 N_2 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 Vdd Vdd N_2 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_4 In Vdd Out Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_2 In Gnd SIN(2.5 500m 500k 0 0 0)
.PRINT TRAN V(Out)
.PRINT TRAN V(In)
*.tran 5ns 500ns
.dc lin source vvoltagesource_2 0 5 1
.print dc v(n_2,gnd)
.end
Output responses:

NMOS_3_S
NMOS_1_S
Fig (b): Current Mirror Waveforms
Result:
The Current Mirror is constructed in Tanner EDA v13.1, the spice code is
generated and wave forms are verified

Exp No: 7
DIFFERENTIAL AMPLIFIER
Aim:
a) To construct the differential amplifier in Tanner EDA v13.1 and to do the
voltage analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice
code of the designed circuit.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig(a): Differential Amplifier Schematic

Tanner Spice Code:

*-------- Devices: SPICE.ORDER > 0 -------RResistor_1 Vdd N_5 R=50
RResistor_2 Vdd N_7 R=50
PD=6.8u
PD=6.8u
VVoltageSource_3 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_5 Gnd pos_PortNotFound_0 PULSE(0 5 0 5n 5n 95n 200n)
ICurrentSource_1 N_3 Gnd DC 5u
.PRINT TRAN V(N_2)
.PRINT TRAN V(N_7)
.PRINT TRAN V(N_1)
.PRINT TRAN V(N_5)
*.tran 5ns 500ns
.dc lin source vvoltagesource_3 -3 3 1
.print dc i(mnmos_2,n_7) i(mnmos_1,n_5)
.end

Output responses:
Fig (b): Differential Amplifier Waveforms
Result:
The differential amplifier is constructed in Tanner EDA v13.1, the spice code
is generated and wave forms are verified.

Exp No: 8
OPERATIONAL AMPLIFIER
Aim:
a) To construct the Operational Amplifier in Tanner EDA v13.1 and to do the
AC analysis.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig (a): Operational Amplifier Schematic

Tanner Spice Code:

*-------- Devices: SPICE.ORDER > 0 -------CCapacitor_1 N_3 Out 1p
CCapacitor_2 Out Gnd 1p
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
PD=6.8u
VVoltageSource_2 N_6 Gnd DC 5
VVoltageSource_4 N_5 N_6 DC 0 AC 1 0
*.tran 5ns 500ns
.ac lin 10 0 10
.print ac vm(out,gnd) vp(out,gnd)
.end

Output responses:
VP(OUT)
Vdb(OUT)
V(OUT)
Fig (b): Operational Amplifier Waveforms
Result:
The Operational Amplifier is constructed in Tanner EDA v13.1, the spice
code is generated and wave forms are verified.

Exp No: 09
TRANS CONDUCTANCE AMPLIFIER
Aim:
a) To construct the Trans Conductance Amplifier in Tanner EDA v13.1 and to
do the DC analysis.
Tools used:
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

Schematic Diagram:
Fig (a): Trans Conductance Amplifier Schematic

Tanner Spice Code:

*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_1 N_2 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out N_4 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_3 N_5 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_1 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_3 N_5 Gnd DC 700m
VVoltageSource_4 Out Gnd DC 2.5
VVoltageSource_5 N_4 N_2 DC 0
.dc lin source VVOLTAGESOURCE_5 -1 1 0.01
.print dc id(MNMOS_1) id(MNMOS_2)
.print dc i(vvoltagesource_4,out)
*.tran 350ns 500ns
.end

Output responses:
i(VPMOS_1)
i1(VNMOS_3)
i1(VNMOS_2)
Fig (b) Trans Conductance Amplifier Waveforms
Result:
The Trans Conductance Amplifier is constructed in Tanner EDA v13.1, the spice
code is generated and wave forms are verified.

Setup Guide for Taneer Tools V13.0

1.
Extract the Taneer Tools

Right Click Extract Here
2.
Go to Taneer Tools_V13_LND
3.
Click Setup
4.
Setup will Continue without any Modifications
5.
Click Finish
6.
Select only when License manager shows the message select local License
7.
Go on to Next to Continue When the Message Taneer Tools are successfully installed
8.
Go to Taneer Tools_V13_LND (where is been Extracted)
9.
Go to Legend Folder Copy the Following
TannerTools_13_Calculator
TannerTools_13_Corrector
10.
Go to Below Steps C: Program Files: Taneer Eda:
11.
Paste the Selected Items
12.
Double Click on TannerTools_13_Corrector
13.
After receiving message Press any Key
14.
Go to Below Steps: C: Program Files: Taneer Eda:
15.
Double Click on TannerTools_13_Calculator
16.
Go to Start: Programs: Taneer Eda: Utitlities: Computer Id: Copy the Ethernet
Value(not available copy IP Address)
17.
Write down the Copied value into TannerTools_13_Calculator Editor
18.
After receiving the License (Lservrc) file press any key
19.
Go to C: Program Files: Taneer Eda:
20.
Paste the Lservrc file in following Paths
copy the Lservrc file
1)
C: Program Files: Taneer Eda: Taneer Tolls V13.0:
2)
C: Program Files: Taneer Eda: Taneer Tolls V13.0: px:

WIN 32.2-I686: bin:
3)
C: Program Files: Taneer Eda: Taneer Tolls V13.0: VerilogA: Vacomp:

bin:
21.
Close all opened Files
22.
Click on L-Edit shortcut on Desktop


23.
Click Setup on Dailog Box
24.
Continue to Next steps without any Modifications
25.
Click finish button
26.
Setup successfully Installed

INSTRUCTION MANUAL
DESIGN AND SIMULATION OF INVERTER WITH

TANNER TOOL
Under The Guidance

of
Dr. Manisha Pattanaik
Designed by
Basanta Bhowmik
Jayveer Singh Bhadauriya
Contents:
Schematic design..03-19
Pre layout simulation..20-26
Layout design.27-50
Design rule check(DRC).51-53
Extraction54-56
Layout Vs schematic(LVS).57-62
Post layout simulation63-65
Generation of GDS II file(MASK)..66-72
Appendix .73-76
MOSIS Design rule .73
Extracted file/Layout Netlist74
GDSII Export file.....................75
GDSII Import file..76
Schematic design of Inverter

What is schematic Design: There are many phases or progressions of a design. A common term you will
hear when working with a Designer is Schematic Design. This phase is early in the design process.
Schematic Design establishes the general scope, conceptual ideas, the scale and relationship of the
various program elements. The primary objective of schematic design is to arrive at a clearly defined
feasible concept based on the most promising design solutions.
Opening S-edit platform:

First of all double click on the icon of s-edit on the desktop
or
Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> S-Edit v 13.0
A new window will open:
Go to >>file >> New >> New Design

Select New Design
One dialog box will appear

Design Name : Give the name your design as you wish
Create a Folder : Give the path where you want to save the S-Edit Files.
Then Click on OK
Now to add libraries in your work click on Add , left on the library window.
Give the path where Libraries are stored . As for example
C:\ Documents and Settings\ Bhowmik.IIIT-3AC288AD0A\ My Documents\ Tanner EDA\ Tanner
Tools v13.0\ Libraries\ All\ All.tanner
Now to create new cell

Go to cell menu >> New view -Select New view
The new cell will appear like below:

Design = your design name
Cell = cell no. ( cell no you can change but your design name inv will be same for different cell.
Design name should be changed only when you are going to design another circuit)
View type = schematic
Interface name = by default
View name = by default
Then press OK.
Then a cell will be appeared where we can draw the schematic of any circuit .
In the black window you have seen some white bubble arranged in specific order. This is called
grid. You can change grid distance by clicking on black screen and then scroll the mouse.
If you want your screen big enough for design space , then you can close the Find & command
window. You can again bring these window from view menu bar.
To make any circuit schematic .

for example inverter
a) Go to >>libraries & click on device then all device will be open.
b) Select any device

e.g. :- NMOSDevice, then click on , instance
(then the dailog box instance cell will appear.)
In instance cell
You can change the values of various device parameters according to your
requirements.
Go to properties >> change the parameter values as your requirement.
Now before clicking DONE you have to DRAG the selected device into the cell
and drop it where you want it to FIX .
Then click DONE or press ESC.
Similarly you can DRAG & DROP any device into the cell for draw your schematic circuit.
For inverter we need another Pmos.
Now connect two device with wire.

Go to tool bar and select wire.
Similarly to give input & output port in the circuit , select input port that shown by red ellipse.
Now you can give Port name as you wish in the dailog box.
Then click OK
Similarly give Output Port name.

NOTE : you can rotate the port (short cut key R).
Now, after completed these steps, you should give the supply (VDD) & ground (GND).
For that Go to liberaries >> MISC >>Select VDD or GND
Now you have to create a source of VDD. For that go to libraries >>spice_element >> and then
select voltage source of type DC . you can give any value in vdd .lets take vdd =5v.
By doing all the above steps you have completed schematic of Inverter
Pre layout simulation

After schematic design you have to check whether your design match with the
specification required or not . Thats why you need to simulate the design which
is called Pre layout simulation.
For simulation go to>> tools>> T-spice>> ok
A T-spice window will open.

Then click on the bar shown by red ellipse
A T-spice command Tool dialog box will open as shown beow.
On the T-spice command you can see in the left hand side
Analysis,
Current source
Files
Initialization,
Output
Settings
Table
Voltage source
Optimization
Lets start doing transient analysis of Inverter.

Step 1 : You have to include TSMC 0.18 m Technology file .
For that
Go to >> T-spice command tool >> Files >> Include >> browse TSMC .18m files
>> Insert command.
C:\ Documents and Settings\ Bhowmik.IIIT-3AC288AD0A\ Desktop\ TSMC
0.18um\ MODEL_0.18.md
File is included shown by highlight.
Step2 : Then to give Input

T-spice command tool >> Voltage source >> select type of input you want to give(lets
take bit) >> Insert command
Step 3: Analysis
T-spice command tool >> Analysis >> select type of analysis you want to give(lets take
transient) >> Insert command
step 4: Output
T-spice command tool >> Output >> which output you want to see >> Insert
Command
The total spice netlist will come like this.
Now save it .
Then Run by clicking red ellipse shown on left above corner.
Output of Pre layout simulation of Inverter
Layout Design
What is Layout Design: A layout-design of an IC refers essentially to the 3-dimensional character of the
elements and interconnections of an IC. There is a continuing need for the creation of new layoutdesigns which reduce the dimensions of existing integrated circuits and simultaneously increase their
functions.
Procedure of Layout Design in 0.18m CMOS Technology(MOSIS>>

Mamin08)
Opening L-edit platform:
First of all double click on the icon of L-edit on the desktop
or
Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> L-Edit v 13.0
A window will come like below.
We will start the layout of Inverter with
NMOS
PMOS
w= 1.5 m L =2.75 m
w= 1.5 m L= 3.50 m
For inverter layout

Go to file>> new.>> select
A dialog box will come as shown in fig
Select layout and then press ok.
A new layout window will open
Carefully observe the Red ellipse which will be frequently used for your Design.
Before starting layout design you have to set the Technology you want to used.
In TSMC .18 m Technology, available Technology are
Charterd
China_hj
Generic0_25 m
Mosis
Orbit
So to set the Technology
Go to >> File >> Replace setup and then select
A dialog box will come.

Click on browse >> Tanner EDA >> Tanner Tools v13.0 >>L-edit and LVS>> TECH >> Mosis >>
mamin08 or mamin12 or or>> press ok
After pressing ok ,A small dialog box will come and it tells you ,Technology are going to be
changes. In that stage press ok.
Lets take in the above set up you set Mosis ->Mamin08 Technology. That means you have to
follow Mosis design rule in your entire design.
Mosis design rule are given in appendix.
Now lets recheck your technology set up.

For that
Go to >> set up >> Design >> then select
In the Set up design layout2 dialog box you have seen there are many technology units.you
can choose any one of them for your design. I have choosen Lambda rule for convenience. Also
for Technology to micron mapping I have taken 1 lambda=0.5 micron . You can choose your
own for better understandig and drawing the design.
In the same way select grid

For design convenience and properly maintain the DRC , I have taken
Major diplayed grid=10 lambda
Minor diplayed grid=1 lambda (You put according to your calculation)
Like that many other parameter you can change thats depends upto you.
Atlast press ok .
Now you properly create the environment for design.
You have two option for any Design .Lets take example of Inverter
First: For inverter design first of all you have to create a PMOS and a NMOSin the same
window.
Or
Second:You can bring a PMOSand NMOS from the Library ,which is already available.
For that Go to Cell >> Instance >> browse the Technology what you are using (e.g
mamin08) >> press ok >> a series of devices which are available in the library will come >>
seect EXT_NMOS or EXT_PMOS >> press ok . The device will come in cell window.
But In the library some standard devices available which are not enough for your requirement
all the time .This is a bad practice.Thats why you need a good practice to Design all the way
from start to end of the Design. We will follow first procedure.
So first of all design a PMOS.
For PMOS you need a N type substrate ,source and drain will be P-type and pollysilicon Gate.
BY default The cell window is P-type. So for design Pmos you need N-substrate that means
Select N-well >> select switch to draging box (left upper corner of the window) >> draw
Then Select P-select >> select switch to draging box (left upper corner of the window) >>
draw
Now Select Active >> select switch to draging box (left upper corner of the window) >>
draw
Now Select Active >> select switch to draging box (left upper corner of the window) >>
draw
In the same way draw Nmos .Here not required p-well because the window is already p-type.
So the procedure is first draw a n-select then then draw the active area and then polysilicon
gate.
After designing Nmos and Pmos you have to connect them . e.g PMOS source and substrate
will be connected to VDD and Nmos source and substrate will be connected to Gnd.
Pmos ,Nmos drain are connected to output and both gate are connected to Input.
For source ,drain ,Vdd and Gnd you have to take Metal 1 layer.
To connect Pmos substrare to Vdd you need N-select and Metal -1 layer
To connect Nmos substrare to Gnd you need P-select and Metal -1 layer
Now connect source and vdd of pMOSby Metal-1 layer
Put active contact of size 2m2 m
Now connect nMOSdrain to pMOSdrain and nMOSsource to Gnd by metal-1 layer.shown by

red ellipse.
Put active contact .
Now Connect both Gate as shown below,To make contact on Polysilicon, you need metal-1
(3m3 m)layer and Poly contact of size (2m2 m)
To give name to input output port, click to Switch to drawing ports as shown below:
After clicking on the Switch to drawing ports, click on that part of the layout where you want
to give name of the port.
As for example to give name Vdd you have to select the Metal-1 layer shown in figure.
After giving name to each port, your layout look like as shown below.
Then save your design.
DESIGN RULE CHECK(DRC)

Design Rule Check (DRC) is the area of Electronic Design Automation (EDA) that determines whether
the physical layout of a particular chip layout satisfies a series of recommended parameters called
Design Rules. Design rule checking is a major step during Physical verification signoff on the design.
Design Rules are a series of parameters provided by semiconductor manufacturers that enable the
designer to verify the correctness of a mask set. Design rules are specific to a particular semiconductor
manufacturing process.
Go to >>setup DRC >> select

One dialog box will come as shown below, check out DRCStandard Rule Set then press OK.
Now run DRC shown by red ellipse.
After running DRC, if there is no error that means your design satisfies Design rule check.
EXTRACT
To verify the functionality and timing of this inverter, you need to extract the spice netlist from the
layout then simulate it. Unfortunately, the netlisting is not working at that moment, but we can still
generate the extracted view from which a netlist can be generated (once we fix the installation).
The extracted view also allows you to run LVS(Layout vs Schematic). This tool (which is also not working
at the moment, probably for the same reason the netlisting is broken) allows you to compare a
schematic and an extracted physical layout to verify that they are equivalent ( i.e. signals are connected
the same way)
To extract, click on setup extract, then a setup extract dialog box will open, check extract
standard rule set if it is not checked and then click on pencil icon as shown below.
After clicking on pencil icon, Setup Extract Standard Rule Set window will open, in that
window give path of Extract Definition File.
Browse >> My document >> Tanner EDA >> Tanner Tools v13.0 >> L edit and LVS>> Tech >>
Mosis >> mamin08.
Note: (check
General -> open output file after extracting and all others are optional .
Output-> Names,Write verbose spice statements,write .End statement
.include mamin08.md file must be included in spice included
Statement. All others are optional.
Subcircuit-> optional.
Then Press OK.
If you not give proper path of Extract definition file then a dialog box will come showing you
I/ O Error cannot open file.
To extract click on EXT toolbar shown by highlighting.

Then warning will come like below.At this stage click on Ignore all.
A extracted file or netlist contaninig device details like connections,aspect ratio ,drain
area,source area, perimeter,and juntion capacitances will come .
Netlist or Extracted file of the inverter shown in appendix.
Layout Vs schematic(LVS)
The Layout Versus Schematic (LVS) is the class of EDA verification software that determines whether a
particular integrated circuit layout corresponds to the original schematic or circuit diagram of the
design.
LVSchecking software recognizes the drawn shapes of the layout that represent the electrical
Components of the circuit, as well as the connections between them. This netlist is compared by the
"LVS" software against a similar schematic or circuit diagram's netlist.
LVSChecking involves :
1. Extraction:
The software program takes a database file containing all the layers drawn to represent the
circuit during layout. It then runs the database through many area based logic operations. Area
based logical operations use polygon areas as inputs and generate output polygon areas from
these operations. These operations are used to define the device recognition layers, the
terminals of these devices, the wiring conductors and via structures, and the locations of pins
(also known as hierarchical connection points).
2. Reduction:
In the time of reduction the software combines the extracted components into series and
parallel combinations if possible and generates a netlist representation of the layout database. A
similar reduction is performed on the "source" Schematic netlist.
3. Comparison:
The extracted layout netlist is then compared to the netlist taken from the circuit schematic. If
the two netlists match, then the circuit passes the LVScheck and a message will come the
circuit are equal. At this point it is said to be "LVSclean .
Opening LVS platform:

First of all double click on the icon of LVS V13.0 on the desktop
or
Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> LVSv 13.0
A new window will come as shown below.
Then go to >>file >> new >> LVSsetup >> ok
Select input.
In the input you have to import Layout netlist and Schematic netlist.
Note: (dont forget to remove .include .md file from both netlist ).
Select output, device parameter, merge device, paracitics,options,performance , the
are basically optional.
After checking click on run verification(shown by red ellipse)
A dialog box verification will come.

In final report a message will shows The circuits are equal. That means your LVS
checking is complete and your layout design perfectly same as schematic of your design.
Post layout simulation

The parasitic capacitances extracted according to how your layout is designed might be critical
in affecting the actual performance of your design. In order to get an idea of how the design
would work from your layout, you should perform a post-layout simulation from the extracted
view. The procedure is identical to that for simulating from the schematic view.
The electrical performance of a full-custom design can be best analyzed by performing a postlayout simulation on the extracted circuit net-list. At this point, the designer should have a
complete mask layout of the intended circuit/ system, and should have passed the DRC and LVS
steps with no violations. The detailed (transistor-level) simulation performed using the extracted
net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics
(such as parasitic capacitances and resistances), and any glitches that may occur due to signal
delay mismatches.
If the results of post-layout simulation are not satisfactory, you should modify some of the
transistor dimensions and/ or the circuit topology, in order to achieve the desired circuit
performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics.
This may require multiple iterations on the design, until the post-layout simulation results satisfy
the original design requirements.
For post layout simulation

Open layout netlist >> rest of the process is same as prelayout simulation.
Output of post layout simulation :
Generation of GDS II file(MASK)
GDS II stream format, common acronym GDSII, is a database file format which is the de facto
industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file
format representing planar geometric shapes, text labels, and other information about the
layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be
used in sharing layouts, transferring artwork between different tools, or creating photomasks.
GDSII is like Gerber for PCBs. It is a format that ASIC Foundries accept for the manufacture of
ASICs/ VLSIs (mainly standard cells).
Alike Gerber, GDSII contains Masks layers (as many as 24 to 30), including Metal top layer(s).
The Term RTL-to-GDSII refers to a design methodology where already in the RTL stage, route
problems, critical placements, Signal Integrity, Crosstalk, and other DRCs are taken under
account to shorten up the "Timing Closure" cycle process.
This is especially true for the new nanometer technologies (below 0.13um)
To generate GDSII file go to >> File >> Export Mask Data >> GDSII >> ok
A Export GDSII dialog box will come . click on the Export button. Shown by red ellipse
If you want log file to save ,then first click on it and give a new name .This is basically
optional.
After Exporting ,a GDSII Export file will come . It will tell you the details of Exporting.
Last of the report something written .
Like below.
Summary:
Export Successful.
Elapsed Time: 0.00 seconds
Then close the layout cell(not layout window) and import GDSII (MASK) file.
For that go to >> File >> Import Mask Data >> GDSII >>ok
Click on the Import.
Press ok
After Importing you will get MASK of your Design.

As for example in the below shows a mask of Inverter
Appendix
MOSIS Design rule

Rule number
RI
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
Description
Active area rules
Minimum active area width
Minimum active area spacing
Polysilicon rules
Minimum poly width
Minimum poly spacing
Minimum gate extension of poly over active
Minimum poly-active edge spacing
(poly outside active area)
Minimum poly-active edge spacing
(poly inside active area)
Metal rules
Minimum metal width
Minimum metal spacing
Contact rules
Poly contact size
Minimum poly contact spacing
Minimum poly contact to poly edge spacing
Minimum poly contact to metal edge spacing
Minimum poly contact to active edge spacing
Active contact size
Minimum active contact spacing
(on the same active region)
Minimum active contact to active edge spacing
Minimum active contact to metal edge spacing
Minimum active contact to poly edge spacing
Minimum active contact spacing
(on different active regions)
Extracted file/ Netlist of Layout
R
3
3
2
2
2
1
3
3
3
2
2
1
1
3
2
2
1
1
3
6
* TDB File: E:\ layout\ layout\ Layout2.tdb
* Cell: Cell0 Version 1.20
* Extract Definition File: C:\ Documents and Settings\ Bhowmik.IIIT-3AC288AD0A\ My
Documents\ Tanner EDA\ Tanner Tools v13.0\ L-Edit and LVS\ Tech\ Mosis\ mamin08.ext
* Extract Date and Time: 08/ 28/ 2011 - 19:26
.include mamin08.md
*
*
*
*
*
*
*
*
*
Warning: Layers with Unassigned AREA Capacitance.

<PMOSCapacitor>
<NMOSCapacitor>
<PCAP Capacitor>
Warning: Layers with Unassigned FRINGE Capacitance.
<PMOSCapacitor>
<Pad Comment>
<NMOSCapacitor>
<PCAP Capacitor>
M1 Out In Gnd Gnd NMOSL=1.5u W=2.75u AD=12.375p PD=14.5u AS=11.6875p

PS=14u $ (25 7 28 12.5)
M2 Out In Vdd Vdd PMOSL=1.5u W=3.5u AD=14.875p PD=15.5u AS=15.75p PS=16u $
(25 27.5 28 34.5)
* Total Nodes: 4
* Total Elements: 2
.END
GDSII Export File

GDSII Export...
TDB File: E:\ layout\ layout\ Layout2.tdb
GDSII File: E:\ layout\ layout\ Layout2.gds
Option Settings:
Do not export hidden objects: ON
Overwrite data type on export: ON
Calculate MOSISchecksum: OFF
Check for self-intersecting polygons and wires: OFF
Write XrefCells as links: OFF
Preserve case of cell names: ON
Restrict cell names to 32 characters.
All cells are being exported
Use custom GDSII units:
1 database unit = 0.0005 microns,
1 database unit = 0.001 user units.
Fracture polygons: OFF
Manufacturing grid for circle and curve approximation: 0.001 Lambda
All ports with port boxes will be converted to point ports
Checking XrefCell links ...
Checking GDSII Numbers ...
Checking for Hidden Layers and Objects ...
Writing actual GDSII data ...
Completed writing actual GDSII data ...
Summary:
Export Successful.
GDSII Import File

GDSII Import...
GDSII File: E:\ layout\ layout\ Layout2.gds
SetupFile: C:\ DOCUME~1\ BHOWMI~1.III\ LOCALS~1\ Temp\ tdb6C.tmp
Option Settings:
Treat unique GDSdata types on a layer as different layers: ON
Using original GDSII database resolution: 0.0005 microns
Warning #33: Found unknown GDSII layer 47 (Action: Created a new layer
GDS_47_DT_00 for GDSII number 47 and Data type 0)
Checking for Cell Name Conflicts...
Resolving External Cell References...
Summary:
E:\ layout\ layout\ Layout2.gds - 0 error(s), 8 warning(s)
Import Successful

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I M.

Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig (a): CMOS Inverter

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Tanner Spice Code:

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig (b): CMOS Inverter Waveforms

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

(i) NAND Gate:

Fig : NAND Gate Schematic

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Tanner Spice Code:

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig : NAND Gate Waveforms

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

(ii) NOR Gate:

Fig :NOR Gate Schematic

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Tanner Spice Code:

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig : NOR Gate Waveforms

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

(iii) AND Gate:

Fig : AND Gate Schematic

Tanner Spice Code:

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig : AND Gate Waveforms

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Layout Net list of AND:

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig : OR Gate Schematic

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Tanner Spice Code:

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Fig : OR Gate Waveforms

Department of Electronics and Communication Engineering

I M. Tech II Semester (VLSI) Mixed Signal Simulation Lab

Layout Diagram of OR Gate:

Department of Electronics and Communication Engineering

* Simulation Settings - General section *

* Simulation Settings - Parameters and SPICE Options *

* Simulation Settings - Parameters and SPICE Options *