Description
Package Types
8-Pin PDIP, SOIC, MSOP
VDD 1
Block Diagram
CS
SDI
SCK
CS 2
LDAC
SCK 3
Power-on
Reset
Interface Logic
VDD
AVSS
Input
Register A
DACA
Register
Input
Register B
DACB
Register
SDI 4
CS 2
SCK 3
SDI 4
String
DACA
Gain
Logic
8 VOUTA
7 AVSS
6 SHDN
5 LDAC
2.048V
VREF
MCP4821
Applications
MCP4822
12-Bit Resolution
0.2 LSb DNL (typ.)
2 LSb INL (typ.)
Single or Dual Channel
Rail-to-Rail Output
SPI Interface with 20 MHz Clock Support
Simultaneous Latching of the Dual DACs
with LDAC pin
Fast Settling Time of 4.5 s
Selectable Unity or 2x Gain Output
2.048V Internal Band Gap Voltage Reference
50 ppm/C VREF Temperature Coefficient
2.7V to 5.5V Single-Supply Operation
Extended Temperature Range: -40C to +125C
8 VOUTA
7 AVSS
6 VOUTB
5 LDAC
String
DACB
Gain
Logic
Output
Op Amps
Output
Logic
VOUTA
SHDN
VOUTB
DS21953A-page 1
MCP4821/MCP4822
1.0
ELECTRICAL
CHARACTERISTICS
5V AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at +25C.
Parameters
Sym
Min
Typ
Max
Units
Input Voltage
VDD
2.7
5.5
IDD
330
415
400
750
Conditions
Power Requirements
ISHDN
0.3
ISHDN_SW
3.3
Power-on-Reset Threshold
VPOR
2.0
DC Accuracy
Resolution
12
Bits
INL Error
INL
-12
12
LSb
DNL (Note 1)
DNL
-0.75
0.2
+0.75
LSb
Offset Error
VOS
-1
0.02
% of FSR
VOS/C
0.16
ppm/C
-45C to 25C
-0.44
ppm/C
+25C to 85C
gE
-2
-0.10
% of FSR
G/C
-3
ppm/C
VREF
2.008
2.048
2.088
VREF/C
125
325
ppm/C
-40C to 0C
0.25
0.65
LSb/C
-40C to 0C
Device is monotonic
Code = 0x000h
45
160
ppm/C
0C to +85C
0.09
0.32
LSb/C
0C to +85C
ENREF
(0.1-10 Hz)
290
Vp-p
Code = 0xFFFh, G = 1
eNREF
(1 kHz)
1.2
V/Hz
Code = 0xFFFh, G = 1
eNREF
(10 kHz)
1.0
V/Hz
Code = 0xFFFh, G = 1
fCORNER
400
Hz
DS21953A-page 2
MCP4821/MCP4822
5V AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at +25C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Output Swing
VOUT
0.010 to
VDD 0.040
Phase Margin
PM
66
Slew Rate
SR
0.55
V/s
ISC
15
24
mA
tSETTLING
4.5
DAC-to-DAC Crosstalk
<10
nV-s
Note 2
45
nV-s
Output Amplifier
Dynamic Performance
Digital Feedthrough
<10
nV-s
Note 2
Analog Crosstalk
<10
nV-s
Note 2
Note 1:
2:
3V AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x,
RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at 25C
Parameters
Sym
Min
Typ
Max
Units
Input Voltage
VDD
2.7
5.5
IDD
300
415
400
750
Conditions
Power Requirements
ISHDN
0.25
ISHDN_SW
VPOR
2.0
DC Accuracy
Resolution
12
Bits
INL Error
INL
-12
12
LSb
DNL (Note 1)
DNL
-0.75
0.3
0.75
LSb
VOS
-1
0.02
% of FSR
VOS/C
0.5
ppm/C
-45C to +25C
-0.77
ppm/C
+25C to +85C
gE
-2
-0.15
% of FSR
G/C
-3
ppm/C
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
Note 1:
2:
Device is monotonic
Code 0x000h
DS21953A-page 3
MCP4821/MCP4822
3V AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x,
RL = 5 k to GND, CL = 100 pF, TA = -40 to +85C. Typical values at 25C
Parameters
Sym
Min
Typ
Max
Units
Conditions
VREF
2.008
2.048
2.088
VREF/C
125
325
ppm/C
-40C to 0C
0.25
0.65
LSb/C
-40C to 0C
45
160
ppm/C
0C to +85C
0.09
0.32
LSb/C
0C to +85C
ENREF
(0.1-10 Hz)
290
Vp-p
Code = 0xFFFh, G = 1
eNREF
(1 kHz)
1.2
V/Hz
Code = 0xFFFh, G = 1
eNREF
(10 kHz)
1.0
V/Hz
Code = 0xFFFh, G = 1
fCORNER
400
Hz
Output Swing
VOUT
0.010 to
VDD 0.040
Phase Margin
PM
66
Slew Rate
SR
0.55
V/s
ISC
14
24
mA
tSETTLING
4.5
DAC-to-DAC Crosstalk
<10
nV-s
Note 2
45
nV-s
Dynamic Performance
Digital Feedthrough
<10
nV-s
Note 2
Analog Crosstalk
<10
nV-s
Note 2
Note 1:
2:
Sym
Min
Typ
Max
Input Voltage
VDD
IDD
2.7
5.5
350
440
Units
Conditions
Power Requirements
A
ISHDN
1.5
ISHDN_SW
VPOR
1.85
12
Bits
INL
LSb
DC Accuracy
Resolution
INL Error
Note 1:
2:
DS21953A-page 4
MCP4821/MCP4822
5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values at +125C by characterization or simulation.
Parameters
Sym
Min
Typ
DNL (Note 1)
DNL
0.25
LSb
Offset Error
VOS
0.02
% of FSR
VOS/C
-5
ppm/C
gE
-0.10
% of FSR
G/C
-3
ppm/C
VREF
2.048
VREF/C
125
ppm/C
0.25
LSb/C
-40C to 0C
45
ppm/C
0C to +85C
Max
Units
Conditions
Device is monotonic
Code 0x000h
+25C to +125C
Code 0xFFFh, not including offset
error
0.09
LSb/C
ENREF
(0.1 - 10 Hz)
290
Vp-p
Code = 0xFFFh, G = 1
eNREF
(1 kHz)
1.2
V/Hz
Code = 0xFFFh, G = 1
eNREF
(10 kHz)
1.0
V/Hz
Code = 0xFFFh, G = 1
fCORNER
400
Hz
Output Swing
VOUT
0.010 to
VDD 0.040
Phase Margin
PM
66
Slew Rate
SR
0.55
V/s
ISC
17
mA
tSETTLING
4.5
DAC-to-DAC Crosstalk
<10
nV-s
Note 2
45
nV-s
0C to +85C
Output Amplifier
Settling Time
Dynamic Performance
Digital Feedthrough
<10
nV-s
Note 2
Analog Crosstalk
<10
nV-s
Note 2
Note 1:
2:
DS21953A-page 5
MCP4821/MCP4822
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V 5.5V, TA= -40 to +125C.
Typical values are at +25C.
Parameters
Sym
Min
Typ
Max
Units
VIH
0.7 VDD
VIL
0.2 VDD
VHYS
0.05 VDD
ILEAKAGE
-1
CIN,
COUT
10
pF
Clock Frequency
FCLK
20
MHz
tHI
15
ns
Note 1
tLO
15
ns
Note 1
tCSSR
40
ns
tSU
15
ns
Note 1
tHD
10
ns
Note 1
tCHS
15
ns
Note 1
CS High Time
tCSH
15
ns
Note 1
tLD
100
ns
Note 1
tLS
40
ns
Note 1
tIDLE
40
ns
Note 1
Conditions
TA = +25C (Note 1)
tCSH
CS
tIDLE
tCSSR
Mode 1,1
tHI
tLO
tCHS
tHD
SI
MSb in
LSb in
LDAC
tLS
FIGURE 1-1:
DS21953A-page 6
tLD
MCP4821/MCP4822
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND.
Parameters
Sym
Min
Typ
Max
Units
TA
-40
+125
TA
-40
+125
TA
-65
+150
JA
85
C/W
JA
163
C/W
JA
206
C/W
Conditions
Temperature Ranges
Note 1
Note 1:
The MCP482X family of DACs operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of
+150C.
DS21953A-page 7
MCP4821/MCP4822
2.0
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.3
0.1
INL (LSB)
DNL (LSB)
0.2
0
-0.1
-0.2
-0.3
0
1024
2048
3072
5
4
3
2
1
0
-1
-2
-3
-4
-5
Ambient Temperature
125C
4096
1024
Code (Decimal)
FIGURE 2-1:
FIGURE 2-4:
Temperature.
0.1
DNL (LSB)
2048
3072
Code (Decimal)
25
4096
2.5
0.2
-0.1
2
1.5
1
0.5
0
-0.2
0
1024
2048
3072
Code (Decimal)
FIGURE 2-2:
Temperature.
125C
-40
4096
85C
-20
20
40
60
80
100
120
25C
FIGURE 2-5:
Temperature.
0.0766
0.0764
0.0762
INL (LSB)
85
0.076
0.0758
0.0756
-2
-4
0.0754
0.0752
-6
0.075
-40
-20
20
40
60
80
100 120
1024
DS21953A-page 8
3072
4096
Code (Decimal)
FIGURE 2-3:
Temperature.
2048
FIGURE 2-6:
Note:
MCP4821/MCP4822
2.050
2.049
2.048
2.047
2.046
2.045
2.044
2.043
2.042
2.041
2.040
100
1.E-04
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
10
1.E-05
VDD: 4V
VDD: 3V
VDD: 2.7V
-40
-20
20
40
60
80
1
1.E-06
0.1
1.E-07
0.1
1E-1
100 120
1
1E+0
10
1E+1
FIGURE 2-7:
Full-Scale VOUTA w/G = 1
(VREF) vs. Ambient Temperature and VDD.
4.100
1k
1E+3
10k
1E+4
100k
1E+5
FIGURE 2-9:
Output Noise Voltage
Density (VREF Noise Density w/G = 1) vs.
Frequency.
1.E-02
10.0
4.096
4.092
100
1E+2
Frequency (Hz)
1.E-03
1.00
4.088
VDD: 5.5V
VDD: 5V
4.084
0.10
1.E-04
4.080
4.076
-40
-20
20
40
60
80
100 120
FIGURE 2-8:
Full-Scale VOUTA w/G = 2
(2VREF) vs.Ambient Temperature and VDD.
0.01
1.E-05
100
1E+2
1k
1E+3
10k
100k
1E+4
1E+5
Bandwidth (Hz)
1M
1E+6
FIGURE 2-10:
Output Noise Voltage (VREF
Noise Voltage w/G = 1) vs. Bandwidth.
DS21953A-page 9
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
5.5V
5.0V
4.0V
3.0V
2.7V
VDD
320
IDD (A)
300
280
260
240
600
5.5V
5.0V
4.0V
3.0V
2.7V
VDD
550
500
IDD (A)
340
450
400
220
350
200
180
300
-40
-20
20
40
60
80
100
120
-40
-20
FIGURE 2-11:
MCP4821 IDD vs. Ambient
Temperature and VDD.
20
40
80
100
120
FIGURE 2-14:
MCP4822 IDD vs. Ambient
Temperature and VDD.
Occurrence
20
15
10
FIGURE 2-13:
(VDD = 5.0V).
DS21953A-page 10
440
430
425
420
435
435
430
425
420
350
>350
345
340
335
330
325
320
315
310
305
300
295
290
285
415
410
405
400
385
Occurrence
10
395
14
22
20
18
16
14
12
10
8
6
4
2
0
390
16
12
FIGURE 2-15:
(VDD = 2.7V).
18
IDD (A)
415
IDD (A)
FIGURE 2-12:
(VDD = 2.7V).
410
405
400
395
390
380
385
>320
320
315
310
305
300
295
290
285
280
275
270
IDD (A)
Occurrence
60
25
20
18
16
14
12
10
8
6
4
2
0
265
Occurrence
IDD (A)
FIGURE 2-16:
(VDD = 5.0V).
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.7
ISHDN (A)
0.5
0.4
0.3
0.2
-0.05
-0.1
VDD
-0.15
5.5V
5.0V
4.0V
3.0V
2.7V
VDD
0.6
5.5V
5.0V
4.0V
3.0V
2.7V
-0.2
-0.25
-0.3
-0.35
-0.4
0.1
-0.45
-0.5
0
-40
-20
20
40
60
80
100
-40
120
-20
FIGURE 2-17:
Hardware Shutdown Current
vs. Ambient Temperature and VDD.
4
40
60
80
100
120
4.0V
2.5
3.0V
2.7V
VDD
1.5
VDD
5.0V
ISHDN_SW (A)
20
FIGURE 2-20:
Gain Error vs. Ambient
Temperature and VDD.
5.5V
3.5
5.5V
3.5
5.0V
3
4.0V
2.5
2
3.0V
2.7V
1.5
1
-40
-20
20
40
60
80
100
120
-40
-20
20
40
60
80
100
120
FIGURE 2-18:
Software Shutdown Current
vs. Ambient Temperature and VDD.
FIGURE 2-21:
VIN High Threshold vs.
Ambient Temperature and VDD.
1.6
0.09
0.07
0.05
5.5V
0.03
VDD
0.01
5.0V
4.0V
3.0V
2.7V
-0.01
-0.03
-40
-20
20
40
60
80
100 120
FIGURE 2-19:
Offset Error vs. Ambient
Temperature and VDD.
0.11
Offset Error (%)
VDD
1.5
5.5V
1.4
5.0V
1.3
1.2
4.0V
1.1
1
3.0V
2.7V
0.9
0.8
-40
-20
20
40
60
80
100
120
FIGURE 2-22:
VIN Low Threshold vs.
Ambient Temperature and VDD.
DS21953A-page 11
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
16
2.5
5.5V
2
5.0V
1.75
1.5
4.0V
1.25
1
3.0V
2.7V
0.75
0.5
15
IOUT_HI_SHORTED (mA)
5.5V
5.0V
4.0V
3.0V
2.7V
VDD
2.25
14
VDD
13
12
11
0.25
10
0
-40
-20
20
40
60
80
-40
100 120
-20
FIGURE 2-23:
Input Hysteresis vs. Ambient
Temperature and VDD.
40
60
80
100
120
6.0
4.0V
0.033
5.0
0.031
VREF = 4.096V
0.029
0.027
0.025
3.0V
0.023
2.7V
VDD
0.021
VOUT (V)
20
FIGURE 2-26:
IOUT High Short vs. Ambient
Temperature and VDD.
0.035
4.0
3.0
2.0
1.0
0.019
0.017
0.0
0.015
-40
-20
20
40
60
80
100 120
FIGURE 2-24:
VOUT High Limit vs. Ambient
Temperature and VDD.
0.0028
FIGURE 2-27:
6
8
10
IOUT (mA)
12
14
16
VDD
0.0026
0.0024
5.5V
0.0022
5.0V
0.0020
4.0V
3.0V
2.7V
0.0018
0.0016
0.0014
0.0012
0.0010
-40
-20
20
40
60
80
100 120
FIGURE 2-25:
VOUT Low Limit vs. Ambient
Temperature and VDD.
DS21953A-page 12
MCP4821/MCP4822
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
VOUT
VOUT
SCK
LDAC
LDAC
Time (1 s/div)
FIGURE 2-28:
Time (1 s/div)
FIGURE 2-31:
VOUT
VOUT
SCK
SCK
LDAC
LDAC
Time (1 s/div)
FIGURE 2-32:
Shutdown.
VOUT
SCK
LDAC
Time (1 s/div)
FIGURE 2-30:
FIGURE 2-29:
Time (1 s/div)
Frequency (Hz)
FIGURE 2-33:
DS21953A-page 13
MCP4821/MCP4822
3.0
PIN DESCRIPTIONS
TABLE 3-1:
MCP4821
Pin No.
MCP4822
Pin No.
Symbol
VDD
CS
SCK
SDI
LDAC
SHDN
VOUTB
DACB Output
AVSS
Analog Ground
VOUTA
DACA Output
3.1
Function
3.6
3.7
3.2
3.8
3.3
3.4
3.5
DS21953A-page 14
MCP4821/MCP4822
4.0
GENERAL OVERVIEW
INL < 0
EQUATION 4-1:
111
110
Actual
Transfer
Function
101
Digital
Input
Code
100
011
Ideal Transfer
Function
010
001
LSb SIZE
2.048V G D N
VOUT = ------------------------------------n
2
000
INL < 0
DAC Output
TABLE 4-1:
LSb SIZES
Device
Gain
LSb Size
MCP482X
MCP482X
1x
2x
2.048V/4096
4.096V/4096
4.0.1
FIGURE 4-1:
4.0.2
DNL ACCURACY
INL ACCURACY
INL Accuracy.
111
110
Actual
Transfer
Function
101
Digital
Input
Code
100
Ideal Transfer
Function
011
010
001
000
Narrow Code < 1 LSb
DAC Output
FIGURE 4-2:
4.0.3
DNL Accuracy.
OFFSET ERROR
4.0.4
GAIN ERROR
DS21953A-page 15
MCP4821/MCP4822
4.1.1
Circuit Descriptions
OUTPUT AMPLIFIERS
5V
Supply Voltages
4.1
4.1.2
VOLTAGE REFERENCE
4.1.3
Transient Duration
10
VDD - VPOR
Time
4.1.1.1
VPOR
8
6
4
2
0
FIGURE 4-3:
4.1.4
TA = +25C
2
3
4
VDD VPOR (V)
SHUTDOWN MODE
Shutdown mode can be entered by using either hardware or software commands. The hardware pin
(SHDN) is only available on the MCP4821. During
Shutdown mode, the supply current is isolated from
most of the internal circuitry. The serial interface
remains active, thus allowing a Write command to
bring the device out of Shutdown mode. When the output amplifiers are shut down, the feedback resistance
(typically 500 k) produces a high-impedance path to
AVSS. The device will remain in Shutdown mode until
the SHDN pin is brought high and a write command
with SD = 1 is latched into the device. When a DAC is
changed from Shutdown to Active mode, the output
settling time takes < 10 s, but greater than the
standard Active mode settling time (4.5 s).
DS21953A-page 16
MCP4821/MCP4822
5.0
SERIAL INTERFACE
5.1
Overview
5.2
REGISTER 5-1:
Write Command
Upper Half:
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
A/B
GA
SHDN
D11
D10
D9
D8
bit 15
bit 8
Lower Half:
W-x
D7
bit 7
bit 15
W-x
D6
W-x
D5
W-x
D4
W-x
D3
W-x
D2
W-x
D1
W-x
D0
bit 0
1=
0=
bit 14
bit 13
Dont Care
1=
0=
bit 12
bit 11-0
Legend
R = Readable bit
W = Writable bit
-n = Value at POR
1 = bit is set
0 = bit is cleared
x = bit is unknown
DS21953A-page 17
MCP4821/MCP4822
CS
0
10 11
12
13 14 15
SCK
(Mode 0,0)
config bits
SDI
(Mode 1,1)
A/B
12 data bits
LDAC
VOUT
FIGURE 5-1:
DS21953A-page 18
Write Command.
MCP4821/MCP4822
6.0
TYPICAL APPLICATIONS
6.3
Digital Interface
6.2
VDD
VDD
0.1 F 0.1 F
VDD
VOUTA
0.1 F
1 F
VOUTB
VOUTA
1 F
VOUTB
SDI
CS1
SDI
AVSS
SDO
SCK
LDAC
CS0
AVSS
FIGURE 6-1:
Diagram.
6.4
PICmicro Microcontroller
6.1
MCP482X
MCP482X
AVSS
Typical Connection
Layout Considerations
DS21953A-page 19
MCP4821/MCP4822
6.5
6.5.1.1
Single-Supply Operation
6.5.1
VDD
VCC+
RSENSE
VDD
MCP482X
VOUT
Comparator
R1
VTRIP
R2
0.1 uF
VCC
SPI
3
D
V OUT = 2.048 G --------12
2
R2
V trip = VOUT --------------------
R 1 + R 2
EXAMPLE 6-1:
DS21953A-page 20
MCP4821/MCP4822
6.5.1.2
VCC+
VCC+
RSENSE
VDD
MCP482X
VOUT
R3
R1
VTRIP
R2
0.1 F
Comparator
VCC-
SPI
3
VCCD
V OUT = 2.048 G ------12
2
Thevenin
Equivalent
R2R3
R 23 = -----------------R2 + R 3
V 23
R1
VOUT
VO
( V CC+ R 2 ) + ( VCC- R 3 )
= -----------------------------------------------------R 2 + R3
V OUT R23 + V 23 R 1
V trip = -------------------------------------------R 2 + R 23
EXAMPLE 6-2:
R23
V23
DS21953A-page 21
MCP4821/MCP4822
6.6
Bipolar Operation
R2
VDD
VDD
VCC+
R1
VOUT
R3
VO
VIN+
MCP482X
VCC
0.1 F
R4
SPI
3
D
V OUT = 2.048 G ------12
2
V OUT R4
VIN+ = -------------------R3 + R 4
R2
R2
VO = V IN+ 1 + ------ V DD ------
R 1
R 1
EXAMPLE 6-3:
6.6.1
4.
The amplifier gain (R2/R1), multiplied by fullscale VOUT (4.096V), must be equal to the
desired minimum output to achieve bipolar
operation. Since any gain can be realized by
choosing resistor values (R1+R2), the VREF
value must be selected first. If a VREF of 4.096V
is used (G=2), solve for the amplifiers gain by
setting the DAC to 0, knowing that the output
needs to be -2.05V. The equation can be
simplified to:
R2
2.05
--------- = ----------------R1
4.096V
R
1
-----2- = --2
R1
DS21953A-page 22
MCP4821/MCP4822
6.7
R2
VDD
VOUTA
VCC+
R1
MCP482X
VDD
VCC+
VO
R5
R3
MCP482X
DACB (Offset Adjust)
SPI
R4
0.1 F
VCC
VCC
DB
V OUTB = ( 2.048V G B ) ------12
2
DA
V OUTA = ( 2.048V G A ) ------12
2
AVSS = GND
VOUTB R 4 + VCC- R3
VIN+ = -----------------------------------------------R3 + R 4
R2
R2
V O = V IN+ 1 + ------ VOUTA ------
R 1
R 1
V CC+ R 4 + VCC- R5
V45 = -------------------------------------------R 4 + R5
V OUTB R45 + V 45 R 3
V IN+ = ----------------------------------------------R 3 + R 45
R4 R5
R 45 = -----------------R4 + R5
R2
R2
V O = VIN+ 1 + ------ V OUTA ------
R1
R1
Offset Adjust Gain Adjust
EXAMPLE 6-4:
DS21953A-page 23
MCP4821/MCP4822
6.8
Designing A Double-Precision
DAC Using A Dual DAC
1.
2.
3.
4.
VDD
MCP482X
VDD
MCP482X
VCC+
DACA (Fine Adjust)
VO
VOUTA
R1
R1 >> R2
VOUTB
R2
0.1 F
VCC
DB
VOUTB = 2.048V G B ------12
2
V OUTA R2 + V OUTB R1
VO = ----------------------------------------------------R1 + R 2
EXAMPLE 6-5:
DS21953A-page 24
MCP4821/MCP4822
6.9
MCP482X
VOUT
VCC+
Load
IL
VCC Ib
SPI
3
Rsense
V OUT
D
= 2.048V G ------12
2
IL
I b = ---
V OUT
I L = --------------- -----------Rsense + 1
G = Gain select (1x or 2x)
D = Digital value of DAC (0 4096)
EXAMPLE 6-6:
Digitally-Controlled Current
Source.
DS21953A-page 25
MCP4821/MCP4822
7.0
DEVELOPMENT SUPPORT
7.1
DS21953A-page 26
7.2
Application Notes
MCP4821/MCP4822
8.0
PACKAGING INFORMATION
8.1
8-Lead MSOP
XXXXXX
YWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
MCP4821
E/P e^3 256
0524
4821E
524256
Example:
MCP4821E
e3 0524
SN^^
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS21953A-page 27
MCP4821/MCP4822
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
A2
A
c
A1
(F)
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0
0.08
0.22
5
5
-
MIN
8
Number of Pins
.026 BSC
Pitch
A
.043
Overall Height
A2
.030
.033
.037
Molded Package Thickness
.006
.000
A1
Standoff
E
.193 TYP.
Overall Width
E1
.118 BSC
Molded Package Width
.118 BSC
D
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
Foot Angle
0
8
c
Lead Thickness
.003
.006
.009
.009
.012
.016
Lead Width
B
55
15
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8
0.23
0.40
15
15
DS21953A-page 28
MCP4821/MCP4822
8-Lead Plastic Dual In-line (P) 300 mil (PDIP)
E1
D
2
n
A2
A1
B1
p
eB
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
L
c
B1
B
eB
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21953A-page 29
MCP4821/MCP4822
8-Lead Plastic Small Outline (SN) Narrow, 150 mil (SOIC)
E
E1
D
2
B
45
c
A2
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
h
L
c
B
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21953A-page 30
MCP4821/4822
APPENDIX A:
REVISION HISTORY
DS21953A-page 31
MCP4821/4822
NOTES:
DS21953A-page 32
MCP4821/4822
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device:
MCP4821:
MCP4821T:
MCP4822:
MCP4822T:
Temperature Range:
= -40C to +125C
Package:
c)
d)
e)
a)
b)
c)
DS21953A-page 33
MCP4821/4822
NOTES:
DS21953A-page 34
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS21953A-page 35
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04/20/05
DS21953A-page 36