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2, MAY 2014


A PFC-Based BLDC Motor Drive Using a

Canonical Switching Cell Converter
Vashist Bist, Student Member, IEEE, and Bhim Singh, Fellow, IEEE

AbstractThis paper presents a power factor correction (PFC)based canonical switching cell (CSC) converter-fed brushless dc
motor (BLDCM) drive for low-power household applications. The
speed of BLDCM is controlled by varying the dc-bus voltage of
voltage source inverter (VSI). The BLDCM is electronically commutated for reduced switching losses in VSI due to low-frequency
switching. A front-end CSC converter operating in discontinuous
inductor current mode (DICM) is used for dc-bus voltage control
with unity power factor at ac mains. A single sensor for dc-bus
voltage sensing is used for the development of the proposed drive,
which makes it a cost-effective solution. A prototype of the proposed
conguration is developed, and its performance is validated with
test results for the control of speed over a wide range with a unity
power factor at universal ac mains.
Index TermsBrushless dc motor (BLDCM), canonical
switching cell (CSC) converter, discontinuous inductor current
mode (DICM), power factor correction (PFC), power quality.

MONG NUMEROUS motors, brushless dc motor
(BLDCM) is preferred in many low and medium power
applications including household appliances, industrial tools,
heating ventilation and air conditioning (HVAC), medical equipments, and precise motion control systems [1][7]. BLDCM is
preferred because of its high torque/inertia ratio, high efciency,
ruggedness, and low-electro-magnetic interference (EMI) problems [1], [2]. The stator of the BLDCM consists of three-phase
concentrated windings and rotor has permanent magnets [1], [2].
It is also known as an electronically commutated motor (ECM)
since an electronic commutation based on rotor position via
a three-phase voltage source inverter (VSI) is used [8], [9].
Therefore, the problems associated with brushes, such as sparking, and wear and tear of the commutator assembly are
Fig. 1 shows a conventional scheme of BLDCM drive fed by
an uncontrolled rectier and a dc-link capacitor followed by a
three-phase pulse width modulation (PWM)-based VSI is used
for feeding the BLDCM [10]. This type of scheme draws peaky,
harmonic rich current from the supply and leads to a high value
of total harmonic distortion (THD) of supply current and
very low power factor at ac mains as shown in Fig. 2 [11]. A
very high THD of supply current of 65.3% and a very poor

Manuscript received September 07, 2013; revised December 20, 2013;

accepted January 28, 2014. Date of publication February 11, 2014; date of
current version May 02, 2014. Paper no. TII-13-0613.
The authors are with the Department of Electrical Engineering, Indian Institute
of TechnologyDelhi, New Delhi 110016, India (e-mail: vashist.bist@gmail.
Digital Object Identier 10.1109/TII.2014.2305620

power factor of 0.72 is achieved which is not acceptable by

International Electro-technical Commission (IEC) 61000-3-2
A front-end power factor correction (PFC) converter is used
after the diode bridge rectier (DBR) for improving the quality
of power and achieving a near unity power factor at ac mains
[13], [14]. The mode of operation of the PFC converter is a
critical issue as it directly affects the cost of overall system.
The continuous inductor current mode (CICM) and the discontinuous inductor current mode (DICM) are the two basic
modes of operation of a PFC converter [13], [14]. A control of
current multiplier is normally used for PFC converter operating
in CICM and requires three sensors (2-V, 1-C) for the operation which is not cost-effective for low-power applications,
whereas, a PFC converter operating in DICM uses a voltage
follower control which requires sensing of dc-link voltage
for voltage control and inherent PFC is achieved at ac
mains [13], [14].
Many topologies of a PFC-based BLDCM drives have been
reported in the literature [10], [15][23]. A boost PFC converter
has been the most popular conguration for feeding BLDCM
drive as shown in Fig. 3 [16][18]. A constant dc-link voltage is
maintained at the dc-link capacitor and a PWM-based VSI is used
for the speed control. Hence, the switching losses in VSI are very
high due to high switching PWM signals and require huge
amount of sensing for its operation. Cheng [19] has proposed
an active rectier-based BLDC motor drive fed which requires
complex control and is suitable for higher power applications.
Lee et al. [20] have explored various reduced parts congurations for PFC operation which also uses a PWM-based VSI and
have high switching losses in it. A buck chopper operating as a
front-end converter for feeding a BLDC motor drive has been
proposed by Barkley et al. [21]. It also has higher switching
losses associated with it due to high-frequency switching.
Madani et al. [22] have proposed a boost half bridge PFC-based
BLDCM drive using four switch VSI. This also requires a
necessary PWM operation of VSI and PFC half bridge boost
converter, which introduces high switching losses in the overall
These switching losses are reduced by using a concept of
variable dc-link voltage for speed control of BLDC motor [24].
This utilizes the VSI to operate in low-frequency switching
required for electronic commutation of BLDC motor, hence
reduces the switching losses associated with it. The front-end
SEPIC and Cuk converter feeding a BLDC motor using a
variable voltage control have been proposed in [10] and [23],

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and its parameters are selected to operate in a DICM for obtaining

a high-power factor at wide range of speed control. A prototype
of proposed drive is developed to experimentally demonstrate its
performance for control of speed over a wide range with a unity
power factor at universal ac mains (90265 V).

Fig. 1. Conventional DBR-fed BLDCM drive.

Fig. 2. Measured PQ indices of the conventional DBR-fed BLDCM drive at rated

load on BLDCM with supply voltage as 220 V showing (a) supply voltage and
supply current; (b) active, reactive, and apparent power, PF, and DPF; and
(c) THD of supply current at ac mains.

Fig. 3. Conventional PFC converter-fed BLDCM drive.

but at the cost of two current sensors. This paper presents the
development of a reduced sensor-based BLDC motor drive for
low-power application.
Fig. 4 shows the proposed BLDCM drive with a front-end
PFC-based canonical switching cell (CSC) converter. A CSC
converter operating in DICM acts as an inherent power factor
pre-regulator for attaining a unity power factor at ac mains. A
variable dc-bus voltage of the VSI is used for controlling the
speed of the BLDCM. This operates the VSI in low-frequency
switching by electronically commutating the BLDCM for reducing the switching losses in six insulated gate bipolar transistors
(IGBTs) of VSI which share the major portion of overall losses
in the BLDCM drive. The front-end CSC converter is designed

The proposed BLDCM drive uses a CSC converter operating

in DICM [25][28]. In DICM, the current in inductor becomes
discontinuous in a switching period ( ). Three states of CSC
converter are shown in Fig. 5(a)(c). Waveforms of inductor
and intermediate capacitors voltage
for a complete cycle of line frequency are shown in Fig. 6(a), whereas
Fig. 6(b) shows the variation in different variables of CSC
converter such as switch gate voltage ( ), inductor current
( ), intermediate capacitors voltage ( ), and dc-link voltage
( ) in a complete switching period. Three modes of operation
are described as follows.
Mode I: As shown in Fig. 5(a), when switch
is turned ON,
the energy from the supply and stored energy in the intermediate
are transferred to inductor . In this process, the
voltage across the intermediate capacitor
reduces, while
inductor current
and dc-link voltage
are increased as
shown in Fig. 6(b). The designed value of intermediate capacitor
is large enough to hold enough energy such that the voltage
across it does not become discontinuous.
Mode II: The switch is turned OFF in this mode of operation as
shown in Fig. 5(b). The intermediate capacitor
is charged
through the supply current while inductor
starts discharging
hence voltage
starts increasing, while current decreases in
this mode of operation as shown in Fig. 6(b). Moreover, the
voltage across the dc-link capacitor
continues to increase due
to discharging of inductor .
Mode III: This is the discontinuous conduction mode of
operation as inductor
is completely discharged and current
becomes zero as shown in Fig. 5(c). The voltage across
intermediate capacitor
continues to increase, while dc-link
capacitor supplies the required energy to the load, hence
starts decreasing as shown in Fig. 6(b).
The proposed BLDCM drive uses a PFC-based CSC converter
operating in DICM. The front-end PFC-based CSC converter of
is designed for a 314-W BLDCM. (Full specications are given in the Appendix.) The dc-link voltage has to be
controlled from 50 V (
) to 200 V (
) with a nominal
voltage of 120 V (
). For the supply voltage ( ) of 220 V, the
voltage appearing after the DBR is given as [11]

A nominal duty ratio ( ) corresponding to

is as [11]



Fig. 4. Proposed BLDCM drive using CSC converter.

Fig. 5. Operation of CSC converter in different modes of operation in a complete switching period: (a) Mode I; (b) Mode II; and (c) Mode III.

Now to operate this converter for PFC even at very low duty
ratio, the value of inductor is taken around 1/10th of the critical
value [29]. Hence, it is
is taken as
Hence, the selected value of inductor
An intermediate capacitor
is designed for permitted
ripple voltage of
across it and it is taken as 10% of
is the voltage across intermediate capacitor, i.e.,
] and is given as [14]

Fig. 6. Waveforms during complete (a) line cycle and (b) switching cycle.

The design of a CSC converter is very similar to a nonisolated

Cuk converter with a single inductor and a switching cell which is
a combination of a switch
, diode , and an intermediate
[14]. The critical value of inductance
to operate
at boundary condition is given as [14]

is the equivalent emulated load resistance which is
given as
Hence, the capacitor of 440 nF is selected.
Now for a permitted ripple of 1% of the nominal dc-link
voltage across the dc-link capacitor ( ), the value of dc-link
capacitor is calculated as [14]


is inductor, ( ) current, and

is switching frequency.


is line frequency in rad/s and

is dc-link current.



Hence, the dc-link capacitor of

is selected.
To avoid the reection of high-order harmonics in supply
system, a low-pass inductive-capacitive (LC) lter is designed
whose maximum value,
is calculated as [30]

are amplitudes of supply current and
supply voltage and is the displacement angle between them.
Hence, the lter capacitor of 330 nF is selected.
Now, the value of lter inductor is designed by considering the
source impedance ( ) of 4%5% of the base impedance. Hence,
the additional value of inductance required is given as

Fig. 7. Operation of a VSI-fed BLDCM when switches






are conducting.


is the cut-off frequency which is selected such that
< < , hence it is taken as
Hence, an LC lter with inductance
and capacitance
selected as 3.77 mH and 330 nF, respectively.
The control of the proposed drive is classied into control of
PFC converter and BLDCM.

and are the proportional and integral gains of the

voltage PI controller.
The output of voltage controller is compared with a highfrequency saw-tooth signal ( ) to generate PWM pulses as

A. Control of Front-End PFC Converter

The PFC-based CSC converter operating in DICM is controlled via a control of voltage follower. It generates PWM pulses
for maintaining the necessary dc-link voltage at the input of VSI.
A single-voltage sensor is used for the control of a PFC-based
CSC converter operating in DICM.
A reference dc-link voltage ( ) is generated as

are the motors voltage constant and the
reference speed, respectively.
Now, the reference dc-link voltage ( ) is compared with the
sensed dc-link voltage ( ) to generate a voltage error signal
( ) at th sampling instant as

This error voltage ( ) is given to the voltage proportional

integral (PI) controller, which generates a controlled output
voltage ( ) at any time instant as



represents the switching signals given to the switch.

B. Control of BLDCM: Electronic Commutation

An electronic commutation of the BLDCM includes proper
switching of VSI in such a way that a symmetrical dc current is
drawn from the dc-link capacitor for 120 and placed symmetrically at the centre of back electro-motive force (EMF) of each
A Hall-Effect position sensor is used to sense the rotor position
on a span of 60 , which is required for the electronic commutation of BLDCM. The conduction states of two switches ( and
) are shown in Fig. 7. A line current
is drawn from the dclink capacitor in which magnitude depends on the applied dc-link
voltage ( ), back-EMFs ( and ), resistances ( and ),
and self and mutual inductance ( , , and ) of the stator
windings. Table I shows the different switching states of the VSI
feeding a BLDCM based on the Hall-Effect position signals
An eZDSP-F2812 based on TMS320-F2812 digital signal
processor (DSP) is used for the development of experimental





Fig. 8. Waveforms of proposed BLDCM drive at rated load on BLDCM with

supply voltage as 220 V and dc bus voltage as (a) 200 V and (b) 50 V.

prototype of proposed drive. An opto-isolation circuitry based on

6N136 opto-coupler is used to provide the required isolation
between the DSP and the switches used in PFC converter and
VSI. The sensed dc-link voltage is given to the input of DSP
via an on-board analog to digital converter (ADC). A lter for
sensing the Hall-Effect position signal is developed for voltage
scaling between the DSP [complementary metaloxide semiconductor (CMOS) level] and Hall-Effect position sensors
[transistor-transistor logic (TTL) level]. Moreover, a softwarebased ltering for Hall signals is also developed using a moving
average ltering technique [31]. Test results of the proposed
BLDCM drive are discussed as follows.
A. Performance of Proposed BLDCM Drive at Rated Loading
The performance of the proposed BLDCM drive at rated
supply voltage, rated load on BLDCM, and dc-bus voltage of
200 V (1970 rpm) is shown in Fig. 8(a) and at dc-bus voltage of
50 V (370 rpm) is shown in Fig. 8(b), respectively. A unity power
factor is achieved as the ac mains current is in phase with ac
mains voltage ( ) and is sinusoidal in nature. The dc-bus voltage
( ) is obtained at the desired reference value, whereas the
frequency of stator current ( ) decides the speed of BLDC
motor. The speed of the BLDCM achieved for different values
of dc-link voltage corresponding to the reference voltage for duty
control at the ADC is shown in Table II.
B. Performance of PFC-Based CSC Converter
As the CSC converter is designed to operate in DICM, a
discontinuous current in inductor
and continuous voltage

Fig. 9. (a) Inductor current and intermediate capacitors and its (b) enlarged
waveforms at rated load on BLDCM at rated condition.

are achieved. Fig. 9(a) and (b)

across intermediate capacitor
shows inductor current ( ) and intermediate capacitors voltage
) with ac mains voltage ( ) and ac mains current ( ) and
their enlarged waveforms, respectively.
C. Stresses on PFC Converter Switch
Fig. 10(a) and (b) shows voltage and current stress of PFC
switch at rated condition. A peak voltage stress of 510 V and peak
current stress of 22 A is obtained at the PFC switch, which is quite
acceptable for a PFC converter operating in DICM.
D. Dynamic Performance of Proposed BLDCM Drive
Fig. 11 shows the dynamic performance of the proposed
BLDCM drive. Fig. 11(a) shows the performance during starting
of BLDCM at 50 V with a limited inrush current drawn from the
dc-link capacitor and the supply system. As shown in the



Fig. 10. (a) Voltage and current stress on a PFC converter switch and its
(b) enlarged waveforms at rated load on BLDCM at rated condition.

obtained test result, during an increase in dc-bus voltage of the

VSI, the magnitude and frequency of the stator current ( ) of
BLDCM are increasing which conrms that the BLDCM is
gaining speed. Fig. 11(b) shows the dynamic performance during
speed control by step change in dc-link voltage. Fig. 11(c) shows
the dynamic performance during load change on BLDCM. The
dynamic behavior of the proposed drive during step change in
supply voltage (260180 V) is shown in Fig. 11(d). A smooth
variation of dc-link voltage with limited stator current is obtained
in all the mentioned cases, which demonstrate a satisfactory
closed loop performance of the proposed BLDCM drive. The
controller gains are given in the Appendix.
E. PFC and Improved Power Quality
Fig. 12 shows the obtained power quality (PQ) indices demonstrating the unity power factor operation of the proposed
BLDCM drive. The performance indices such as ac mains
voltage ( ), ac mains current ( ), active ( ), reactive ( )
and apparent ( ) powers, power factor (PF), displacement
power factor (DPF), and THD of supply current are measured
on a Fluke make PQ analyzer. Fig. 12(a)(c) and (d)(f) shows
the test results obtained for dc-link voltage of 200 and 50 V,
respectively. Fig. 12(g)(i) and (j)(l) shows the performance at
supply voltages of 90 and 270 V, respectively. A unity power
factor is obtained with PQ indices under IEC 61000-3-2 limits
[12]. This demonstrates a satisfactory performance in terms of
power quality at different speeds and its operation at universal ac

Fig. 11. Dynamic performances of proposed BLDCM drive system during

(a) starting at 50 V, (b) speed control for change in dc-link voltage from 100
to 150 V, (c) load change, and (d) supply voltage uctuation.


This section deals with a comparative study of three congurations of BLDCM drive. The proposed conguration is compared with a conventional DBR-fed BLDCM drive and a



Fig. 13. Comparative analysis of efciency of the conventional and the proposed

Fig. 12. Measured PQ indices of proposed BLDCM drive at (a)(c) rated load on
, (d)(f) rated load on BLDCM with
BLDCM with
, (g)(i) rated load on BLDCM with
, and (j)(l) rated load on BLDCM with

conventional single-switch PFC converter feeding BLDCM

drive via a PWM-based switching of VSI. This study is classied
as follows.
A. Comparison on Basis of Efciency
The losses in a two-conventional scheme of BLDCM drive are
higher on account of high switching losses in a PWM-based VSI,
which results in higher switching losses. This accounts for an
increase in efciency of the proposed system, due to use of low
switching frequency as shown in Fig. 13. An efciency of
81.34% is achieved at the rated condition which is higher than
the obtained efciency of the conventional drive system with
PWM switching frequency of VSI at 20 kHz.
B. Comparison on Basis of Power Quality and Power Factor
Fig. 14(a) and (b) shows the THD of supply current at ac mains
and power factor with output power, respectively. As shown

Fig. 14. Comparative performance of (a) power factor, and (b) THD of supply
current at ac mains with output power for conventional and the proposed

these gures, the THD of supply current and power factor

obtained in PFC converter-fed BLDCM drive are very low as
compared to a DBR-fed BLDCM drive. Hence, the power quality
indices achieved in the proposed drive and the conventional
PFC-based BLDCM drive is under the acceptable limits of IEC
61000-3-2 [12]. But the conventional scheme has a lower
efciency due to higher switching losses in PWM-based switching of VSI.
C. Comparison on Basis of Cost and System Complexity
Table III shows a comparative performance of the proposed
conguration with the conventional scheme of BLDCM drive.
The evaluation is based on the control requirement, sensor
requirement, and losses in PFC converter and VSI-fed BLDCM.
Since the proposed conguration requires a single-voltage sensor
and a simple control loop for dc-link voltage control, a low-cost




processor can be used for the development purpose. Increased

efciency, requirement of minimum amount of sensing and a
much simple approach of speed control with a PFC at ac mains
make the proposed drive a good solution for low-power
A PFC-based CSC converter-fed BLDCM drive has been
proposed for targeting low-power household applications. A
variable voltage of dc bus has been used for controlling the
speed of BLDCM which eventually has given the freedom to
operate VSI in low-frequency switching mode for reduced
switching losses. A front-end CSC converter operating in DICM
has been used for dual objectives of dc-link voltage control and
achieving a unity power factor at ac mains. The performance of
the proposed drive has been found quite well for its operation at
variation of speed over a wide range. A prototype of the CSCbased BLDCM drive has been implemented with satisfactory test
results for its operation over complete speed range and its
operation at universal ac mains. The obtained PQ indices are
found under the limits various international PQ standards such as
IEC 61000-3-2 [12].
BLDCM Specications:




Controller Gains:

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Bhim Singh (SM99F10) received the B.E. degree

in electrical engineering from the University of
Roorkee, Roorkee, India, in 1977, and the M.Tech.
degree in power electronics, electrical machines, and
drives and the Ph.D. degree from the Indian Institute
of Technology (IIT)Delhi, New Delhi, India, in 1979
and 1983, respectively.
In 1983, he joined the Department of Electrical
Engineering, University of Roorkee, as a Lecturer,
and in 1988 he became a Reader. In December 1990,
he joined the Department of Electrical Engineering,
IITDelhi, as an Assistant Professor. He became an Associate Professor in 1994
and a Professor in 1997. His research interests include power electronics,
electrical machines and drives, renewable energy systems, active lters, exible
ac transmission system (FACTS), high-voltage direct current (HVDC), and
power quality.
Dr. Singh is a Fellow of the Indian National Academy of Engineering (INAE),
the National Science Academy (NSc), the IEEE, the Institute of Engineering and
Technology (IET), the Institution of Engineers (India) [IE(I)], and the Institution
of Electronics and Telecommunication Engineers (IETE). He is also a Life
Member of the Indian Society for Technical Education (ISTE), the System
Society of India (SSI), and the National Institution of Quality and Reliability
(NIQR). He received the Khosla Research Prize from the University of Roorkee in
1991. He was the recipient of the J. C. Bose and Bimal K. Bose Awards from
the IETE for his contributions in the eld of power electronics in 2000. He was also
a recipient of the Maharashtra State National Award from the ISTE in recognition
of his outstanding research work in the area of power quality in 2006. He received
the Power and Energy Society (PES) Delhi Chapter Outstanding Engineer Award
in 2006. He was the General Chair of the IEEE International Conference on
Power Electronics, Drives, and Energy Systems (PEDES2006) and (PEDES2010)
held in New Delhi.

Vashist Bist (S13) received the Diploma and B.E.

degrees in instrumentation and control engineering
from Sant Longowal Institute of Engineering and
Technology (SLIET Longowal), Punjab, India, in
2007 and 2010, respectively. Currently, he is working toward the Ph.D. degree in the Department of
Electrical Engineering, Indian Institute of Technology
Delhi, New Delhi, India.
His research interests include power electronics,
electrical machines, and drives.