IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-22,

NO.

1, FEBRUARY

1987

77

Dynamic ;Safe-Area Protection for

Power Transistors Employs
Peak-Temperature
Limiting
ROBERT

J. WIDLAR

AND MINEO

Abstract Safe-area protection can be provided for a large power

transistor by limiting its peak junction temperature. A p-n junction that is
distributed throughout the power transistor in close prclximity to the entire
active emitter makes a satisfactory peak-temperature sensor. Thermal
response times under 100 ys are practical, so that ~dcfoldback cnrrent
limiting is not required. Peak-cument limiting and an overvoltage shutdown
that operates as B VC~o is approached establishes thle boundaries of the
safe-area curve.

I.

HERMAL
power

has been employed

voltage

However,

temperature

protection.

sensing

Located

conventional

network

coupliing

between

could

provide

the

at the edge of a power

transistor

with increasing

age has been used to compensate

coupling.

This

foldback

current

array,

of the

should

dissipation

case temperature

in practice.

control
With

it

encountered

is expected

the junction
a distributed

that

output

the

volt-

thermal

match

the

at the maximum

thermal

temperature.
peak-temperature

cur-

collector

for inadequate
limit

safe-area curve for continuous

peratures

At higher

tem-

limiting

will

sensor that is tightly

coupled to the entire active emitter, foldback current limiting is unnecessary [6]. Maximum
capabilities
will follow
the actual

safe-area

curve of the power transistor,

continuous,

for all operating

completely

effective,

long

as the current

transistor
sustaining

increases

the continuous

that can be guaranteed

arbitrary

by an order of

deratings

and the toler-

ance problems of foldback current limiting. Increased pulse

ratings are a bonus. At the same time, much better control
of peak junction

temperature

is maintained

under

worst-

case conditions.

conditions.

pulse or

The protection

is

even if severe hot spots develop,

as

is held below

The

the peak ratings

effect

power

of the

and the voltage is less than the collector-emitter

sensor placement

using the test die sketched

array

active
within

SENSORCOUPLING

of thermal

experimentally

was 43X 5.7 roils with

sense emitter.

adequate

sensor detects only 60 percent

that reduces the maximum

rent of the power

by avoiding

and power

peak junction-to-case
temperature
rise; sense delays of
milliseconds
are also observed. The situation deteriorates
rapidly as spacing between the sensor and power elements
increases to several roils, as is frequently
the case. An
electrical

protection

magnitude

in

has not been good enough

alone

right

thermal

extensively

regulators

thermal

sensor and the power transistor

that

safe-area
ratings

II.

limiting

[1][5].

Dynamic
dissipation

INTRODUCTION

ICS, particularly

amplifiers

YAMATAKE

This

sense emitter

Manuscript
received November 25, 1985; revised June 27, 1986.
R. J. Widlar
is an independent
consultant
living at Apartado
Postal
541, Puerto Vallarta,
Jalisco, Mexico.
M. Yamatake
is with National
Semiconductor
Corporation,
Santa
Clara, CA 95051.
IEEE Log Number 8611324.

a notch

for the first

was separated

from

the

emitters by 4.5 roils on three sides. Temperature

the array was 30C with 6-W dissipation
as mea-

sured by a separate sense emitter (not shown) immersed

within
the array. Silicon die t@ckness was 10 roils. A
gold-eutectic
die attach to a 13-mil-thick
molybdenum
interface brazed to a copper heat spreader on a steel TO-3
package completed
the thermal system. Th9 plot shows
that

the temperature

rise at the first

than half the internal

for more remote
Thermal
mated
emitter

Fig.

might

stantaneous

sensor is little

more

rise and falls off rapidly

sensors.

transient

from

temperature
response

2. The

be taken

of this system can be esti-

response

of the internal

as representative

temperature

sense

of the peak in-

of the active emitters.

The adja-

cent sensor is the first in Fig. 1 while the remote

sensor is

separated by 20 roils down the centerline from the power

array. Millisecond
delays in reaching the final temperature
are obtained
source.
Teledeltos

even when the sensor is adj scent to the power

dimensional

solution

the power

resistance
array

paper

was used to obtain

for the temperature

as well

variations

as on the outside.

plotted
in Fig. 3, assume a uniform
power array and a 24-rnil equivalent

voltage.

was evaluated
in Fig. 1. The

a twowithin

The results,

heat flux within the

die thickness, corre-

sponding to the hard die-attach method described above.

These data suggest that the sensor must be immersed
well inside the power array to accurately sense temperature
even when ballasting
is adequate to maintain
uniform
conduction

0018-9200/87/0200-0077$01.00

throughout.
01987 IEEE

Accounting

for three-dimensional

78

[EEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

SC-22,

NO.

1, FEBRUARY

1987

50
I

I
P=6W

40

10

10

40

20

0,2

Fig, 1. Thermal-sensor
temperature
distance
from the power transistor.
with a notch for the nearest sensor.
roils down the centerline.
Die size is

15

rise
The
The
61x

above case as a function

of
power array is 43x 5.7 roils
nine sensors are spaced by 5
75 rnils.

0.6

1.0

0.8

Fig. 4. Temperature
increase above 225C required
to maintain
constant output from a sense transistor when only a fraction of the emitter
area is heated. Zero emitterbase
bias is assumed.

would be an improvement
over former methods but will
not give the absolute protection
of a peak sensor distrib-

INTERNAL SENSOR
,/

0.4

FRACTION AT TEMPERATURE

DISTANCE (roils)

90:

uted throughout

10

the array.

ADJACENT

III.

P-N JUNCTION SENSORS

Although
0
I

J-lLu
o

12

not

perfect,

a p-n junction

is a satisfactory

peak-temperature
sensor. The reverse leakage current increases exponentially
with temperature,
doubli~g
about
every 10 C. Therefore, should a hot spot develop such that
only 10 percent of the junction is heated, the peak temperature would have to rise less than 40C above a uniformly

16

TIME (ins)

Fig. 2. Transient
response of the thermal system sketched in Fig. 1. The
internal
sensor is representative
of power-transistor
thermal response.
The adjacent sensor has a 3-ins delay in approaching
its final temperature. Remote sensor is located 20 roils down the centerline.

heated junction

to give the same leakage current.

The collector
ponentially

with

bias, in a manner
if

1.0

sense

current

of a transistor

temperature,
related

transistor

with

also increases

a fixed

to the leakage current.

limits

ex-

baseemitter

temperature

Therefore,
at

given

emitter-base
voltage and collector current, thermal localization will require equally small increases in peak temperature to effect limiting.
Fig. 4 plots the temperature error in
peak detection
as a function
of the fraction of the transistor emitter being heated. A nominal limiting
tempera-

i>
i=
~
u
K

ture
(V&

equation [8].
An important

0.2

DISTANCE (roils)

Fig. 3. Surface-temperature
profile
for a two-dimensional
IC power
transistor
as modeled
with resistance paper. The curve is scaled to
represent a hard die attach to a molybdenum
spacer in a copper TO-3
package.

temperature

die attach directly

encountered

conductivity

increases the gradients,

to copper [7]. Thermal

in marginally

modify results.
Marginal
ballasting

ballasted

of silicon

as does soft

destabilization

arrays

at
as

can severely

is effected

voids

can cause hot

spots that will not necessarily occur at the center of the

power array. A single sensor in the center of the array

without

and interference.
Minimum
spacing

generating

between

sensor is obtained
by putting
region of the power transistor
the active

or die-attach

in dynamic

safe-area

pro-

a modified
foldback current limit would have to be used.
Minimum
thermal
delay also allows the control
circuit
feedback loop to be frequency compensated so that protection

effects or the decrease in thermal

consideration

tection is that the thermal sensor be located close enough

to the active emitter so that it can control overloads at
maximum
peak current and operating voltage. Otherwise,

elevated

of 2250 C and a zero emitter-base

bias are assumed
>> O). This plot was obtained
by solving the V~~

emitter.

Narrow

spurious

the thermal

oscillations

source and the

a sense emitter in the base

located about 0.4 roils from

active emitters

are required

so

that the heat generation

cannot elect~cally
or thermally
shift away from the sensor. Spacings greater than 0.4 roils
were not investigated.
However, this spacing does allow for

79

WIDLAR AND YAMATAKE: SAFE-ARSA PROTECTION FOR POWER TRANSISTORS

BASE
SPREADING
RESISTANCE

HOT

COLD
P

BASE

N+ INTO P

COLLECTOR

+
EMITTER

,::=TOR

BASE

II

_ACTIVE
EMITTER

(a)

SENSE
EMITIER
\

BASE

N+

CONTROL
OP AMP

(b)

--t
EMITTER

Fig. 5. A distributed
peak-temperature-sensing
transistor can be formed
without
continuous
metal contacts on the base and emitter as shown
here. However,
thermoelectric
voltages can alter performance.
(a) Uncontacted base and emitter. (b) Uncontacted
emitter.

(a)

COLLECTOR
RB2

RBI

both
100

control-loop

stabilization

and capture

times

al

BASE

under

R1

p.s.

Initially,
used

the leakage

to establish

problems

and

thermal

is far better

shifted

the emphasis.
a

+ 15C

production

current

the fact

voltage
hold

With
in

limiting

exclusive

can

temperature

the

over

prob-

caused by stray

nodes also proved

easier.

-t

EMITTER

(b)
Fig. 6. Sense emitter on the power transistor is biased so that VB~- O
at the limiting
temperature.
At this temperature,
the op amp will a sorb
base drive to regulate
temperature.
Uncompensated
base-spreading
resistance can cause positive feedback. (a) Control loop. (b) Compensating for RB2.

EFFECTS

curacy.
Large

IC

problems

transistors

caused largely

Getting
Adding

have

topological

design

collector

contact.

by the topside

current.

the thermal

In principle,
using

the sensor can be included

doped silicon

is done,

parent

sensor can be operated

as a second-level

thermoelectric

potentials

C2MI

at low
into

the

conductor.

If

alter

the ap-

length

a temperature

of a conductor,

gradient

is established

carriers will diffuse

along

toward

above 1 mV/C

A distributed

transistor

metallization

is shown

diffused

a base region

cold

into

end. The

in Fig.

doping

contact

at the cold

stripe

across the length

end, causing

is

of the

VB~ at the hot

a substantial

temperature-sense
error.
A second structure
is shown in Fig. 5(b). A metal
contact is used along the length of the base, but there is
none on the emitter. The Seebeck-voltage error is that of
the emitter
more

lightly

alone.
doped

Eliminating

the Seebeck voltage

base significantly

improves

the temperatureof the junction-to-

rise when the cold end is located

tures along its length.

tion with

the power

the power
Located

Further,

at the

to peak tempera-

it can share base metalliza-

transistor,

array without

so it can be integrated

requiring

additional

in the same base region

into

metal traces.

as the active

can also be optimized

V.

emitters,

as mentioned

earlier.

A functional

of the

sensor ac-

CONTROL

diagram

CIRCUITRY

of the control

loop for peak-tem-

perature limiting
is shown in Fig. 6(a). The sense emitter
within the power transistor is forward biased and operated
at a current that will give VB~ = O at the desired limiting
temperature

made only at the

both increase the apparent

as measured

[9], [10].

emitter

6 percent

periphery
of the power array.
The sensor in Fig. 5(b) does respond

the cold

that does not require

5(a). An

with

Seebeck voltages

base and emitter

end

for light
structure

is about

the

end until an electric field is established that balances the

diffusion
[9]. The resulting voltage is called the Seebeck
voltage and depends on the temperature
differential.
With
metals, the Seebeck coefficient is in the order of 1 pV/C;
with heavily doped semiconductors,
it is about 100 pV/C,
increasing

as can be determined,

error

sensor coupling

VB~ of the sensing transistor.

When

As near

measurement

case temperature

the base lead out of an array is difficult

enough.
thermal-sense
leads is not a welcome challenge.

Fortunately

this

power

Q2

RE

sensing

of severe hot-spot

THERMOELECTRIC

OP
AMP

practical

design,, the latter

oscillations

into high-impedance

R2

was

emitter-base

for temperature

proper

control-loop

IV.

Unresolved

forward-biased

characterized

distribution,

coupling

of the sense emitter

limiting.

that

error

lems. Eliminating

array

BALLAST
RESISTANCE

BIAS
CURRENT

EMITTER

(about

225 C). The differential

op amp are connected

common

isolates

the op-amp

when

the sense emitter

and the op-amp

op-amp
circuitry

output

inputs

the sense emitter

base lead for the sense and power

diode

transistor

between
output

potential

from

of an

and the

transistors.

the base circuitry

is below

that of its base

is high. As the VB~ of the sense

starts to reverse with increasing

temperature,

the

output will drop, taking over control of the base

such as to regulate hot-spot temperature.
.

1Normal
transistor
operation is obtained
zero or even reverse emitter-base
bias
voltage is above a few hundred millivolts.

at elevated tern eratures with

as long as co f ectoremitter

[EEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 1, FEBRUARY 1987

80

COLLECTOR

rents were also a consideration

sistor configuration.
The peak-current-limit

BASE

is also established

in using the inverted-tran-

boundary

by this circuit.

of the safe-area
The voltage

curve

on the base

terminal
is clamped
at 2V~~ plus the drop across R5.
When the drop across the ballast resistance of the modified Darlington
power transistor RI equals
this
voltage,

QI 2

Q12

will

rent.
R5 . :
2.lk: ,

for

conduct,

inhibiting

Although

not

protecting

output

the

capabilities

any

precise,
bond
of

this
wires

the

further

increase

current

limit

while

not

is

in

cur-

adequate

restricting

the

IC.

EMITTER

Fig. 7. Simplified
schematic of the control op amp. Low bias current
for current mirror,
Q and Q6, allows loop compensation
with a small
capacitor
Cl. Inverte 2 transistors are used to minimize parasitic leakage
and capacitance
to substrate.

Base resistance

common

to the sense and power

tran-

sistors is a source of positive feedback in the control loop.

This can be minimized
by using a separate sense contact to
the base near the sense emitter such that the base spreading resistance of the power transistors is shifted outside the
input

circuitry

resistance
ment

shown

produce
in

RI

of

the

compensation
While

of

Any

in

overcompensation
the

Q2

residual

is of

in voltage
The

in

across R ~2

resulting

a polarity

oscillation

to

change
cancel

input.

thermal

transistor

at lower
because

the

Underlimiting

gives a temperature-sense

is most important
power

common

for by using the arrange-

R ~2 as seen at the op-amp

results

Compensation
ages for

amp.

changes across R ~.

collector

across

change

op

in Fig. 6(b). Changes

similar
in

the

can be compensated

error.

collector

volt-

base current

in

thermal limit will be highest. Problems with base spreading

resistance as well as thermoelectric
potentials can be mitigated by biasing the sense emitter in the reverse (leakage)
mode. Even so, forward-bias
operation
appeared to give
more satisfactory
overall results.
A simplified
schematic of an IC control
op amp is
shown

in Fig. 7. It is designed

transistor
into

collectoremitter

obtaining

control-loop

tions with conventional

hysteresis.
with

The object

a minimum

to operate

the power

Some effort

stability

to avoid

thermal

limit

was to provide

of spurious

from

voltage.

was put

the oscilla-

even as controlled
effective

interference

by

protection

or signal distor-

tion.
The differential
input stage of the op amp is formed by
lateral p-n-p transistors Q3 and Q4. The collectors of those
transistors
feed into an inverted transistor current mirror,
Q5 and Q6, with feedback buffered
by QT. The mirror
output from Q6 feeds another buffer Q8, that drives QIO.
Additional

current

gain to take over command

drive is provided by Qlz.

Minimal
operating currents

of the base

were used for Q5 and Q6 so

that the control loop could be compensated with a small

diffused capacitor Cl. The resulting high-impedance
nodes
in the current-mirror
output required the use of inverted
transistors
so that parasitic capacitances would not cause
loop instability
in certain applications.
Tub leakage cur-

VI.
Silicon

MAXIMUM TEMPERATURE

ICS are generally

rated for a maximum

junction

temperature
of 150C. With linear ICS, this is not an
arbitrary limit: most do not function properly above 150 C
because

of

Increased

circuit

temperature
falls

problems

leakage currents
operation.

with

unrelated

are a limiting

Further,

increasing

the

VBE

temperature

to

reliability.

factor

with high-

of

the

transistors

the

collector-

while

VTH rises. If VBE does not exceed

VTH, many popular configurations
like a current mirror or
AVBE current source do not operate properly [11]. ICS can
saturation

threshold

be designed

to operate

performance
mised.

at normal

Bipolar
perature

power

transistors

of 200C.

transistors
rising

200C,

are rated

but

the cost and

are usually

limit.

be biased such that falling

current

compro-

for a junction

This is not a fundamental

can usually

leakage

above

temperatures

can be accommodated

temPower

VBE and

to tempera-

tures approaching
400C.
Further,
no inherent
failure
mechanism was identified in running hermetically
packaged
n-p-n

IC transistors

at 300C

for 5000 h with

bias. Dou-

ble-diffused
n-p-v-n transistors operate properly at temperatures where the collector region is intrinsic;
however, IC
power transistors
collector contact
sic collector
Because
mally

region.
of the substantial

encountered

lish different
sistor

require a sinker diffusion with the topside

if they are to be operated with an intrintemperature

gradients

in power ICS, it is reasonable

maximum

and low-level

temperatures

circuitry.

separate temperature

controllers,

for the power

Implementing

nor-

to estabtran-

this requires

because the package tem-

perature
can approach that of the power transistor with
minimal
heat sinking. Excessive temperature
in the lowlevel
circuitry
could
make
the temperature
limiting
malfunction.
A peak-temperature
limit of 250C for the
power transistor
and 150C for the low-level circuitry has
proven

satisfactory

for ICS in hermetic

VII.

metal cans.

POWER CYCLING

If the thermal-expansion
coefficient of a power package
is substantially
different
from that of silicon, power cycling will cause mechanical stress. For example, if a large
silicon die is rigidly
mounted
to copper, the stress can

WIDLAR

ANIS YAMATAKE : SAFE-AREA PROTECTION FOR POWER TRANSISTORS

cause the die to crack.

This

can be avoided

by using

81
v+

soft-solder die attach that has some give. However, soft die
attach fatigues with cycling [12], Failures beginning
at
3 x 103 cycles with a 70C junction-to-case
temperature

rise are not uncommon.

Molybdenum
as silicon.
silicon

has nearly

It

and copper

eutectic
immune

the same expansion

can be used as an interface

to equalize

die attach
to thermal

Metallization

SHUT

the

stress,, so that a hard gold-

can be used, This

fatigue.

failures

coefficient
between

unrelated

system is virtually

to electromigration

can
-

be

induced

by

copper-doped
glass, failures
cycles with
Reducing
lem.

rapid

temperature

cycling

[13].

With

aluminum passivated with plhosphorosilicate

have been induced in a power IC at 106

a temperature

rise of 175 C in a millisecond.

the rate of temperature

Degradation

begins

with

rise mitigates
cracks

in

Fig, 8. This overvoltage

detector gives a shutdown signal as the B VCEO
of Q1 is approached
based upon the increase in h FE with voltage. The
value of 171, a pinched-base
resistor, is proportional
to h FE at low
voltage.

the prob-

the passivating
metal

oozes

greater

through
the cracks. Ultimately,
failure
occurred
shorting between the emitter and base metallization
power transistor.

from
of the

reverse base current

layer

that

can be observed

VIII.
Although
B V&o,
power

bipolar

transistor.

age is best

Next,

transistors
practical

Protecting

done

can

be

operated

to do this with
a circuit

by shutting

from

it down

above

excessive volt-

as, B V&.

gain.

It

of a transistor

has a negative

of this, an open-base
its voltage

is ap-

resistance

to

characteristic

by leakage currents where gain is

voltage where gain peaks. Because
transistor

will

is above the operational

circuit

is related

shown

in

Fig.

not break down

until

rated

limiting

its emitter

current

to

of Qz can be used to shut down

work

was done
IC

performance

as part

op amp

to deliver

RESULTS
of the development

[6]. The device,

~ 10 A, or 150 W into

represents

a dramatic

of a

as completed,
a 4-fl

load.

is
This

increase over what has

been
accomplished
using
older
techniques.
When
worst-case specifications
and the added stresses imposed
by reactive loads are taken into account, the practical
value of dynamic safe-area protection
becomes even more

8 avoids

processing

sheet resistance

of double-diffused

the problem

by

n-p-n transistors

the

of a pinch resistor is given by R = 30t?~e,2

h ~e is the peak

equation is reasonably
ature range.

ac current

gain

at Vc~ = O. The

valid over a 55 tc) 150C temper-

this relationship,

The data presented

shown in Fig. 9. There

are four

each individually

lasted

power

with

the pinch

resistc)r in the base of

to an emitter

resistor having

a sheet resistance of 30 fi?/cI, independent

of h FE and
temperature.
Thus the bias on the base Q.z will be 0.2V~~
with low-collector
voltage on QI rising to V~E as the h FE
of QI increases to four times its low-voltage
value. This
occurs at approximately
0.95B V&o. With a supply voltage
2Although
this has not been established theoretically,
there is considerable
experimental
evidence
showing
correlation
between
hf.
and
pinched-base
sheet resistivity
within
+30 percent over a wide range of
processing variables.

emitters

per cell,

a polycrystalline-film

sected by a thermal-sense
sistor
nine

resistor.

emitter

the closest power emitter.

is composed
columns

in the array.

resistance

are given

controlled

tranwith

of the power

dissipation

limit of
thermal

at 20 V is 2.2 C/W.
with dynamic

safe-area

in Fig. 10. The pulse capability

obtained

current

power

in columns,

bounded by a peak-curre~t
shutdown
at 85 V. The

for continuous

protection

that is spaced 0.4 rnils

The safe curve

The pulse power ratings obtained

bal-

The cell is bi-

The complete

of 15 cells stacked

transistor is nominally
12 A and a voltage

exceeds that

Q, in Fig. 8 can be translated

here are from an IC power-transistor

design using the basic cell structure

from

B V&o.

operating
the voltage sensor near its current-gain
peak.
Key to its operation is the pinched-base resistor RI. With

Given

thereby

The output

obvious.
breakdown

because it is activated
low, falling to a lower

where

This

monolithic

a conducting

so that it can stand off voltages equal to BVcE~.

The open-base

modern

a safe value.

IX.

sistors.

The

BVCEO, Qg clamps the base of Ql, absorbing

the IC.

Since production
variations in BVCEO can be substantial, it
is desirable that shutdown be activated at a voltage directly related to the capabilities
of the [C power tran-

current

than

OVERVOLTAGE SHUTDOWN

it is rarely

proached

optically.

by earlier

limiting

methods

[4], [5]. With

far

using gradient-

sine-wave

drive to

reactive loads, peak power can exceed four times average.

This power peak has a constant-power-pulse
equivalent of
about one-fifth
the waveform period. Potential
improvements in power capability should be clear.
The transient response of dynamic safe-area protection
under

adverse conditions

is shown in Fig. 11. Peak dissipa-

tion before limit is 900 W, about ten times the continuous

rating. Even so, the protection
circuitry
detects the fault
and effects
less stable

shutdown
in limit

in 150 ps. The control

at lower

fault

voltages

circuitry

under

is

certain

82

JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 1, FEBRUARY 1987

IEEE

COLLECTOR

POLY

POLY

COLLECTOR
R

POLY
RESISTOR
CONTACTS
TO EMl17ERS

BASE
CONTACTS

EMWTERS

SENSE EMITTER

(a)

COLLECTOR

..

BUSSES

20

40

60

COLLECTOREMITTER

60

vOLTAGE (~

Fig. 12.
Guaranteed
specifications
with dynamic
safe-area protection
are not much different
from typicaf.
This illustrates
that tolerance
problems of conventional
techniques can be avoided.

circumstances.
oscillations

There can be considerably

When compared
EMITT{R

BUS

guaranteed

(b)

500

typicals.

to conventional

ratings

most impressive
Fig. 9. Photomicro
raph of the power-transistor
cells used in this study,
Each emitter is baf f asted with a polycrystalline-film
resistor. The thermal-sense emitter bisects the cell, Cells are stacked into vertical columns; adj scent columns complete the power array. (a) Before metallization. (b) After metaf etch,

This

in that they do not differ

is illustrated

distribution

voids

can be eliminated

that

should

be noted

limited

by a maximum

with

that

tested into

niques

TC = 125C

the worst-case

greatly

by good
ratings

junction

are

from the

curve in Fig.

in that it represents

the exception

power

the

of die-attach

workmanship.
on

this

temperature

It

curve

are

of 200C,

not

temperature.

safe-area protection

has the advantage

thermal

or

protection

by the safe-area

production

Dynamic

200

safe-area

12. This curve can be guaranteed

limiting
z
~
~

methods,

of dynamic

the 2250 C thermal-limit

TLIM = 230C

more ringing

in limit.

therlmal

limit,

giving

resistance.

This

differs

where questionable

with its peak-temperature

that parts can be 100-percent

a quantitative
from

indirect

measure of

conventional

methods

tech-

are used.

100

X.
50

I I 111111

I 1111[1

1.0

0,1

I Illlu

Dynamic
100

10

tionary

TIME (ins)

Fig. 10. This graph gives the pulse power required to activate dynamic
safe-area protection
in the time indicated.
The curves suggest that there
is no important
response time limitation.

lithic

safe-area protection

in that

can be considered

the power

capability

ICS by more than an order of magnitude

there is a penalty

of increased

may not pay off in all cases. In order

appreciation
critically
15

it extends

cases. However,
that

APPLICATIONS

with

for the method,

conventional

revolu-

of monoin certain
complexity

to develop

an

it is necessary to compare

it

techniques.

Conventional
protection
uses foldback current limiting
to match the dc safe-area curve of the power transistor. In
practice,
the limiting
current has been subject to a 2:1
tolerance, minimum
to maximum, in the production
distribution

at 15 V. At 30 V, the tolerance

at 50 V it is 8:1.
manufacturers

These tolerances

buildup

is 5:1,

must be inferred

data sheets. Specifying

min/max

and
from

limits

at

15 V is not common; hard specifications

at higher voltages
are rare. When specified, limits are as stated. Worst-case
design cannot take advantage of more than the minimum
but must allow for the maximum with an overload.
Fig. 13 plots the junction
temperature
rise of a power

o
0

02

0.4

0.6

0.8

*.0

TIME (ins)

Fig.

11. The transient

response
gross overload demonstrates

of dynamic
safe-area protection
the effectiveness of the method.

to a

transistor as a function of case temperature in an IC using

conventional
protection.
Thermal-limit
temperature
is

WIDLAR

AND YAMATAKS: SAFE-AREA PROTECTION FOR POWER TRANSISTORS

83

safe-area
rent.

protection

High

voltage

advantage
quently

100

Fig. 13.
Power-transistor
junction
temperature
as a function
of case
temperature
where the thermal sensor responds to one-third the temperature rise. Factors not considered can cause the temperature
to peak at
a much higher value.

the

internal

Foldback

temperature
limit

to 150C.
When there is little
temperature

will

of

sinking

is provided,

however,

hotter

resulting

thermal

power

gradients.

peak-junc-

temperature

the power transistor

must be

sensor to support
temperature

the

in the

power transistor will rise with decreasing ci~se temperature

in thermal limit until the power-limit
curve is intersected.
The worst-case junction
temperature in limit is given by

~~
where

TLIM

fraction

is the

= ~LIM + (1

thermal-limit

temperature,

of the junction

mal-limit

temperature

sensor, 6JC is the thermal

transistor,

to IC applications.
vided

with

operating

resistance of the power

with

the maxi-

Power limiting

curve can drastically

at the high

transistor
must be made large to obtain low-saturation
voltage at high current. The resulting thermal resistance is
low enough that power dissipation
capability
is not a
limiting
factor, and conventional
protection
can give satisresults.

With

higher

protection
bring

thetical
reliability

voltage

regulators,

up the load

under

however,

[1]
[2]

[4]

[5]

[6]
[7]

power

transistors

distributed

would

then

limited

can be pro-

temperature

be provided

sensor.

by

external

CONCLUSIONS

system has been developed

allows
rather

use of

their

full

than those established

curve. As a result,

higher

for power

capabilities

as

by a hypo-

power

ratings

with a given die size. At the same time,

is ~mproved by controlling

peak temperature

devices to be 100-percent

and
tested

conditions.

current

to

Dynamic

R. J. Widlar,
New developments
in IC voltage regulators/
IEEE
J. Solid-State
Circuits, vol. SC-6, pp. 2-7, Feb. 1971.
A. Bondini
and B. Murari, Protection
device for a power element
of an integrated
circuit,
U.S. Patent 3792316,
Feb. 1974.
C. T. Nelson and R. C. Dobkin,
Current
limiting
circuit,
U.S.
Patent no. 3796943,
Mar. 1974.
R. C. Dobkin,
5A regulator
with thermal
gradient
controlled
current limit, in 1979 ISSCC Dig. Tech. Papers, Feb. 1979, pp.
228-229.
P. A. Antognetti,
G. R. Bisio, F. CurateIi, and S. Palara, Threedimensional
transient
thermaf shutdown:
Application
to delayed
short circuit protection
in power Ks,
IEEE J. Solid-State
Circuits, vol. SC-15, pp. 277281, June 1980.
R. J. Widlar and M. Yamatake, A 150W op ampj in 1985 lSSCC
Dig. Tech. Papers, Feb. 1985, pp. 140-141.
R. Castello
and P. Antognetti,
Integrated
circuit thermaf modeling;
IEEE J. Solid-State Circui&, vol. SC-13, pp. 363365, June
1Q7R
-,..

[8]

[9]

[10]
[11]

conventional

enough short-circuit
worst-case

of the die area.

is not necessarily

REFEMNcEs

[12]

may not provide

safe-area

can be guaranteed

portion

alter results. Clearly,

applications
require this sophistication.
A 5-V
for logic supplies is an example. The series pass

factory

that

manufacturered,

[3]

the advantage
of dynamic safe-area protection
is that it
maximizes
the dissipation
rating of a power transistor,
particularly
at higher voltages and under pulse conditions.
Not all
regulator

transistors

of many power ICS

in the secondary-breakdown-limited

of the safe-area

internal

limiting

XI.

n is the

end of the productiofi

distribution
will increase the worstcase temperature
well above 250C. Further, thermal destabilization

Discrete

by permitting
individual
for rated power.

limit.
conditions.

an

protection

rise seen by the ther-

The plot in Fig. 13 is representative

for typical

the total supply

can be several times

Jcpl)

and PD is the power dissipation

mum value of current

safe-area

A new protection

will be
As heat

Junction

are fre-

rise

temperature.

than the thermal

take

transistor.

temperature

equal the steady-state

near the 150C thermal-limit

the peak dissipation

by a heat sink, the case

In this case, junction

limited

sufficiently

the

heat removal

nearly

tion temperature.

rise

is assumed to limit

full

They

circuitry.

on the die that is sensitive to one-third

current

can

protection.

takes up only 10 percent

Dynamic

Thermal
at a location

amplifiers

can occur at levels approaching

Further,

complex,

CASE TEMPERATURE ~C)

150C

cur-

the average. In this kind of service, dynamic

safe-area
protection
can deliver ten times the output power for a
given die size when compared to conventional
methods. In
the example cited earlier, the protection circuitry, although

150

125

power
safe-area

much more start-up

called upon to drive reactive load lines where peak

voltage.

75

class-B

of dynamic

dissipation

50

can provide

[13]

J. S. Brugler, Silicon
transistor biasing for linear collector current
IEEE J. Solid-State Circuits, VOL SC-2,
temperature
dependertce~
pp. 5758, June 1967.
H. F. Wolf, Semiconductors.
New York: Wiley Interscience,
1971,
l-m 9-3-96
%f: R. R-unyan, Silicon Semiconductor
Technology.
New York:
McGraw-Hill,
1966, p. 185.
R. J. Widlar,
A new breed of linear ICS runs at l-volt
levels:
Electronics, pp. 115-119, Mar. 29, 1979.
N. D. Zommer.
D. L. Feucht. and R. W. Heckel. Reliability
and
thermaf
impedance
studies in soft-soldered
power transi;tors~
IEEE Trans. Electron Devices, vol. ED-23, pp. 843-850, Aug. 1976.
A. C. McPherson,
W. H. Weisenberger,
H. M. Day, and A.
Christou,
Effects
of fast temperature
cycling on alurnirium
tid
gold metaf systems:
Reliability Physics, pp. 113-120, 1975.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 1, FEBRUARY 1987

84

Robert 1 Widlar

for

both

Nationaf

was born in November

1937.
He graduated from the University
of Colorado,
Boufder, in 1962 while working for Ball Brothers
Research.
In 1963 he joined
Fairchild
Semiconductor
where he headed line~ IC development.
In 1966
he formed
the Linear
IC Group
at Nationaf
Semiconductor,
Santa Clara, CA, and was respoitsible
for new product
design until
1970.
Since 1974 he has been working as an Independent Consultant,
and he has developed products
Semiconductor
and Linear Technologyduring that

time. He has specialized

tion of standard
linear

in the development,
specification,
and applicaICS since 1963. He designed the first industry

standard
op amps, voltage comparators,
and voltage regulators
afong
with generations
of improvements.
He has over two-dozen
products
in
volume
production,
some for over 20 years. He has pioneered
such
innovations
as the bandgap reference and super-gain transistor as well as
numerous
design techniques that are widely used today. His most recent
work includes low-voltage
micropower
ICS, bandgap curvature
correction, advanced super-gain op amps, and improved class-B amplifiers
and
high-power
techniques.

Mheo Yamatakewas

of their

designs.

His

born in September 1933 in

Fresno,
CA.
He studied
electronics
at the
Hiroshima
TechnicaJ School, Hiroshima,
Japan,
and later in the U.S. Army.
In 1960 he joined Link Aviation,
working
on
aircraft simulators.
In 1963 he went to Fairchild
Semiconductor
where he worked on several integrated circuits, including
the uA709. In 1966
he joined the founding
group at National
Semiconductor,
Santa Clara, CA. He worked closely
with Bob Widlar and later, Bob Dobkin on most
innovations
made significant
contributions
to the

performance
of dozens of products that have become industry standards.
He now has the design responsibility
for severaf advanced linear ICS at
Nationaf
Semiconductor.