if
3 Differential Amplifiers
V1 = Vx + Vpickup
V2 = Vy + Vpickup
where Vpickup is a signal common to both, then
V0 = Ad (V1 V2 ) = Ad (Vx Vy )
Figure 3.2:
Figure 3.1:
3-1
3-2
EEE3068F
provides some very desirable properties such as improved linearity, independence of fluctuations in Ad as a result of temperature).
Opamp circuits usually operate in the kHz frequency range, but some
of the faster opamps can be used in the MHz region.
3.1.1 Terminology
The input terminal labelled V1 or + is known as the non-inverting input
(if V2 = 0 then V0 = Ad V1 ).
The input terminal labelled V2 or - is known as the inverting input (if
V1 = 0 then V0 = Ad V2).
A differential change1 at the inputs refers to a change in Vd = (V1 V2 ).
A common-mode change refers to a change in voltage which is common to
both inputs.
Ideally a differential amplifier should respond only to differential changes at
the inputs. In practical circuit implementations the output is also sensitive
to common-mode changes. For example if we tie both inputs together and
connect the inputs to a signal generator, the output will responds to some
degree.
To characterise the behaviour, it is useful to define two voltage gains:
Ad
Ac
Example
Differential gain
Vout
Ad =
Vd
where Vd is an incremental change in the difference voltage, i.e.
Vd = (V1 V2 ) V1 V2 + Vd
Common-mode gain
Ac =
1
Vout
Vc
3-3
EEE3068F
3-4
EEE3068F
The output voltage is typically arranged to sit at half the supply (VC =
1
V ) for the case when both inputs are grounded.
2 CC
Now consider what happens if a small differential voltage V = V1 V2 (say
less than 100 mV) is created between the input terminals, by increasing V1
V
by V
2 and decreasing V2 by 2 such that V1 V2 = V . The differential
voltage is created in such a way to avoid introducing a common-mode component at the input (i.e. the average voltage is still zero).
The emitter voltages will follow with approximately the same increments,
and so by symmetry, the voltage at node A will not change significantly
(VA V ). Thus we consider VA = 0.
3-5
EEE3068F
3-6
EEE3068F
RC
V /2
V
RC =
re + RE
2 (re + RE )
I2
50mV
50mV
100mV
RC
Vout
=
V
2 (re + RE )
(being half of the gain derived for a single ended common emitter AC amplifier).
Figure 3.4 shows a plot of the currents I1 and I2 as a function of the differential input voltage V . As V increases from zero, the currents I1 and
I2 are initially fairly linear functions of V but eventually flatten as |V |
increases. For larger values of V (a few volts), Q2 will switch off completely, and IEE = I1 (V1 0.6)/(RE + R), rising beyond the operating
value as V1 continues to increase (this plot does not extend that far).
3-7
IEE
2
Figure 3.4: Plot of the collector currents I1 and I2 as a function of the differential input
voltage V .
I1
100mV
Ad =
IEE
V /2
= I1
re + RE
Vout = I2RC =
IC IE
EEE3068F
3-8
EEE3068F
RC
RC
Ad
/
=
Ac
2(re + RE ) re + RE + 2R
CMRR =
re + RE + 2R
2 (re + RE )
R
re + RE
Figure 3.5:
RC
V2
RC =
V2
re + RE + 2R
re + RE + 2R
and
Vout
RC
=
V2
re + RE + 2R
Thus the common mode gain is
Ac =
RC
Vout
=
V
re + RE + 2R
Figure 3.6:
3-9
EEE3068F
3-10
EEE3068F
To improve the CMRR, one can replace the tail resistor R by a current
source which has very high impedance. Observe that as R , Ac 0
and |CMRR| . A practical circuit can achieve a CMRR of 106, with a
well designed current source.
25
= 250
0.1
Ad =
Figure 3.7:
RC
RC
75
Ac =
=
0.5
(re + RE + 2R)
2R
2 72
Thus
CMRR =
30
= 60
(0.5)
3-11
The emitter voltage is biased to a couple of volts above the negative rail.
This ensures that small changes in VBE2 do not significantly affect the current IE3.
The output impedance2 of the current source is about 4 M, which implies
2
RC
re + RE + 2R
R
CMRR
re + RE
Ac =
EEE3068F
VE3 VEE
VB 0.6
=
RX
RX
The output impedance of this BJT current source implementation (with the base at a fixed voltage)
can be shown to be R0 = r0 (1 + (re k RE )/(re k r0 )) r0 (1 + RE /(re + RE )) where RE is the
emitter resistor, r0 is the collector emitter resistor in the small signal model. For a collector current
IC , r0 = VA /IC where VA is the so called Early voltage, specified in data sheets. For a discrete BJT
transistor like the 2N2222A, 100 < VA < 500, and so for a collector current of 2 mA, this would predict
50 k < r0 < 250 k. For r0 = 100 k, RE = 1000 , = 100, re = 25/2 = 12.5 , R0 4.5 M.
3-12
EEE3068F
3.3 DC Amplifier
A non-inverting DC amplifier can be created from a differential amplifier by grounding one input V2 = 0, and feeding the input signal at
V1 .
The output can not swing below the base voltage of Q2, which is zero.
Thus for the case of Vin = V1 = 0, the output is typically designed to
sit at Vout = 12 VCC (by the choice of RC ). A subsequent level shift stage
may be used to remove the 12 VCC offset at the output.
The use of a differential amplifier (with one input grounded) for DC
amplification essentially removes the problem of the 0.6 volt VBE offset present in a single transistor amplifier shown in Figure 3.10, and
compensates for dependence on temperature.
For a fixed collector current, VBE decreases by 2.1 mV/C increase
in temperature. If the temperature increases, the reduction in VBE
forces the collector current (Figure 3.10) to increase, and hence the
output voltage decreases.
3-13
EEE3068F
3-14
EEE3068F
Vin VCC
+
2
2
VCC
2
since Ad Ac .
Figure 3.11:
re + RE re + RE
R
+ I
2
I
I
3-15
VA
1
2
+
re + RE R
VA =
EEE3068F
V1
re + RE
V1
E
2 + re +R
R
3-16
EEE3068F
V1
2
V1
2 .
VBE2
VA
=
re + RE
re + RE
Substituting our expression for VA ,
I2 =
I2 =
Thus
Vout
The gain is thus
2+
V1
(re + RE )
re +RE
R
Figure 3.12:
RC
= V1
re +RE
(re + RE )
2+ R
Vout
=
V1
2+
RC
(re + RE )
re +RE
R
Vout
RC
=
V1
2 (re + RE )
Figure 3.13: Inpedance paths to ground seen looking into the base.
3-17
EEE3068F
3-18
EEE3068F
re =
RE
Zin = 250 k
Note Very much higher input impedance can be achieved using FET transistors. FET input stages are often used in opamps (although FET input
stages have higher voltage noise than BJT input stages).
Input impedance of DC amplifier (by derivation)
Zin =
Since
I1 = I2 =
and Vin V1 , thus
Zin
Figure 3.14:
Vin
Vin
Vin
=
=
Iin
I1/
I1
Voltage Gain
re + RE
= 2+
R
2 (re + RE )
RC ||RL
re +RE
(re
R
Vo
=
Vin
V1
re +RE
2+ R
(re + RE )
2+
Rc ||RL
2 (re + RE )
+ RE )
Input Impedance
(re + RE )
1
R1 C1
3-19
EEE3068F
3-20
EEE3068F
Figure 3.15:
Figure 3.17:
(double ended) A = 2
Figure 3.16:
3-21
RC
RC
=
2 (re + RE ) re + RE
EEE3068F
3-22
EEE3068F
Figure 3.20:
Figure 3.18:
Recall Faradays law, which states that the induced voltage equals (minus) the rate of change of flux cutting a loop, i.e. Vind = ddtm adds in
series with the driving source.
Figure 3.19:
3-23
EEE3068F
3-24
EEE3068F