th

30 July 2013

Robust Async Coverage User Guide

Version 1.1

Robust Async Coverage

Version 1.1

Paper Copies Uncontrolled

The master copy of this document is stored electronically. Any paper copies are only copies, and
are to be considered uncontrolled material.

Organization
MSG Freescale

Project
Async Coverage

Document Title
User Guide

Author
Sandeep Jain

Revision History
Version
Number
1.0
1.1

Date

Description

Author

10th May 2013

30th July 2013

Initial draft.
Updated for preserving reset-mux

Sandeep Jain
Sandeep Jain

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Table of Contents

List of Figures in This Document

i. Reference Documents ........................... 2

ii. Abbreviations used in this document ..... 2
1 Introduction .................................... 3
1.1
Overview ............................... 3
1.2
Features ................................. 3
2 Problem Statement ........................... 3
2.1
Coverage Loss with Test-mode
Gating 3
2.2
Coverage Recovery with ScanEnable Logic ...................................... 4
2.3
Glitches Due to Reconvergence
on Scan-enable Cone ........................... 5
2.4
Glitches Due to Reconvergence
on Async-SE Cone .............................. 6
2.5
Glitches Due to Reconvergence
on Reset Mux ..................................... 7

Figure 2-1 Static Gating of Internally

Generated Reset .............................. 3
Figure 2-2 Async_SE Generated with a
Static Bit and an External Pin SE .. 4
Figure 2-3 Waveforms for Async_SE
Operation ...................................... 5
Figure 2-4 Async-SE updated for SE
Reconvergence ................................ 5
Figure 2-5 Waveforms for Async_SE after
adding Another Qualifier Pin.......... 6
Figure 2-6 Reset-Ripples Created due to
Same Async-SE controlling Cascaded
Resets ............................................ 7
Figure 2-7 Async-SE Split within TCU
Based on 1-cold Decoded Testpoints .. 7
Figure 2-8 Reset Mux broken into
Combinational Gates Resulting in
Glitches .......................................... 8

List of Tables in This Document

Table 2-1 Modes of Operation with AsyncSE.................................................. 4

i. Reference Documents
Document

Description

Path

ii. Abbreviations used in this document

SE
SCR

Scan-enable
Scan Control Register

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1
1.1

Robust Async Coverage User Guide

Version 1.1

Introduction
Overview

The purpose of this architecture is to provide a robust design that can be used to test stuck-at
coverage of faults on internally generated resets/set logic.
The flow uses alternate control signals rather than a single scan-enable pin to excite the faults on
internally generated resets. This removes any possible glitches arising from reconvergent paths
which are fatal for asynchronous pins.

1.2

Features

Following are the salient features of this architecture:

Targets coverage on internally generated set and reset logic
Avoids glitches due to reconvergence on scan-enable and async-SE signals
Reuses scan-in pin during capture to delay the async-SE trigger

2
2.1

Problem Statement
Coverage Loss with Test-mode Gating

In addition to a top-level reset control, a design can have reset logic generated from
combinational decoding of other sequential cells. During scan-mode, if this logic gets random
scan-data, the sink flop can get reset thus corrupting the scan shift data. To avoid this situation,
the combinational logic is gated-off with a static signal (testmode/scanmode) to feed a constant
data during shift as well as capture

Figure 2-1 Static Gating of Internally Generated Reset

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However, using a static signal blocks the observe cone of the combinationl logic, leading to
coverage loss, as seen in Figure 2-1.

2.2

Coverage Recovery with Scan-Enable Logic

Figure 2-2 Async_SE Generated with a Static Bit and an External Pin SE

The coverage loss on functional reset can be recovered, if the gating logic is enabled
only during shift. During capture, the functional values take control of the flop-reset pin.
The scan-enable signal (denoting the shift or capture phase) is gated with a static-bit, so
that this functionality is enabled only in a specific ATPG mode (when reset coverage is
targeted).
Mode
Mode-1
Mode-2

Details
ATPG without targetting reset faults
ATPG targetting reset faults

Mode-3

ATPG targetting functional reset cone

coverage

Configuration
SCR_bit=1, RESET=1
SCR_bit=1,
RESET=0(capture)
SCR_bit=0, RESET=X

Table 2-1 Modes of Operation with Async-SE

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Mode Entry

Load Phase

Version 1.1

Capture

Unload

Reset Pad
Scan Mode
Clock
Scan Enable
SCR Bit
Async-SE

Combo Glitches settle in this window

Figure 2-3 Waveforms for Async_SE Operation

The waveforms in Figure 2-1 shows a window after the clock pulses and before asserting SE,
where all glitches in the combinations logic has settled before the logic is made transparent for
flop reset pin.

2.3

Glitches Due to Reconvergence on Scan-enable Cone

(a)

(b)

Figure 2-4 Async-SE updated for SE Reconvergence

The async-SE logic discussed earlier can still create glitches during capture, if there is
any reconvergence on SE pin, as shown in Figure 2-4(a). SE is typically used to control
various pin-muxing and other muxing logic which can get triggered simultaneously, the
moment SE is asserted.

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To avoid this issue, another qualifying signal is added which allows any transition excited
by SE-assertion to settle down, before making the functional-reset cone transparent. In
order to avoid another top-level pin for this functionality, we have reused 1 of the scan-in
pins which are unused during the capture phase.

Mode Entry

Load Phase

Capture

Unload

Reset Pad
Scan Mode
Clock
Scan Enable
Scan-In Pin
SCR Bit
Async-SE

Combo Glitches settle

in this window

All SE-reconvergence Glitches

settle in this window

Figure 2-5 Waveforms for Async_SE after adding Another Qualifier Pin

The waveforms in Figure 2-1 shows a 2-stage approach that allows any glitch arising from clockpulsing or SE-assertion to settle down before the logic is made transparent for flop reset pin.

2.4

Glitches Due to Reconvergence on Async-SE Cone

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Figure 2-6 Reset-Ripples Created due to Same Async-SE controlling Cascaded Resets

Incase the output of a flop driven by async_SE feeds the functional reset cone of another flop,
there can be ripple effect when async-SE is asserted. The 1st flop would get a reset, once asyncSE is asserted. This would make the functional-reset logic of 2nd flop to be re-evaluated and
update the output of 2nd flop (this behavior was not expected though, during pattern generation).
As the ATPG tools work on a static view of the design, these issues are not detectable during
pattern generation. This can lead to simulation failures when actual timing data is applied.
Sometimes the ripple effect is seen to manifest only at silicon, while the glitch was not seen
during timing simulations.

Figure 2-7 Async-SE Split within TCU Based on 1-cold Decoded Testpoints

In order to avoid the ripple-reset scenario, the async-SE logic is split so that a unique
async-SE signal is generated for cascaded reset cases. The async-SE is gated by
testpoints which are 1-cold decoded, so that only 1 of the flops are at 0, while others
are at logic 1.

2.5

Glitches Due to Reconvergence on Reset Mux

There can be cases where we get a glitch on the reset pin even after taking care of the
reconvergence in the SE and Async_SE pins. These glitches can arise due to reconvergence in the
reset-mux itself, if the logic gets broken in combinational gates during synthesis

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Figure 2-8 Reset Mux broken into Combinational Gates Resulting in Glitches

Inorder to avoid these glitches, we need to ensure that the reset mux gets preserved as
a mux and is never broken into AND-OR gates.
It is recommended that the reset muxing is always done using a mux-instantiation code
in the RTL rather than a combinational statement. The synthesis team can add-in rules
to ensure that these muxes are further preserved as mux during the entire Synthesis/BE
cycle.

X assign muxed_rst = (async_se) ? test_rst : func_rst;

dft_reset_mux

mux_inst (.a(func_rst), .b(test_rst), .sel(async_se), .x(muxed_rst) );

As the mux is a single library cell, there will not be any glitch inside the mux logic. There
should be no special requirement to use any balanced or glitchless muxes for reset
muxing.

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