INTRODUCTION TO PRINTED CIRCUIT
BOARD (P.C.B)
The Printed Circuit Board (P.C.B) is an instantly recognizable symbol of both the beauty
of electronics design and its overwhelming sophistication. A fine P.C.B is a mixture of
high art and solid engineering. It is a synthetic, laminated insulating material to which
copper tracks have been added.
A typical P.C.B consists of 1.5mm (1/16th inch) epoxyglass substrate bonded on both sides
of a 1.0 ounce copper foil (approx. 1.4mils or 0.03mm thickness). The signal, return and
interconnect etched traces are about 1.0mm in width.
A P.C.B is an integral part of electronic devices. Electronic components mounted on a
P.C.B big or small. Besides keeping the components in place P.C.B provides electrical
connection between the components mounted on it.
Printed circuit board can be divided into four types:
1) Rigid board
2) Flexible and RigidFlex Boards
3) Metal Core Boards
4) Injection Molded Boards
The board that is most widely used is the rigid board. The boards can be further classified
density and faster propagation speeds, which stem from the demand for high performance
systems, have forced the evolution of the boards from singlesided, doublesided to multi
layered boards.
On SingleSided Boards, all the inter connections are on one side.
Double Sided Boards have connections on both sides of the board and allow wires to
cross over each other without the need of jumpers. This was accomplished at first by Z
wires, then by eyelets and at present by P.T.H (Plated Through Hole). The increased pin
count of the ICs has increased the routing requirements, which led to multilayer board.
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The necessity of controlled impedance for the highspeed traces, the need for bypass
capacitors, the need for low inductance values for the power and ground distribution
networks have made the requirements of power and ground planes a must in high
layer boards, the P.T.H can be buried, semiburied, or through vias.
MATERIAL USED IN P.C.B:
Properties:
The material used in P.C.B manufacturing should be strong
• Mechanically so as to bear mechanical shocks and vibrations.
• Chemically so as to bear environmental effects.
• Electrically so as to withstand high frequency signal.
• Thermally so as to withstand temperature changes due to heat loss by components
The properties that must be considered when choosing a P.C.B substrate material are their
mechanical, electrical, chemical, and thermal properties. Earlier used was copper clad
phenolic & paper laminate material.
Some special properties of certain material are mentioned below:
Polyamide has longterm thermal rest, low C.T.E (Coefficient of thermal expansion), high
reliability.
Cyanate Ester has low ε and is used in highspeed circuits.
Teflon has lower €, lower dissipation factor, high temperature stability.
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FR4 Epoxy resin impregnated for glass cloth. Rolls of glass cloth are coated with liquid
resin (Astage). Then the resin is partially cared to a semi stable state (Bstage). The rolls
are cut into large sheets and several sheets are stacked to form the desired final thickness.
For a board green is the standard color. While selecting a board material, C.T.E of material
must be matched to that of component material or else the mechanical connections may
break and cause malfunctioning.
Material εr
Polyimide glass 3.9-4.5
Teflon 2.1
Benzocyclobutane 2.6
F.R-4 Epoxy glass 4-4.5
Cyanate Ester glass 3.5-3.9
Ceramic ~10.0
Copper --
Copper/Invar/copper --
CHIP PACKAGES
A chip package is what surrounds the IC die and connect the die's pads to the packages
external pins. Most commonly used packages are:
circuit board.
o Surface Mount Packages : They use surface mount technology and
are compact and prevent the use of through hole.
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SURFACE MOUNT DEVICE (S.M.D)
The main reasons to consider implementation of S.M.T include,
o Reduction in circuit board size.
o Reduction in circuit board weight.
o Reduction in number of layers in the circuit board.
o Reduction in board assembly cost through automation.
o Reduction in trace length on circuit board.
o Shorter signal transit time.
o Potentially higher speed operation.
During the assembly of a throughhole board either the component lead goes through the
hole or they don’t and the component placement machine can detect the difference in force
involved and hence yell for help. During S.M.T such features are absent and accuracy of
component pad design, accuracy of P.C.B artwork and fabrication deposition volume and
accuracy of solder paste deposition, variation in components size from assumed size and
thermal issue, etc.
A few chip packages are as follows:
Plastic Leaded Chip Carrier (P.L.C.C)
circuit package with pin spacing of 0.05" (1.27 mm). Lead counts range from 20 to 84.
PLCC packages can be square or rectangular. Body widths range from .35" to 1.15". The
PLCC “J” Lead configuration requires less board space versus equivalent gull leaded
components, and is a less expensive version of the leadless chip carrier, which is housing
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with flat contacts instead of pin connectors, on each side.
A P.L.C.C device is suitable for use in surfacemount applications or may be installed in a
technology. The motivation for a surfacemount P.L.C.C socket would be when working
with devices that cannot withstand the heat involved during the reflow process.
Low Profile Quad Flat Pack (L.Q.F.P)
L.Q.F.P is a lowprofile rectangular surfacemount component package. Its chip (die) is
bonded to an inner land contact area, primarily a lead frame. External terminals exit
parallel to the seating plane on two opposite sides of the molded, flat package. Low Profile
Quad Flat Pack (L.Q.F.P) packages provide the same benefit of the metric Q.F.P packages,
but are thinner (body thickness of 1.4mm) and have a standard leadframe footprint
(2.0mm lead footprint). L.Q.F.P help to solve issues such as increasing board density, die
shrink programs, thin endproduct profile and portability. Lead counts range from 32 to
256. Body sizes range from 5 x 5 mm to 28 x 28 mm. Copper leadframes are used for the
LQFP package. Lead pitches available for L.Q.F.P package are 0.65mm, 0.5mm, 0.4mm
and 0.3mm.
Third Quad Flat Pack (T.Q.F.P)
Thin Quad Flat Pack (T.Q.F.P) packages provide a spaceefficient packaging solution,
resulting in smaller printed circuit board space requirements. Their reduced height and
body dimensions are ideal for spaceconscious applications, such as P.C.M.C.I.A cards and
networking devices. Most of the Lattice Semiconductor highdensity P.L.D and F.P.G.A
Single In Line Package (S.I.P)
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Short for Single In-line Package, S.I.P, is a type of computer chip packaging that contains
only one row of connection pins, instead of two rows, like those found on a dual in-line
packages.
electronic device package with a rectangular housing and two parallel rows of electrical
connecting pins, usually protruding from the longer sides of the package and bent
downward.
D.I.P may be used for integrated circuits (I.C, "chips"), like microprocessors, or for arrays
of discrete components such as resistors or toggle switches. They can be mounted on a
printed circuit board (P.C.B) either directly using throughhole technology, or using
inexpensive sockets to allow for easy replacement of the device and to reduce the risk of
overheat damage during soldering.
The most common D.I.P have an interlead spacing (lead pitch) of 0.1" (2.54 mm) and a
row spacing of either 0.3 in (7.62 mm) or 0.6 in (15.24 mm). Typical pin counts are 8 or
any even number from 14 to 24 (less common 28) for 0.3 in packages, and 24, 28, 32 or 40
(less common 36, 48 or 52) for 0.6 in packages. Several DIP variants exist, mostly
distinguished by packaging material:
1Ceramic Dual Inline Package (C.E.R.D.I.P)
2Plastic Dual Inline Package (P.D.I.P)
3Shrink Plastic Dual Inline Package (S.P.D.I.P) A shrink version of the PDIP with a
0.07 in (1.778 mm) lead pitch.
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Electrical Programmable Logic Device (E.P.L.D)
E.P.L.D stands for "Electrical programmable logic device” and is an integrated circuit that
comprises an array of programmable logic devices that do not come preconnected; the
connections are programmed electrically by the user.
Thin SmallOutline Package (T.S.O.P)
Thin SmallOutline Packages or T.S.O.P is a type of surface mount I.C package. They are
notably very lowprofile (about 1mm) and have tight lead spacing (as low as 0.5mm).
They are frequently used for R.A.M or Flash memory I.C due to their high pin count and
small volume. However, they are being supplanted by ball grid array packages, which can
achieve even higher densities.
T.S.O.P is rectangular in shape and come in two varieties: Type I and Type II. Type I I.C
has the pins on the shorter side and Type II has the pins on the longer side.
SmallOutline Integrated Circuit (S.O.I.C)
The Small Outline Integrated Circuit (S.O.I.C) is a small surface mount package and is an
excellent choice for maximum board density. It is surface mounted on printed circuit board
and is ideal for the automotive, telecommunications, computer industries, or any industry
that requires dense placement of chips on boards.
A SmallOutline Integrated Circuit (S.O.I.C) is an integrated circuit (I.C) package, which
occupies an area about 30 50% less than an equivalent D.I.P, with a typical thickness that
is 70% less. They are generally available in the same pin outs as their counterpart D.I.P
I.C. This package is shorter and narrower than D.I.P, the sidetoside pitch being 6 mm for
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an S.O.I.C14(from lead tip to lead tip) and the body width being 3.9 mm. This package
has "gull wing" leads protruding from the two long sides and a lead spacing of 0.050
inches.
Complex Programmable Logic Device (C.P.L.D)
A complex programmable logic device (C.P.L.D) is a programmable logic device with
complexity between that of P.A.L and F.P.G.A with architectural features of both. The
building block of a C.P.L.D is the macro cell, which contains logic implementing
disjunctive normal form expressions and more specialized logic operations.
Features of C.P.L.D:
o Nonvolatile configuration memory.
o For many legacy C.P.L.D devices routing constrains most logic blocks to have input
and output signals connected to external pins, reducing opportunities for internal state
storage and deeply layered logic.
o Large number of gates available.
o Macro cells with predictable timing characteristics
o Low cost
The characteristic of nonvolatility makes C.P.L.D the device of choice in modern digital
designs to perform 'boot loader' functions before handing over control to other devices not
having this capability.
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Ball Grid Array (B.G.A)
The B.G.A is descended from the Pin Grid Array (P.G.A), which is a package with one
face covered (or partly covered) with pins in a grid pattern. These pins are used to conduct
electrical signals from the integrated circuit to the printed circuit board (P.C.B) it is placed
on. In a BGA, the pins are replaced by balls of solder stuck to the bottom of the package.
The device is placed on a PCB that carries copper pads in a pattern that matches the solder
balls. The assembly is then heated, either in a reflow oven or by an infrared heater, causing
the solder balls to melt. Surface tension causes the molten solder to hold the package in
alignment with the circuit board, at the correct separation distance, while the solder cools
and solidifies.
Mini B.G.A
In mini B.G.A layers of polyamide and metal are applied to the die to redistribute original
die pads from a peripheral arrangement into an area array configuration.
Advantages
•High density
•Heat Conduction
•Low Inductance leads
Disadvantages
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•Non compliant leads
•Expensive inspection
B.G.A Variants
1C.B.G.A and P.B.G.A denote the Ceramic or Plastic substrate material to which the
array is attached.
2F.B.G.A or Fine Ball Grid Array based on ball grid array technology. It has thinner
9 reasons why B.G.A are preferred…
•Their low profile and small size means that the total loop area, from a signal on the chip,
power/ground pins is very small, as little as 1/2 or 1/3 the size of the same loop on a Q.F.P
or S.O.I.C package of equivalent pin count. This smaller loop area means lesser radiant
noise, and less crosstalk between pins.
ground bumps. Problem with ground bounce diminish in almost direct proportion to the
number of power and ground bumps used.
•Most B.G.A packages have big, fat, easy to work with solder bumps, much bigger than
the ones used for flipchip connections. BY way of contrast, flip chip technique, which
uses solder balls placed directly on the face of a silicon die; require solder bumps with
much smaller dimensions, which can lead to troublesome manufacturing problems. Flip
chip has given the solder ball technique a somewhat dark, mysterious and wholly
undeserved reputation.
•B.G.A packages are study; compare this with a 20mil pitch Q.F.P. On the B.G.A, there
are no leads to bend or break. It’s like a little brick. With a B.G.A package a lot of power
and ground bumps can be placed in the interior bumps, leaving the I/O traces to more
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routable positions around the edges. This is just one of the ways you can use the pre
routing inherent in the BGA substrate to straighten out an otherwise messy I/O routing
situation.
•B.G.A packages are inherently low profile. There is nothing to it but the chip, some
interconnections, a thin substrate, and a plastic encapsulate. No big pins and no lead frame.
The total installed height above your P.C.B can be as little as 1.2 mm (0.05").
•Advanced B.G.A packages can cram all the solder bumps right under the chip, with very
little package overhang. That is as good as can be done for miniaturization.
•The bumps on the bottom look cool, feel neat.
•No fancy technology involved. It's not like direct attach flipchip technology, where you
have to carefully match the thermal coefficient of expansion between the P.C.B and the
chip in order to prevent die cracking. With a B.G.A package, the interconnection matrix
provides sufficient mechanical compliance to relieve thermal stress on the die. No
expansion missmatches and no hassles.
•It is an inherently thin package, with reasonable good cooling properties. With the die
mounted faceup, most of the heat flows down and out through the ballgrid array. In
packages that mount the die facedown, the backside of the die is in intimate contact with
Table: Diagrams and names of few chip packages.
Thin Quad
T.Q.F.P
Flat Pack
Plastic Quad
P.Q.F.P
Flat Pack
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B.G.A Ball Grid Array
Plastic Ball
P.B.G.A
Grid Array
Dual Inline
D.I.P
Package
Plastic Lead
P.L.C.C
Carrier Chip
Thin Small
T.S.O.P
Outline Package
Complex Programming
C.P.L.D
Logic Device
GROUND PLANE
Need for ground plane:
o Reduces interference due to high frequency nets
o Reduces the capacitive effect existing between two electric layers
o Provides return path
o Provides shield to critical signals
o Provides termination for traces
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o Reduces ground bounce
Grounds should be run separately for each section of the circuitry on a board and brought
together with the power ground at only one point on the board. On multilayer boards, the
ground is frequently run in its own plane. This plane should be interrupted no more than
necessary, and with nothing larger than a via or a through hole. An intact ground plane
will act as a shield to separate the circuitry on the opposite sides of the board, and it will
also not act as an antennaunlike a trace, which will act as an antenna. On singlesided
analog boards, the ground plane may be run on the component side. It will act as a shield
from the components to the trace/solder side of the board.
A brief illustration of the issue of interplane capacitance and crosstalk is presented in
figure, which shows the two common copper layouts styles in circuit board design
(cutaway views).
Conductor
plates
d
To define a capacitor C where copper is the conductor, air is an insulator, and FR4 is an
A = area of the "plates"
d = distance between the planes
For a circuit board, the area A of the plates can be approximated as the area of the
conductor/trace and a corresponding area of the ground plane.
The distance d between the planes would then be a measurement normal to the plane of
the trace.
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The impedance of a capacitor to the flow of current is calculated as:
XC =1/2πfC
f= frequency of operation
C= value of the capacitor or the capacitance of the area of the circuit board trace.
Analog Design
The analog design world relies less on C.A.D systems auto routes than the digital design.
Analog design also follows the stages of schematic capture, simulation, component layout,
critical signal routing, noncritical signal routing, power routing and a "copper pour" as
needed. The copper pour is a C.A.D technique to fulfill an area of the board with copper,
rather than having that area etched to bare F.R4. This is typically done to create a portion
of a ground plane.
The first rule of design in the analog portion of the board is to have a ground that is
separate from another ground such as digital, RF, or power. This is particularly important
since analog amplifiers will amplify any signal presented to them, whether it is legitimate
signal or noise, and whether it is present on a signal input or on the power line. Any
digital switching noise picked up by the analog circuitry through the ground will be
amplified in this section.
Digital Design
The first rule of design in the digital portion of the board is to have a ground that is
separate from any other grounds such as analog RF or power. This is to primarily protect
other circuit from the switching noise created each time a digital gate shift state. The faster
the gate, and the lower its transition time, the higher the frequency components of its
spectrum. Like analog circuits, digital circuits should either have a ground plane on the
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component side of the board or a separate "digital” ground that connects only to the other
grounds at one point of the board.
At some particular speed (>40MHz), the circuit board traces need to be considered as
transmission lines. The normal rule of thumb is that this occurs when the two way delay of
propagation time of the signal. Since we assume that electricity travels down a copper wire
or trace at the speed of light, we have a beginning set of information to work with.
R.F Design
RF circuits cover a broad range of frequencies from 0.5 KHz to >2 GHz. Generally RF
designs are in shielding enclosures. The nature of RF means that it can be transmitted and
received even when the circuit is intended to perform all of its activities on the circuit
board. As in the case of light the RF circuits lead to very short band widths, which means
that the RF can leak through smaller openings .This is the reason for shielded enclosures
and the reason that RF I/O uses trough pass through filters rather than direct connections.
DIGITAL CIRCUITS
RF CIRCUITS
ANALOG CIRCUITS
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Fig: Partitioning of Circuit Board
Some Important Terms
Copper Pour:
Copper pour is an area of copper, which partially covers an electrical layer. The copper is
"poured" onto the layer, into an area bounded by a copper pour template, in such a way that
it avoids contact with all electrical items of a different signal. This is a way of creating
partial power planes. More than one copper pour can be put on any single layer. Pads and
routes on the layer may lie within, outside or crossing the boundaries of one or more
partial power planes.
Pad:
A conductive area on the surface of an active substrate, as an integral portion of the
conductive interconnection pattern to which components or test probes may be applied.
Design Rules:
A set of electrical or mechanical rules that must be followed to ensure the successful
manufacturing and functioning of the board. These may include min. track widths and
track spacing, track widths required to carry a given current, maximum length of clock
lines and maximum allowable distance of coupling between a pair of signal lines.
E.M.C (Electromagnetic Compatibility):
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The ability of an electronic product to coexist in its intended electromagnetic environment
without causing functional degradation or damage.
E.M.I (Electromagnetic Interference):
A process by which disruptive EM energy is transmitted from one electronic device to
other through radiative or conductive paths or both.
Net List:
A file of component connections generated from a schematic. The file list, net names and
the pins, which are a part of each net in the design.
Schematic:
A drawing or set of drawings that shows an electrical circuit design.
INTRODUCTION TO CADSTAR
Features:
The CADstar PCB design suite delivers one of the most powerful price/performance
solutions in the world of PC based PCB design. Some features that are incorporated in
CADSTAR are discussed below:
o Total flexibility for EDA environment as well as offering ‘state of art’ P.C.B design
capabilities, the CADSTAR P.C.B design suite provides a broad range of
manual, interactive and automatic routing.
o Unleash the power of CADSTAR
Easy to learn and fast to use, CADSTAR delivers workstation performance on a
P.C.B.
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o The software is highly productive, enabling the user to process design through
system faster.
o CADSTAR P.C.B design editor offers powerful editing suite for the most
challenging and complex design.
Placements:
For designers who like or need to place components by hand, options, which emulate the
Routing:
At the heart of CADSTAR core technology are the CADSTAR embedded route editor and
dialogdriven (standalone) CADSTAR route editor.
GERBER FILE
A Gerber file is a standard file format used by P.C.B (Printed Circuit Board)
fabrication houses that contains information necessary for computercontrolled machines
to draw an exact pattern for circuit boards. These patterns are typically used to assemble
and electrically connect electronic assembly .The pattern usually contains features such as
land patterns, signal traces, drill holes and cutting information.
A Gerber file standard is named after Gerber Scientific Instrument Company, pioneer
in photo plotter manufacturing and a former division of Gerber scientific, incorporated.
P.C.B layout designers using specialized Electronic Design Automation (E.D.A) produce
CADSTAR or ZUKEN CR500 also follows the same standard.
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Since a P.C.B may have many layers, the older Gerber format is RS274D always
assume a setup command file (one for each P.C.B layer) and one for " tool " description
file .The command file (consisting of short command and XY coordinates) were called
"Gerber files" and the tool file were called "aperture files".
Standard for the latter was never established, so every E.D.A software has its own E.D.A
file format that caused problem for the manufacturers. Often the aperture information has
to be reentered manually.
The newer Gerber format RS274X, also known as XGerber or extended Gerber, includes
the aperture information into the file headers. With embedded apertures this makes every
XGerber file complete as to how each P.C.B layer should look. However, there are still
problems with the interpretation of these files such as on polygons, or the question of
which file to use for which layer. Gerber file extensions are often .SPL, .GBR, .ART,
.GBX or .PHA.
OVERVIEW OF THE SYSTEM
Block Diagram
The 'core' suite of CADSTAR programs consists of:
o The Design Editor (which includes the SCM Design and PCB Design
applications);
o The Library Editor;
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o P.R. Editor XR (and its 'high speed' version, P.R. Editor XR HS);
o The Simulation Library Manager.
There are other CADSTAR programs that are cost options – S.I Verify and CADSTAR
3D. Each of these programs has its own icon that can be selected from the Start menu.
The relationship between the 'core' applications is shown below:
SCM Design Editor
Schematic Design is the engineer’s tool for designing the circuit. Logic and Discrete
symbols are added from the Schematic Symbol library. Connections are added between
the terminals on these symbols. This connectivity is maintained right through PCB design
and routing.
The schematic design can be spread over several sheets, with Signal Reference symbols
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maintaining the connectivity between sheets.
It can also be a hierarchical design, where toplevel `blocks' reference lower level circuits.
The schematic symbols can be `generic' (i.e. symbols without related part information), or
`part allocated' with pin numbers and gate allocation.
P.C.B Design Editor
This application enables you to draw a board outline, place the components within the
errors, and to create manufacturing outputs from the resulting design.
We can add components from the P.C.B Component Library direct to the P.C.B design.
specified areas on specified grids.
Routing can be manual or automatic, and can be provided by the separate P.R. Editor
application, or the internal Embedded Router. The Embedded Router provides a subset of
Export is a `What You See Is What You Get (WYSIWYG)' system. This means that the
Colors option (which sets up the visible display on your screen) is important in the
process of creating plots. You can create Check Plots, Artworks, Power Plane Plots, Drill
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Library Editor
The primary use of this application is for graphically managing the Parts libraries (the
Parts libraries are ASCII format files). With it you can:
o Edit existing parts information in the Parts libraries;
o Create new parts;
o Enable and disable Parts libraries;
o Update the Parts Index file (parts .idx) after you have created or modified a Parts
library;
We can also edit the contents of the Symbol/Component/Documentation Symbol libraries
from this application.
P.R. Editor XR
P.R. Editor XR is a graphical automatic and interactive tool for routing the connections on
your design and for modifying the placement of your components. At its heart is an
advanced routing engine' which is controlled by the P.R. Editor interface. Note: The
Embedded Router and the Auto Router option in P.C.B Design also use this routing
engine.
P.R. Editor enables us to carry out sophisticated routing tasks on your P.C.B. Not only
does it allow us to carry out the multipass routing tasks (also provided by the Embedded
Router and Auto Router options in P.C.B Design), it also allows us to automatically create
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Test points, and Component Breakout patterns (Footprints).
P.R. Editor also provides us with sophisticated tools for manual routing, enabling us be
warned of error situations, to automatically add teardrops, to create memory patterns.
P.R. Editor also enables you to move your components to new positions, using indicators
that automatically tell us when the shortest connection lengths are achieved.
The inputs/outputs to/from P.R. Editor are:
o RIF files (that describe the connections and routes);
P.R. Editor XR HS
P.R. Editor XR HS is the highspeed version of P.R. Editor XR. It has the same interface,
but with the addition of several highspeed options (e.g. Crosstalk, Shield Route,
Lengthen). It also has two options that enhance interactive manual routing:
Routing Head up monitors impedance, overshoot and crosstalk and indicates, using
'traffic' lights, whether you are violating the limits you have set up.
CharZ Calculator enables you to access the correct Route Widths to use to match net
and pin impedances.
Its inputs/outputs are:
o RIF files (describes the connections and routes in your design);
o FIF files (describes the component placement on your design);
Constraint Manager
This is a separate application with its own window. It is displayed initially when you call
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up P.R. Editor XR HS. It is used to set up the parameters that control several aspects of
the highspeed operations. For example, you can use it to set up the Min and Max Zo
(Impedance) allowed, the Min and Max Delays along routes, the Max Crosstalk allowed.
You can ask the system to calculate whether the values you have entered will be violated
by your design again it uses colors to indicate violations.
Simulation Library Manager
The Simulation libraries contain Models that simulate the behavior of pins on parts, thus
enabling the P.R. Editor XR HS to calculate Overshoot and display the correct pin
symbols on the Tree View in the Constraint Manager. The Simulation Library manager
provides an interface for managing the libraries that contain these models. You can
modify existing models, and import new ones in the format of I.B.I.S files.
Schematic Symbol/ Component Symbol/ Documentation
Symbol Editors
These applications are for creating the symbols used by the Schematic and PCB Design
applications. The symbols you create are stored in libraries. Related parts in the Parts
library reference both Schematic and P.C.B Component symbols:
In this way, Schematic symbols and P.C.B components are allocated parts information
such as pin numbers, gate and pin swapping rules, etc.
Documentation symbols are nonelectrical symbols that can be added to your designs (e.g.
company logos, drawing templates).
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ECO Update and Back Annotation
ECO Update (an option on the File menu in P.C.B Design) automatically feeds forward
Engineering Change Orders such as new components and additional nets to the P.C.B
design.
Back Annotation (an option on the File menu in Schematic Design) automatically
incorporates P.C.B changes such as component renames, and gate and pin swaps into
the Schematic design.
P.C.B Transfer
The P.C.B Transfer process (an option on the File menu in Schematic Design) converts a
schematic design into the format required by the P.C.B Design program. The schematic
symbols are automatically assigned their appropriate component `footprints' (provided
they have been allocated part information). The components are superimposed at X0 Y0
on the P.C.B design, ready for you to place.
What Is E.M.C?
E.M.C or Electromagnetic Compatibility is the ability of the system, component, P.C.B, to
function as designed or without malfunctioning, in real conditions.
E.M.I or Electromagnetic Interference is any signal, which contains unwanted conductor
or radiator signal, which can degrade the performance of the system, subsystem,
component or P.C.B.
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Worldwide E.M.C regulations set strict limitations on electromagnetic emissions from
electromagnetic interference.
Interference is either conducted or radiated:
Why Analyze For E.M.C?
equipment, have the unwelcome side effect of producing increased levels of
electromagnetic emissions. International guidelines have been established in order to keep
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electromagnetic emissions down to an acceptable level.
Rules for Analyzing E.M.I / E.M.C
Impedance Profile Rule
o Areas of high characteristic impedance give higher emissions.
In order to reduce E.M.I and Susceptibility for a design, it is good practice to reduce the
inductance and increase the capacitance of the signal tracks.
The characteristic impedance of a transmission line is approximately:
So, to reduce the impedance, one needs to increase the capacitance (C). One can increase
the capacitance of a track by shielding it, or by altering the dielectric between the track and
the Power plane
XY Tracking Rule
Route segments on the adjacent layers of multilayer boards should run at right angles to
coupling between routes on adjacent layers:
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Layer Stack
The Layer Stack defined for the design affects the following rules:
•Closed Loops
•Open Loops
•Impedance Profile
•XY Tracking
•Track Stubs
•Track Resonance
•Return Loops
•Layer Stack
•Overlapping Planes
•Termination
•Track Mitering
•Crosstalk
•Impedance
•Field Solver
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The Layer Stack is set up by the Layers option on the Settings menu.
The Layer Stack is the system of layers you have set up in your design technology. In
particular it considers the physical construction of your board, considering the materials,
permittivity, and thickness of the layers making up the board.
For example:
Some of the designs may make use of multiple Power planes at different voltages.
It is not good practice to overlap the planes of different voltages (this can lead to
undesirable noise current distribution throughout the system):
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It is also good practice to overlap corresponding Power planes (this gives additional
capacitive decoupling)... For example, the 5 Volt plane and its corresponding Ground
plane):
Overlapping Ground planes are capacitively coupled to each other so noise can transfer from
one to another.
In addition, large copper areas are excellent radiators of E.M.I so it is good practice to
prevent high frequency signals from appearing on Ground planes.
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Track Resonance Rule
As the timelength of a route (given by the delay along the track) approaches a multiple of
a quarter of the signal wavelength (or a harmonic of that signal), its efficiency as a
radiating antenna increases.
This increases the electromagnetic radiation from the route, and also enhances the route's
susceptibility to externally generated electromagnetic interference. Thus track resonance
should be avoided.
Component Decoupling Rul e
Appropriate decoupling of active components reduces component noise and power plane
transients.
Reducing the voltage transients on power supply connections reduces emissions from the
signal loops formed by the power connections.
Although circuit conditions affect the choice of decoupling capacitor to a certain extent,
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the technology of the device being decoupled is the most important factor in the choice of
capacitor and method of decoupling.
Hence, we normally use the same decoupling capacitor each time you use a particular
component in the design.
Termination Rule
High frequency nets with long routes should be terminated to avoid extra high frequency
harmonics.
Each track has a critical length above which reflections are a maximum, and below which
they are reduced. This critical length occurs when the roundtrip delay time along the track
is equal to the risetime of the signal. It is recommended practice to terminate lines whose
length is close to or above this critical value.
A typical termination is shown below:
Track Length Rule
High frequency signal tracks should be as short as possible.
Long routes, particularly those that operate at high frequencies and edge rates, generate
E.M.I. Long routes are also more susceptible to E.M.I.
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Track Mitering Rule
Electromagnetic emissions are more concentrated on the right angled corners, especially
on high speed nets. Mitering is replacing right angled corners with angled segments at 45
degrees. Mitering reduces trace lengths, reduces high frequency signal reflections and
minimizes the effect of acid traps. Track mitering helps to reduce the number of sharp
corners and therefore the electromagnetic emissions. Two examples of mitering are shown
below:
Closed Loop Rule
A tracking loop constitutes a loop antenna for E.M.I. Radiation is generated in the plane
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of the loop. Closed loops always use more than one layer and the tracks cross over another
segment of the same net, as shown in the diagram below. The intervening plane acts as a
local return path for the loop signals, greatly reducing radiation from the loop.
Open Loop Rule
A tracking loop constitutes a loop antenna for E.M.I. Radiation is generated in the plane
of the loop. The area and frequency of operation, and signal amplitude on each loop, are
determined.
Track Stub Rule
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Stubs (branches from the main routing path) cause unwanted reflections and hence H.F
harmonics if they exceed a critical, maximum stub length. This generates additional
electromagnetic interference, causing signal distortion. Thus the stub length should be
minimized.
Return Loop Rule
There should be an appropriate ground return within a specified distance of each signal
(the default is 2 millimeters).
To reduce costs, a twolayer board is preferable to a fourlayer board.
If transmission lines are not an issue, you can carefully arrange the ground return paths to
allow twolayer boards to be used:
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introduce Ground planes for the purposes of screening and controlling the impedance. The
use of planes inevitably means a minimum of four layers.
Current Rule
The amount of current that can be carried by the design depends on the width of the
tracks used on that design. There must be sufficient track width on your board to support
the current it is expected to carry.
Thus, optimum current should be passed through the conductor.
Power Plane Impedance Rule
A Ground or Power plane may become excessively perforated by throughhole pins, vias
and thermal relief cutouts in a particular area. This has the effect of increasing the
resistance of the plane in that area, and the impedance of the total plane. This can result in
transient conditions on the board, leading to increased E.M.I.
Component Placement Rule
Highspeed components should be nearest to power sources to reduce transients.
For boards without Powerplanes, the power connections form a signal loop in the design.
If you keep high speed and high power components as close to the power source as
possible, you will reduce these signals; loop areas and hence reduce the radiation from the
power routes.
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Components with a highspeed factor should be placed close to power sources and
components with lower speed factors further away from power sources:
CROSSTALK
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Crosstalk is caused by parallel, or near parallel, tracks on the same board layer or on
adjacent board layers. A change of state on one line causes interference on another due to
mutual capacitance and inductance between the lines. The net causing crosstalk is known
as the active net. The net receiving (picking up) the crosstalk is called the passive net. The
active signal is the signal on the active net. The E.M field couples adjacent transmission
lines.
Coupling depends on:
o Distance between the traces
o Distance to the reference plane
o Dielectric material
o Thickness, width of the traces
o Coupled length
o Rise/fall time of the signal
Crosstalk can be Capacitive, Inductive or Radiative.
Capacitive (electrostatic) when transmission lines are parallel on adjacent planes
It can be minimized by:
o Restricting routing on adjacent planes to right angles
Inductive (magnetic) when transmission lines are parallel on same plane
It can be minimized by:
o Restrict parallelism to < the critical length
o Adjust board stackup
o Adjust tracetrace clearance and trace width
o Shielding the critical net
There are two types of crosstalk:
1. Backward Crosstalk:
This is usually the dominant form. The backward crosstalk signal travel down the passive
line in the opposite direction to the active signal. It is always of the same polarity as the
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active signal:
2. Forward Crosstalk:
This is a secondary effect, which occurs predominately on the outer board layers. The
forward crosstalk signal travels in the same direction as the active signal, and is usually of
opposite polarity.
Isolated Copper Area Rule
A common way to reduce emissions is to fill spare areas of each layer with copper, thus
providing an effective screen to all signal tracks on the layer. However, these areas of
copper can act secondary radiators of E.M.I and should always be connected to a power
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plane:
Secondary radiators can couple to a nearby net purely by virtue of its proximity, and
resonate in sympathy with the signals on that net.
So, while the nets itself may not be of the correct dimensions to radiate, it may couple to a
secondary radiator whose dimensions are a multiple of the wavelength of the signal on the
net. In this situation, the secondary radiator acts as a antenna and transmits the signal as a
electromagnetic wave.
Hence we should check every copper area in the design to see if it is connected to a signal.
by other signals. The critical net can be shielded by ground as shown in the following fig.
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NEED OF HIGH SPEED CIRCUIT
Not long ago, the major T.T.L logic families all had typical rise and fall times that, by
modern standards were very slow on the order of 10ns. Products that use these old chips
have few problems with ringing or crosstalk. Today’s digital logic operates much faster
with rise and fall time of the order of 1ns or less. As chips continue to shrink, and as
switching speed continue to improve by a factor of two every few years, we will soon see
rise and fall times slink down into the deep subnanosecond realm, a territory previously
reserved for U.H.F and microwave engineers. This relentless, shrinking trend towards sub
nanosecond rise times brings us to the crux of the problems: Faster switching exaggerates
problems with ringing and crosstalk. Over the years, as logic outputs have continued to
switch faster and faster, problem with ringing and crosstalk have gotten progressively
worse.
TRACE BANDWITH
Every trace has a signal bandwidth, where signals are transferred with acceptable results,
and a cutoff region, where undesired effects may occur; the curve here shows the
frequency response for an ideal trace. As shown the response is flat in the operating
region, then rolls off gradually in the cutoff region.
In a typical P.C.B trace (bottom graph) resonance can occur at high frequencies. This
uncontrolled resonance can create havoc in a wideband circuit and can be difficult to
curve.
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Possible solutions are:
•Eliminate branches and nodes on P.C.B traces. This may be impossible on clock nets,
which have to be distributed to several devices. In this event, buffer may be needed, which
add to circuit delay.
•Ensure all traces are terminated in there characteristic impedance and run over unbroken
ground plane. This goes without saying in highspeed design, and it requires careful
attention to trace dimension and fabrication processes.
•Keep traces as short as possible. This leads to the same considerations as in trace delay
discussed above.
•When necessary, use coax for critical signals instead of P.C.B traces.
PARASITIC OSCILLATIONS
Transistors, OpAmp, F.E.T and analog I.C including simple voltage regulators, can
exhibit parasitic oscillations. This is usually a layout problem caused by the invisible
inductance and stray capacity in each trace.
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The graph bellow shows the effect of a parasitic oscillation in an amplifier. The input
signal is shown in first figure and the output is shown in second figure.
Note the oscillation can come and go with different operating conditions.
Some symptoms of parasitic oscillations are:
•Erratic operation when a hand is waved nears the circuit, or cables are moved or touched.
•Excessive noise or distortion in the output.
analyzer, and communication circuits.
•Erratic circuit behavior when signal parameters are changed.
Trace Delay
Earlier we ignored time the time delay as signals propagated along PCB traces. Today, this
delay can account for over half the total delay in a design. Trace delay may make it
impossible to use a design, component placement may be limited by physical size, and if
the components can't be mounted close together, excessive trace delay may cause timing
failure in some circuits.
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Comparing the two graphs given above for a simple "Dlatch” where the input signal D,
clock (clk) and Q the output, the circuit fails due to extra delaying in the second case.
When a design fails due to excessive trace delay some alternate solution may be
• Simplify the design
# this is the preferred solution. If the design goals can be met by eliminating critical
timing specifications, it usually reduces costs and givers a more robust design.
# If a separate gate is available, and if it is located in a suitable package, it could be used to
add delay to a critical signal to help meet timing requirements.
# Motorola E.C.L I.C. E.C.L logic is a temperature compensated for propagation delay, but
other logic families may not have this advantage. Guaranteeing the design will meet specs
over the temperature and supply voltage may be difficult.
•Choose smaller packages so they can be moved closer together.
# This may mean a redesign since smaller logic devices may not have the same functions
that are available in larger ones.
# It also may increase junction temperatures and reduce reliability, since the heat is
dissipated in a smaller region.
•Use hybrid.
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# It will increase cost, as hybrids are more expensive and difficult to manufacture.
# Temperature may become a serious problem.
# Yields may suffer, since limited facilities are available to test devices before they are
mounted in the hybrid.
•Design a custom integrated circuit. #
It is the most expensive option, but, depending on the circuit topology and clock speed,
there may be little choice. However, this raises a host of new problems, such as floor
planning, electro migration, crosstalk and timing delay.
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SIGNAL INTEGRITY
Introduction to Signal Integrity (S.I)
The term Signal Integrity (S.I) addresses two concerns in the electrical design aspects –
the timing and the quality of the signal.
o Does the signal reach its destination when it is supposed to?
o And also, when it gets there, is it in good condition?
The goal of signal integrity analysis is to ensure reliable highspeed data transmission. In a
digital system, a signal is transmitted from one component to another in the form of Logic
1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver,
voltage above some reference value is considered as logic high, while voltage below the
reference value considered as logic low.
Where S.I Problems Happen?
Since the signals travel through all kinds of interconnections inside a system, any electrical
impact happening at the source end, along the path, or at the receiving end, will have great
effects on the signal timing and quality. The chip package could be single chip carrier or
MultiChip Module (M.C.M). Through the solder bumps of the chip package, signals go to
the Printed Circuit Board (P.C.B) level. At this level, typical packaging structures include
daughter card, motherboard or back plane. Then signals continue to go to another system
component, such as an A.S.I.C (Application Specific Integrated Circuit) chip, a memory
module or a termination block. The chip packages, printed circuit boards, as well as the
cables and connecters, form the socalled different levels of electronic packaging systems.
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In each level of the packaging structure, there are typical interconnects, such as metal
traces, vias, and power/ground planes, which form electrical paths to conduct the signals.
system.
S.I analysis
Comparison studies
S.I analysis
Find solution space
by simulating corner
cases
SI analysis
S.I analysis
Pre-layout analysis
Pre-layout analysis
SI analysis
S.I analysis
Simulation of of reflection,
Simulation
crosstalk, SSN
reflection, crosstalk,
SSN
SI analysis
Post-layout
S.I analysis simulation
Post-layout
simulation
Meet S.I
Conditions
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Successful design
S.I Issues in Design
“Timing” is every thing in a highspeed system. Signal timing depends on the delay caused
by the physical length that the signal must propagate it also depends on the shape of the
waveform when the threshold is reached. Signal waveform distortion can be caused by
different mechanisms but the following are mostly considered.
Rise Time and S.I
Since many SI problems are directly related to dV/dt or dI/dt, faster rise time significantly
worsens some of the noise phenomena such as ringing, crosstalk, and power/ground
switching noise. Systems with faster clock frequency usually have shorter rise time;
therefore they will be facing more SI challenges.
Transmission Lines, Reflection, Crosstalk
In S.I analysis, since the electric models for many interconnects can be treated as
transmission lines, it is important to understand the basics of transmission line theory and
get familiar with common transmission line effects in highspeed design such as crosstalk,
resonance, reflection, ground bounce, termination, impedance mismatch, etc.
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Power/Ground Noise
Transient currents drawn by a large number of devices (corelogic, offchip drivers)
switching simultaneously can cause voltage fluctuations between power and ground
planes, namely the simultaneous switching noise (S.S.N), or DeltaI noise, or
power/ground bounce. S.S.N will slow down the signals due to imperfect return path
constituted by the power/ground distribution system. It will cause logic error when it
couples to quiet signal nets or disturbs the data in the latch. It may introduce common
mode noise in mixed analog and digital design.
S.I in Electronic Packaging
Technology trends toward higher speed and higher density devices have pushed the
package performance to its limits. The clock rate of present personal computers is
approaching gigahertz range. As signal rise time becomes less than 200ps, the significant
frequency content of digital signals extends up to at least 10 GHz. This necessitates the
fabrication of interconnects and packages to be capable of supporting very fast varying and
broadband signals without degrading signal integrity to unacceptable levels. While the
chip design and fabrication technology have undergone a tremendous evolution: gate
lengths, having scaled from 50 µm in the 1960’s to 0.18 µm today, are projected to reach
0.1 µm in the next few years; onchip clock frequency is doubling every 18 months; and the
intrinsic delay of the gate is decreasing exponentially with time to a few tens of Pico
seconds. However, the package design has lagged considerably.
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With current technology, the package interconnection delay dominates the systemtiming
budget and becomes the bottleneck of the highspeed system design. It is generally
accepted today that package performance is one of the major limiting factors of the overall
arrival of gigabit networks, and the need for broadband Internet access, necessitate the
transmission inside every electronics system. Signal integrity is one of the most important
factors to be considered when designing these packages (chip carriers and P.C.B) and
integrating these packages together.
Principles of S.I Analysis
A digital system can be examined at three levels of abstraction: logic, circuit theory, and
electromagnetic (E.M) fields. The logic level, which is the highest level of those three, is
abstraction, comprise the foundation that the other levels are built upon. Most of the S.I
problems are E.M problems in nature, such as the cases of reflection, crosstalk and ground
bounce. Therefore, understanding the physical behavior of S.I problems from E.M
perspective will be very helpful. Even though E.M full wave analysis is much more
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accurate than the circuit analysis in the modeling of packaging structures, currently,
common approaches of interconnect modeling are based on circuit theory, and SI analysis
is carried out with circuit simulators. This is because field analysis usually requires much
more complicated algorithms and much larger computing resources than circuit analysis,
and circuit analysis provides good S.I solutions at low frequency as an electrostatic
approximation.
Typical circuit simulators, such as different flavors of SPICE, employ nodal analysis
and solve voltages and currents in lumped circuit elements like resistors, capacitors and
circuit element. For instance, a piece of trace on the printed circuit board can be simply
modeled as a resistor for its finite conductivity. With this lumped circuit model, the
voltages along both ends of the trace are assumed to change instantaneously and the travel
time for the signal to propagate between the two ends is neglected. However, if the signal
propagation time along the trace has to be considered, a distributed circuit model, such as
a cascaded R L C network, will be adopted to model the trace. To determine whether
the distributed circuit model is necessary, the rule of thumb is – if the signal rise time is
comparable to the roundtrip propagation time, you need to consider using the distributed
circuit model.
In summary, as the current highspeed design trend continues, fast rise time reveals the
distributed nature of package interconnects. Distributed circuit models need to be adopted
to simulate the propagation delay in SI analysis. However, at higher frequencies, even the
distributed circuit modeling techniques are not good enough, full wave electromagnetic
field analysis based on solving Maxwell’s equations must come to play. As presented in
later discussions, a trace will not be modeled as a lumped resistor, or an RLC ladder; it
will be analyzed based upon transmission line theory; and a power/ground plane pair will
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P.C.B Simulation
A traditional boardlevel digital design starts with the creation of a schematic at the level
of components and interconnects. The schematic is passed to the board designer in the
form of a netlist. The design is laid out, prototyped, and then verified. Simulation is
intended to precede the prototype stage and find problems before they are committed to
hardware. In this scenario, the schematic design/netlist is passed to the simulator, along
with definitions of power supplies and required stimulus. The simulator has libraries of
parts that ideally will include all parts used in the schematic. If not, the design team must
create the part specifications and provide criteria such as amplification, frequency
response slew rate, logical function, device timing constraints such as set up and hold
times and line and load regulations.
Simulation results are presented in both graphical and textual forms. Simulator helps to
design correctly even in presence of low power supplies. One of the most difficult things
is timing delays and effects of parasitic inductance and capacitance. Digital circuits
involve fault simulation, which aims to determine all possible faults such as solder short
between traces and ground. So as to support the highspeed model circuitry the I.B.I.S
model (I/O Buffer Information Specification) can now be purchased. The I.B.I.S standard
also includes transmission line descriptions to perform signal integrity simulation. This
part of I.B.I.S is termed as E.B.D (Electrical Board Description).
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I.B.I.S
The Input/Output Buffer Information Specification (I.B.I.S) is an emerging standard used
to describe the analog behavior of the Input/Output (I/O) of a digital Integrated Circuit
information. With I.B.I.S, simulation tool vendors can accurately model compatible
accompanying industrial competition has resulted in the need for new descriptive models
of integrated circuit drivers and receivers. These models should be nonproprietary and
capable of maintaining suitable accuracy and speed in the simulation of transmission lines
and signal integrity related effects such as crosstalk and power/ground bounce (noise).
Simulation of digital I/O buffers, together with their chip packages and printed circuit
boards, can mainly be done in two ways. The traditional approach is to use transistor level
network is the objective of the simulation. This approach would be very time consuming
for simulations of large number of buffers and their interconnections. Transistor level
models may also reveal vendor's proprietary device information. As a solution to this
(I.B.I.S) are introduced. The behavioral I.B.I.S modeling data can be derived from
measurements as well as circuit simulations. Simulations with behavioral models can be
generally executed faster than the corresponding simulations with transistor level models.
A behavioral device model does not reveal any detailed and sensitive information about the
design technology and the underlying fabrication processes, so the vendor’s intellectual
property would be protected.
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The behavioral I.B.I.S based models of a device provide the D.C current vs. voltage curves
along with a set of rise and fall time of the driver output voltage and packaging parasitic
information of the I/O buffer. It should be noted that the I.B.I.S modeling data itself does
not provide explicit information on driver transient state transitions beyond the steadystate
IV curves. The extraction of the transient state transition of buffers is necessary for
correct S.I simulations.
REFRENCE
WWW.CADSTARWORLD.COM
WWW.IPC.COM
PCB Design Tutorial by David L.Jones.
The Electronic Packaging Handbook by Glenn R. Blackwell.
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CONCLUSION
My six weeks training under PAG (Product Assurance Group) was successful. I
learned about P.C.B. layout design in CADSTAR (Ver. 9.0) software over here, I hope
this will be useful ahead in my professional life. My experience at D.E.A.L Dehradun
was good. Rather of just sharing technical knowledge DEAL staff had shared there
valuable work experience too.
To my best known the past six weeks will be valuable in my future life. These days are
really precious for me and will be last in my memory.
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