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Dept.

of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Course Plan
Semester: 1st Semester, M.Tech, VLSI Design and Embedded systems
Course Title:

Course Code:

Modeling of Digital
Systems using VHDL

15VDE111

Total Contact Hours: 52

Duration of SEE: 03 hours

SEE Marks: 50

CIE Marks: 50

Lesson Plan Author: Mr. Pradyumna G.R.

Date: 19-09-2015

Checked By: Mr. Pradyumna G.R.

Date: 19-09-2015

Prerequisites
1. Digital Electronics.
2. Very High Speed Integrated Circuit Hardware Descriptive Language
Course Learning Objectives (CLO):
After studying this Course, the student should be able to:
1
2

3
4
5

6
7
8

Get an insight to the fundamentals of digital logic using Very High


Speed Integrated Circuit Hardware Descriptive Language (VHDL).
Work on various programs starting with design of basic gates to design of

sequential circuits as well as combinational logic circuits using VHDL.


Design networks involving arithmetic operations using VHDL language.
Analyze and design standard combinational modules.
Get an insight to the specification, organization and Implementation of
RTL systems.
Understand data and control subsystems and design it.
Analyze the specifications and implement a microcomputer system.
Learn to design a RTL system for the specifications mentioned.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Course Content
Course Code: 15VDE111
Course Title: MODELING OF DIGITAL SYSTEMS USING VHDL
Teaching Hours: 52Hrs
UNIT- I

L-T-P: 4-0-0
CIE: 50
SEE: 50

INSIDE VHDL: Introduction to VHDL, Specification of combinational systems using VHDL,


Basic language element of VHDL, VHDL description of gates, Behavioral Modeling, Data flow
modeling, structural modeling, Subprograms

10 Hrs

UNIT -II
DESIGN OF NETWORKS FOR ARITHMETIC OPERATIONS: Design of a Serial Adder
with Accumulator, State Graph for Control Network, Design of a Binary Multiplier,
Multiplication of a Signed Binary Number, and Design of a Binary Divider with VHDL
Codes .
08 Hrs
UNIT-III
STANDARD COMBINATIONAL MODULES: Binary decoder, Binary encoder, multiplexers
and de-multiplexers, shifters.
REGISTER-TRANSFER LEVEL SYSTEMS: Execution Graph, Organization of System,
Implementation of RTL Systems, Analysis of RTL Systems, and Design of RTL
Systems.
12 Hrs
UNIT-IV
DATA AND CONTROL SUBSYSTEM: Data Subsystems, Storage Modules, Functional
Modules, Data paths, Control Subsystems, Micro programmed Controller, Structure of a micro
programmed controller, Micro instruction Format, Micro instruction sequencing, Micro
instruction timing
10 Hrs
UNIT-V
SPECIFICATION AND IMPLEMENTATION OF A MICROCOMPUTER: Basic component of
a micro system, memory subsystem, I/O subsystem, Processors, Operation of the computer and
cycle time.

Text Books:

12 Hrs

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

T1. M. Ercegovac, T. Lang and L.J. Moreno, Introduction to Digital Systems, Wiley, 2000
T2. C. H. Roth, Digital System Design using VHDL, Thomson Learning, 2001
T3. J. Bhaskar, A VHDL Primer, Addison Wesley, 1999
Reference Books:
R1. John.F.Wakerly, Digital Design-Principles and Practices, PHI, 3rd Edition updated,
2005
R2. Douglas Perry, VHDL: Programming by Example, TMH, 2002
R3. Michae John Sebastian Smith, Application-Specific Integrated Circuits, AddisonWesley, 1997
Evaluation Scheme
CIE Scheme
Assessment

Weightage in Marks

Mid Semester Exam 1

20

Mid Semester Exam 2

20

Task 1: Simulation using VHDL

05

Task 2: Implementation on FPGA using


VHDL(Mini Project)

05

Total

50

Semester End Examination (SEE) is a written examination, of three hours duration of


100 marks, with 50% weightage.

Be ready with laptop with Xilinx installed in it.


Sometimes you may have to show the output.

Course Utilization for Mid Semester Exams and Semester End Examination

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

No. of Questions in
Unit

I
II

III

Chapter

Teaching
Hours

Inside VHDL

10

Design of networks
for arithmetic
operations

08

Standard
combinational
modules

Mid
Semester
Exam 2

No. of
Questions
in SEE
2

-04

-2

12

Register-transfer
level systems
IV

Mid
Semester
Exam 1

--

Data and control


subsystem

10

Specification and
implementation of a
microcomputer

12

04
2

--

--

Note:

Each question carries 20 marks and may consist of sub-questions.

Mixing of sub-questions from different chapters within a unit is allowed in Mid Semester
Exam I, II and SEE.
Answer 5 full questions of 20 marks each by selecting one question from each unit out of
10 in SEE.

UNIT I

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Chapter Wise Plan


Subject Code: 15VDE111

Course Title: Modeling of Digital Systems


using VHDL

Chapter Number: 01

Chapter Title: Inside VHDL

Planned Hours: 10
Chapter Learning Objectives:
After studying this chapter, the student should be able to:
1. Know the basics of Very High Speed Integrated Circuit Hardware Descriptive
Language (VHDL)[L1,L2,L3]
2. Write the coding in different styles of modeling for any example given.[L4]
3. Solve digital combinational circuits and also write the VHDL code for the designed
circuits.[L5]
4. Solve sequential circuits and also write the VHDL code for the designed circuits.[L6]
5. Design FSM and write the VHDL code for the designed circuit.[L7]
6. Understand the concept of subprograms .[L8]
7. Write codes in VHDL for any circuits asked to design.[9,10]
Lesson Schedule
Class No.
1.
2.
3.
4
5.
6.
7.
8.
9.
10.

Portion covered per hour


Introduction to VHDL
Various language elements in VHDL and designing using these concepts.
Various language elements in VHDL and designing using these concepts.
Review the basic styles of modeling involved in VHDL
Analysis of combinational logic circuits with design concept.
Analysis of sequential logic circuits with design concept.
Designing finite state machines.
Subprograms description for the given problem definitions.
VHDL code to be written for all the above mentioned topics
VHDL code to be written for all the above mentioned topics

Review Questions:
1. Explain the three types of WAIT statements available in VHDL also give examples.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

2. With an example, explain binding between a library and a component taking full
adder as an example.
3. Design an FSM for a BCD up counter.
4. Write a VHDL code for a full adder using procedures.
5. Design a digital system which takes serial datas as inputs and outputs a 1
whenever consecutive three numbers of ones appear. Overlapping also should be
considered. Write the code for the same.

UNIT-II

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Subject Code: 15VDE111

Course Title: : Modeling of Digital Systems


using VHDL

Chapter Number: 02

Chapter Title: Design of networks for


arithmetic operations

Planned Hours: 08

Chapter Learning Objectives


After studying this chapter, the student should be able to:
1. Understand the concept state graph and state machines.[L11]
2. Design serial adder circuits for any n bit mentioned.[L12,13]
3. Design of binary multiplier for any n bit mentioned.[L14,15]
4. Design of binary divider for any n bit mentioned.[L16]
5. Write VHDL codes for all the above mentioned designs.[L17,18]
Lesson Schedule
Class No.
11.
12.
13.
14.
15.
16.
17.
18.

Portion covered per hour


Concept of state graph
Design of serial adder with accumulator
State and control graphs
Design of a signed binary multiplier
Design of a unsigned binary multiplier
Design of a binary divider signed and unsigned.
Design any arithmetic networks with VHDL codes.
Design any arithmetic networks with VHDL codes.

Review Questions:
1. Illustrate with a state graph and block diagram how an 8 bit number can be divided
by a 4 bit number.
2. Design a 4 bit array multiplier.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

USN
NMAM INSTITUTE OF TECHNOLOGY, NITTE
(An Autonomous Institution affiliated to VTU, Belgaum)
I Semester M.Tech. (E&C) Mid Semester Examinations-I
Sample Paper
15VDE111-MODELING OF DIGITAL SYSTEMS USING VHDL
Duration: 1 Hour

Max. Marks: 20

Note: 1) Answer any one full question from each unit

Unit I

1.
a)
Write a procedure to add 2-4 bit binary numbers
05

b)
What are the various objects in VHDL explain them with examples
05

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

2.
a)
Write a code in VHDL for a SR-FF using structural style and behavioral style .
05

b)
Write how binding takes place between components and the entity with a VHDL code.
05

Unit II

3.
a)
Design a twos compliment multiplier by giving the state graph and the block diagram
04

b)
Write a VHDL code for the above mentioned statement
06

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

4.
a)
With the help of a state graph and state table design a binary divider
06

b)
Two constraints that have to be placed on the input labels to have a completely specified proper
state graph. Justification for the statements with an example
04

UNIT-III(i)
Subject Code: 15VDE111
Chapter Number: 03
Planned Hours: 06

Course Title: Modeling of Digital Systems


using VHDL
Chapter Title: Standard combinational
modules

Subject
Code: 15VDE111
Course Title: Modeling
of Digital
Dept. of Electronics
& Communication Engineering
NMAMIT,
Nitte Systems
--------------------------------------------------------------------------------------------------------------------using VHDL
----------

Chapter Number: 03

Chapter Title: Register-transfer level


systems

Planned Hours: 06

Chapter Learning Objectives


After studying this chapter, the student should be able to:
1. Design decoders with various decoding networks.[L19]
2. Design binary encoders with appropriate applications .[L20,L21]
3. Understand multiplexer tree structures.[L22,23]
4. Design shifters and implement them invarious modules.[L24]
Lesson Schedule
Class No.

Portion covered per hour

19. Binary decoders and tree structures.


20. 20.
Binary encoders with applications
21. Priority encoders.
22. Multiplexer design with tree structures.
23. De multiplexers design with various tree structures.
F1 (a,b,c)=m(1,4,5,7)
F2 be
(a,b,c)=
M(2,3,6,7)
24. Shifters designs to
covered.
.
Review Questions:
1. Implement the following multiple output function using 3:8 decoder and external gates.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Chapter Learning Objectives


After studying this chapter, the student should be able to:

5.
6.
7.
8.

Relate and find how executions graphs can be drawn for the equation given[L25,26]
Find how the systems are organized.[L27]
Know how an RTL system can be designed using VHDL.[L28,29]
Analyze the RTL design.[L30]
Lesson Schedule

Class No.-Portion covered per hour


25. Implementation of various modules with shifting properties.
26. Executions graphs for different mathematical equations.
27. Design of sequential, group sequential, concurrent system.
28. Specification of RTL systems.
29. Data and control subsystem designs.
30. VHDL code for RTL designs.

Review Questions:
i.

Design a unimodule data subsystem for evaluating the polynomial


5

p xi
P5(x)
i=0

UNIT IV
Subject Code: 15VDE111

Course Title: Modeling of Digital Systems


using VHDL

Chapter Number: 03

Chapter Title: Data and Control Subsystem

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Planned Hours: 10

Chapter Learning Objectives


After studying this chapter, the student should be able to:
1.
2.
3.
4.
5.

Design Storage modules, functional modules and data path.[L31, L32]


Design an overall data subsystem.[L33, L34]
Design of control subsystem.[L35, L36]
Get an Insight to Micro programmed controller operations[L37, L38]
Write VHDL code for the above mentioned topics.[L39, L40]

Lesson Schedule
Class No.-Portion covered per hour
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.

Storage modules
Functional modules
Design of data subsystem with VHDL code.
Design of data subsystem with VHDL code
Design of control subsystem with VHDL code
Design of control subsystem with VHDL code
Micro programmed controller.
Examples of micro programmed systems
Any design example with VHDL code.
Any design example with VHDL code.

Review Questions:
1. With the help of a block diagram explain micro programmed controller.
2. With the help of block and timing diagram explain the sequence of events in data
Sub system for arithmetic and logic instructions during the
execution of the instruction.

USN
NMAM INSTITUTE OF TECHNOLOGY, NITTE
(An Autonomous Institution affiliated to VTU, Belgaum)

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

I Semester M.Tech. (E&C) Mid Semester Examinations-II


Sample Paper
15VDE111-MODELLING OF DIGITAL SYSTEMS USING VHDL
Duration: 1 Hour

Max. Marks: 20

Note: 1) Answer any one full question from each unit

Unit I

1.
a)
Implement the following multiple output function using 3:8 decoder and external gates
F1 (a,b,c)=m(1,4,5,7) F2 (a,b,c)= M(2,3,6,7)
05

b)
Implement a six input decoder using coincident and tree decoder networks and give the
comparison between the two in terms of decoder modules and AND gates
05

2.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

a)
Design a 2 bit right shifter using multiplexer.
05

b)
Implement a subtractor using 3:8 decoder and external gates
05

Unit II

3.
a)

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Fig 3.a
Write a VHDL code for the data subsystem shown in figure3.a
06

b)
Write any four characteristics of RTL level system.
04

4.
a)
Write a VHDL code for 4 bit serial parallel multiplier.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

06

b)
Show how the working of the serial parallel multiplier can be traced
04

UNIT V
Chapter wise Plan
Course Code: 15VDE111
Chapter Number: 10
Planned Hours: 12

Course Title: Modeling of Digital Systems


using VHDL
Chapter Title: Specification and
Implementation of a Microcomputer

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

Chapter Learning Objectives


After studying this chapter, the student should be able to:
1.
2.
3.
4.
5.

Implement a memory subsystem.[L41-44]


Implement a Processor of given specifications.
Optimize the memory subsystem design.
[L45-49]
Implement the data Subsystem.
Implement a simple microcomputer system [L50-52]

Lesson Schedule
Class No.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.

Portion covered per hour


Basic concept of a computer
Specification of the memory subsystem, data Subsystem, I/O subsystem.
Specification of the memory subsystem, data Subsystem, I/O subsystem
Specification of the memory subsystem, data Subsystem, I/O subsystem
Implementation of memory subsystem, data Subsystem, I/O subsystem
Implementation of memory subsystem, data Subsystem, I/O subsystem
Implementation of memory subsystem, data Subsystem, I/O subsystem
Implementation of memory subsystem, data Subsystem, I/O subsystem
Operation of the computer and cycle.
VHDL codes for the design of memory subsystem, data Subsystem.
VHDL codes for the design of memory subsystem, data Subsystem.
VHDL codes for the design of memory subsystem, data Subsystem.

Review Questions:
1. Draw the block diagram, internal organization and timing diagram for a memory
subsystem suitable for a microcomputer.
2. Write the VHDL entity declaration and a behavioral description for the above memory
subsystem.

USN
NMAM INSTITUTE OF TECHNOLOGY, NITTE
(An Autonomous Institution affiliated to VTU, Belgaum)

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

I Semester M.Tech (E&C) (Credit System) Degree Examinations


Model Question paper
15VDE111-MODELLING OF DIGITAL SYSTEMS USING VHDL
Duration: 3 Hours

Max. Marks: 100

Note: 1) Answer one question from each unit


UNIT I
1.
a)
Write a VHDL code for 8:1 MUX using behavioral, Dataflow and structural style of modeling
09

b)
With examples explain the various data objects present in VHDL.
06

c)
Design using a 4:1 multiplexer for the following function
E(x2,x1,x0) =m(1,2,4,6,7)
05

2.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

a)
Explain VHDL data objects with examples and also give the general syntax for the same.
06

b)
Design a 4-bit up counter using structural style of modeling and also write the code
08

c)
Write a VHDL function to convert integer to binary.
06
UNIT II
3.
a)
Design a 4 bit serial parallel multiplier with example.
06

b)
Write the VHDL code for a 4 bit serial parallel multiplier for data and control subsystem
14

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

4.
a)
Design a block diagram for signed binary fast multiplier.
03

b)
With the help of a state graph write a VHDL code for signed binary fast multiplier.
08

c)
Write a block Diagram of signed divider and explain with an example how overflow is detected
in case of signed division.
06

d)
Write the state graph for signed divider control network.
03

UNIT III

5.
a)
For the polynomial of degree seven given below ,Design a system with non-sharing functional
units and decentralized control

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

08

b)
Design a data subsystem and control subsystem for the system specified .Write a generalized
VHDL code for data and control subsystem.

12
6.
a)
With neat block diagram explain structure of RTL systems
10

b)
Write a VHDL code for the register transfers for the above explained RTL system
10

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

7.
a)
Draw a block diagram of a typical block diagram of a typical microprogrammed controller and
briefly describe its modules.
08

b)
Bring out the advantages of a microprogrammed controller with respect to a controller
implemented as a fixed network.
02

c)
Explain microinstruction formats and microinstruction sequencing.
10

8.
a)
Define register file used in a data subsystem. Write VHDL description for a register file that can
perform two read and one with operation only write control signal. Read operations are
performed whenever address applied to RAL and RAR inputs.
12

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

b)
Write the structure of cross bar data path and explain briefly. Write a VHDL code for the same.
08

9.
a)
Explain the sequence of events in data subsystems for arithmetic logic instruction
04

b)
Write the block diagram for the sequence of events in data subsystems
08

c)
Write the timing diagram in data subsystems for arithmetic logic instruction
08

10.

Dept. of Electronics & Communication Engineering


NMAMIT, Nitte
------------------------------------------------------------------------------------------------------------------------------

a)
Give a description of how the operation of the computer and its cycle time calculations are
performed.
10

b)
Draw the block diagram, internal organization and timing diagram for a memory subsystem
suitable for the design of a microcomputer system.
10