15/09/2015

MEKATRONIKA
Meet 2 : Counter dan Shift Register
15 September 2015

Teknik Mesin
Unjani
HBH

Herman Budi Harja, S.T., M.T.

Definisi
Counter aplikasi Flip flop sebagai penghitung maju/mundur.
Register merupakan penerapan flip flop sebagai penyimpan
memori (1 bit = 1 Flip flop)

15/09/2015

Case

Common TTL Flip-Flops

7474 is a positive edge triggered D flip-flop
Active low Preset (PRN) and Clear (CLRN)

7473a is a negative edge triggered JK flop-flop

7473 is the master-slave version
positive edge triggered

15/09/2015

Registers
A flip-flop stores one bit of information
When you want to store n bits register
n flip-flops used
Clock is shared by all so action is synchronous with clock edge

Some common register types

Simple register
Shift register
Parallel access shift register
Lots of counters: up counter, down counter, BCD counter, ring counter,
Johnson counter

Simple 4 Bit Register

A standard 4 bit register using D flip flops
Parallel output
Q3
D

Q
Q

Q2
D

Q
Q

Q1
D

Q
Q

Q0
D

Q
Q

Parallel input
Clock

15/09/2015

4 Bit Register with Load Control

Controlling the load capability
Parallel output
Q3
D

Q2

Q1

Q0

Q
Q

Parallel input
Clock Load

Simple Shift Register

Provide only serial in/out access

In
Clock

Q
Q

Q1

Q
Q

Q2

Q
Q

Q3

Q4

Out

15/09/2015

Action of Shift Register

t0

In
1

Q1
0

Q2
0

Q3
0

Q4 = Out
0

t1

t2

t3

t4

t5

t6

t7

Can you use a level sensitive gated latch instead of a flip-flop?

No! The values would propagate during Clock = 1

Parallel Access Shift Register

Provide parallel data load
Provide parallel data read
Provide serial shift
Shift/Load = 0
Shift right
Shift/Load = 1
Load

Parallel output
Q3

Q2

Q1

Q0

D Q

D Q

D Q

D Q

Serial
input Shift/Load

Parallel input

Clock

15/09/2015

Example Problem: General Shifter

Design a parallel access (parallel data in / out) shift register
that can load or shift either left or right choice dictated
by a control signal
Then add the ability to "stay in memory"
Don't forget to connect serial in to both MSB and LSB
S1

S0

Function

memory

SHR

SHL

load

Solution: General Shifter

Parallel output
Q3

s1
s0

Q3

Q3

Q3

D Q

D Q

D Q

D Q

0 1 2 3

s1
s0

0 1 2 3

s1
s0

0 1 2 3

SRSI

s1
s0

0 1 2 3

SLSI
Parallel input

Clock

15/09/2015

74164 Shifter
8 bit serial in / parallel out shifter (used in modems)
Active low clear (CLRN)
Data-in provided by AND(A,B)
Positive edge triggered shift right register

74165 Shifter
8 bit parallel in / serial out shifter (also used in modems)
Active low asynchronous parallel load output is H
CLKIH is an active high clock inhibit memory state
Positive edge-triggered shift right register: SER is serial in

15/09/2015

74194 Bi-Directional Shifter

4 bit bi-directional shifter with parallel load

Active low asynchronous clear

Shift Left Serial In (SLSI)
Shift Right Serial In (SRSI)
Positive edge-triggered

Asynchronous Counters
Up counter using T flip-flops
Count clock pulses
1
Clock

Q
Q0

MSB of count

Q
Q1

Q2

Q0 toggles on every 0 1 clock edge

Q1 toggles on every 1 0 transition of Q0
Q2 toggles on every 1 0 transition of Q1

15/09/2015

Delays in Asynchronous Counters

Propagation delays slow this counting process!

Clock

Q
Q0

Q
Q1

Q2

Clock
Q0
Q1
Q2
Count 0

Asynch Modulo 8 Up Counter

This counter counts 000 001 111 000
Assumes output is in order Q2 Q1 Q0
Modulo 8 up counter

The lower order flip-flop is synchronized to the Clock

All other flip-flops are not asynchronous
Also called ripple counter

1
Clock

Q
Q0

Q
Q

Q1

Q2

15/09/2015

Asynch Modulo 8 Down Counter

To count 111 110 001 000 111

Clock

Q
Q0

Q
Q

Q1

Q2

Clock
Q0
Q1
Q2
Count 0

Synchronous Counters
Asynchronous counters are slow due to propagation delays
Synchronous counters share the clock among all flip-flops

clock cycle

Q2

Q1

Q0

T0 = 1
T1 = Q0
T2 = Q1Q0
T3 = Q2Q1Q0

always toggle
toggle when Q0 = 1
toggle when Q1Q0 = 1
toggle when Q2Q1Q0 = 1

10

15/09/2015

Mod 16 Synchronous Up Counter

Clock

Q0

Q1

Q2

Q3

Waveform for Mod 16 Up Counter

Clock

Q0

Q1

Q2

Q3

Clock
Q0
Q1
Q2
Q3
Count

10

11

12 13

14 15

11

15/09/2015

Adding Clear and Enable Signals

Just use T flip-flop with asynchronous clear
Cascade the Enable via AND gates to the T inputs
Recall: T toggle only when T input = 1

Enable

Clock

Q
Q

Q
Q

Clear

4 Bit Up Counter Using D Flip-Flops

How can you make an up counter using D flip-flops?
clock cycle

Q2

Q1

Q0

D0 = 1 Q0
D1 = Q1 Q0
D2 = Q2 Q1Q0
D3 = Q3 Q2Q1Q0

always toggle
toggle when Q0 = 1
toggle when Q1Q0 = 1
toggle when Q2Q1Q0 = 1

12

15/09/2015

4 Bit Up Counter
Q0

D Q

Enable

Enable input permits

control of counter

Q1

D Q
Q

Output carry permits

chaining of counters
to make larger ones

Q2

D Q
Q

Q3

D Q
Q

Output
carry

Clock

Counter With Parallel Load

Want a counter that
can load any initial
value that you desire
in order to start the
count

Enable
D0

D1

Load = 1 load
D2
Enable = 1 increment
Load = Enable = 0 memory

Load
Clock

0
1

DQ
Q

0
1

DQ
Q

0
1

DQ

Q0

Q1

Q2

0
1

DQ
Q

Q3
Output
carry

13

15/09/2015

Mod n Counting for n 2k

Most counters reset (cycle) to 0 when all k flip-flops are 1
value of count = 2k-1
Mod 8 counter: k = 3
000 001 010 111 000

How to synchronously reset when value < 2k-1?

Want to allow something like:
000 001 101 000
This is a mod 6 counter

Mod 6 Synchronous Up Counter

When output = Q2Q1Q0 = 101, load 000 to force reset on
next clock edge
This provides a synchronous reset

Enable

D0

Q0

D1

Q1

D2

Q2

Load
Clock
Clock

14

15/09/2015

Another Mod 6 Up Counter

This version provides an asynchronous reset
Look at the narrow width of the 101 output level!
recognizes
1x1
1

Clock

Q0

Q1

Q2

Clock
Q0
Q1
Q2
Count 0

Other Counter Types

BCD Counter
Count from 0 to 9 and back to 0
Cascade the counters to mimic decimal counting
00 01 09 10 11 19 20
Each position is a BCD digit

Ring Counter
4 bit ring count: 1000 0100 0010 0001 1000
One-hot output that cycles in a ring

Johnson Counter
4 bit count: 0000 1000 1100 1110 1111 0111 0011 0001
0000

15

15/09/2015

2 Digit BCD Counter

1
0
0
0
0

Enable
D0
D1
D2
D3

Q0
Q1
Q2
Q3

BCD 0

Load
Clock
Clock
Clear
0
0
0
0

Enable
D0
D1
D2
D3

Is 1 when 1xx1 is detected

-- first time is for 1001 = 9
Q0
Q1
Q2
Q3

BCD 1

Load
Clock

4 Bit Ring Counter Using a Decoder

Counts 1000 0100 0010 0001 1000

16

15/09/2015

Ring Counter Using D Flip-Flops

A design that uses a minimum of combinational logic, but
uses more flip-flops
asynchronous preset
Q0

Q1

Qn 1

Start

Q
Q

Clock

asynchronous clear

Johnson Counter
n-bit counter that generates a sequence of length 2n
0000 1000 1100 1110 1111 0111 0011 0001
0000 .
Q0

Q
Q

Reset
Clock

Q1

Q
Q

Qn 1

Q
Q

pushes the initial 1

into the count

17