Digital Receiver Verification

Verification of Digital Receiver System Architecture
CHAPTER 1
ABOUT THE ORGANIZATION

The Defence Research and Development Organisation (DRDO) is an agency of
the Republic of India, charged with the military's research and development,
headquartered in New Delhi, India. It was formed in 1958 by the merger of the
Technical Development Establishment and the Directorate of Technical Development
and Production with the Defence Science Organisation. It is under the administrative
control of the Ministry of Defence, Government of India.
With a network of 52 laboratories, which are engaged in developing defence
technologies covering various fields, like aeronautics, armaments, electronics, land
combat engineering, life sciences, materials, missiles, and naval systems, DRDO is
India's largest and most diverse research organisation. The organisation includes around
5,000 scientists belonging to the Defence Research & Development Service
(DRDOs)[4] and about 25,000 other scientific, technical and supporting personnel.
Defence Research and Development Organisation (DRDO) was established in
1958 by amalgamating the Defence Science Organisation and some of the technical
development establishments. A separate Department of Defence Research and
Development was formed in 1980 which later on administered DRDO and its 50
laboratories/establishments. Most of the time the Defence Research Development
Organisation was treated as if it was a vendor and the Army Headquarters or the Air
Headquarters were the customers. Because the Army and the Air Force themselves did
not have any design or construction responsibility, they tended to treat the designer or
Indian industry at par with their corresponding designer in the world market. If they
could get a MiG-21 from the world market, they wanted a MiG-21 from DRDO.[5]
DRDO started its first major project in surface-to-air missiles (SAM) known
as Project Indigo in 1960s. Indigo was discontinued in later years without achieving
full success. Project Indigo led to Project Devil, along with Project Valiant, to develop
short-range SAM and ICBM in the 1970s. Project Devil itself led to the later
development of the Prithvi missile under the Integrated Guided Missile Development
Programme (IGMDP) in the 1980s. IGMDP was an Indian Ministry of
Defence programme between the early 1980s and 2007 for the development of a
VLSI Design & Embedded Systems, Dept. of ECE
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comprehensive range of missiles, including the Agni missile, Prithvi ballistic
missile, Akash missile, Trishul missile and Nag Missile.
In 2010, then defence minister A K Antony ordered the restructuring of the
Defence Research and Development Organisation (DRDO) to give a major boost to
defence research in the country and to ensure effective participation of the private sector
in defence technology.
The key measures to make DRDO effective in its functioning include the
establishment of a Defence Technology Commission with the defence minister as its
chairman.[6][7] The programmes which were largely managed by DRDO have seen
considerable success with many of the systems seeing rapid deployment as well as
yielding significant technological benefits.[8] DRDO has achieved many successes since
its establishment in developing other major systems and critical technologies such as
aircraft avionics, UAVs, small arms, artillery systems, EW Systems, tanks and
armoured vehicles, sonar systems, command and control systems and missile systems.
Aeronautics
The DRDO is responsible for the ongoing Light Combat Aircraft. The LCA is
intended to provide the Indian Air Force with a modern, fly by wire, multi-role fighter,
as well as develop the aviation industry in India. The LCA programme has allowed
DRDO to progress substantially in the fields of avionics, flight control systems, aircraft
propulsion and composite structures, along with aircraft design and development.[9]
The DRDO provided key avionics for the Sukhoi Su-30MKI programme under
the "Vetrivel" programme. Systems developed by DRDO include radar warning
receivers, radar and display computers. DRDO's radar computers, manufactured by
HAL are also being fitted into Malaysian Su-30s.
The DRDO is part of the Indian Air Force's upgrade programmes for its MiG27 and Sepecat Jaguar combat aircraft, along with the manufacturer Hindustan
Aeronautics Limited. DRDO and HAL have been responsible for the system design and
integration of these upgrades, which combine indigenously developed systems along
with imported ones. DRDO contributed subsystems like the Tarang radar warning
receiver, Tempest jammer, core avionics computers, brake parachutes, cockpit
instrumentation and displays.
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HAL AMCA: Aeronautical Development Agency of DRDO is responsible for
the design and development of the fifth generation aircraft. In 2015, 700 ADA
employees were working on the project along with 2,000 employees of DRDO.
Avatar (spacecraft)
Other Hindustan Aeronautics programs
Apart from the aforementioned upgrades, DRDO has also assisted Hindustan
Aeronautics with its programmes. These include the HAL Dhruv helicopter and
the HAL HJT-36. Over a hundred LRU (Line Replaceable Unit)'s in the HJT-36 have
come directly from the LCA programme. Other duties have included assisting the
Indian Air Force with indigenisation of spares and equipment. These include both
mandatory as well as other items.
Unmanned aerial vehicles
The DRDO has also developed two unmanned aerial vehicles the Nishant tactical UAV and the Lakshya (Target) Pilotless Target Aircraft
(PTA).[10] The Lakshya PTA has been ordered by all three services for their gunnery
target training requirements. Efforts are on to develop the PTA further, with an
improved all digital flight control system, and a better turbojet engine.[11]The Nishant
is a hydraulically launched short-ranged UAV for the tactical battle area. It is currently
being evaluated by the Indian Navy and the Indian Paramilitary forces as well.
The DRDO is also going ahead with its plans to develop a new class of UAVs.
These draw upon the experience gained via the Nishant programme, and will be
substantially more capable. Referred to by the HALE (High Altitude Long Endurance)
and MALE (Medium Altitude Long Endurance) designations. The MALE UAV has
been tentatively named the Rustom
[12]
and will feature canards and carry a range of
payloads, including optronic, radar, laser designators and ESM. The UAV will have
conventional landing and take-off capability. The HALE UAV will have features such
as SATCOM links, allowing it to be commanded beyond line of sight. Other tentative
plans speak of converting the LCA into a UCAV (unmanned combat aerial vehicle),
and weaponising UAVs.
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DRDO Abhyas
DRDO AURA
DRDO Fluffy
DRDO Imperial Eagle
DRDO Kapothaka
DRDO Lakshya
DRDO Netra
DRDO Nishant
Pawan UAV
DRDO Rustom
DRDO Ulka
Indigenisation efforts
DRDO has been responsible for the indigenisation of key defence stores and
equipment.[13] DRDO has assisted Hindustan Aeronautics Ltd and the IAF with the
indigenisation of spares and assemblies for several aircraft. DRDO laboratories have
worked in coordination with academic institutes, the CSIR and even ISRO over projects
required for the Indian Air Force and its sister services. DRDO's infrastructure is also
utilised by other research organizations in India.
Armaments
DRDO often cooperates with the state owned Ordnance Factories Board for
producing its items. These have led to issues of marginal quality control for some items,
and time consuming rectification. Whilst these are common to the introduction of most
new weapons systems, the OFB has had issues with maintaining the requisite schedule
and quality of manufacture owing to their own structural problems and lack of
modernisation. Criticism directed at the OFB is invariably used for the DRDO, since
the users often make little distinction between the developer and the manufacturer. OFB
has got more access to funding in recent times, and this is believed to have helped the
organisation meet modern day requirements.
Even so, India's state owned military apparatus provides the bulk of its
ammunition. The DRDO has played a vital role in the development of this ability since
the role of private organisations in the development of small arms and similar items has
been limited. A significant point in case is the INSAS rifle which has been adopted by
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the Indian Army as its standard battle rifle and is in extensive service. There have been
issues with rifle quality in usage under extreme conditions in the heat, with the OFB
stating that it will rectify these troubles with higher grade material and strengthening
the unit. Prior troubles were also dealt with in a similar manner.[14] In the meantime, the
rifle has found favour throughout the army and has been ordered in number by other
paramilitary units and police forces.[15][16]
In the meantime, the DRDO has also forged partnerships with several private
sector industrial partners, which have allowed it to leverage their strengths. Successful
examples of this include the Pinaka MBRL, which has been assisted significantly by
two private developers, Larsen and Toubro Ltd as well as TATA, apart from several
other small scale industrial manufacturers.
DRDO's projects:
Small arms
The INSAS weapon system has become the standard battle rifle for the Indian
Army and paramilitary units.[19] Bulk production of a LMG variant commenced in
1998.[20] It has since been selected as the standard assault rifle of the Royal Army of
Oman.
In 2010, DRDO completed the development of Oleo-resin plastic hand grenades
(partly derived from the potent Bhut Jholokia chilli found in north-east India), as a less
lethal way to control rioters, better tear gas shells and short-range laser dazzlers.[21]
Electronic warfare
1) EW systems for the Army
It is India's largest electronic warfare system. It is a land based EW project,

consisting of 145 vehicles. The Samyukta consists of ESM and ECM stations
for both communication and non-com (radar etc.) systems. The Indian Army
has ordered its Signal Corps to be a prime contributor in the design and
development stage, along with the DRDO's DLRL. The scale of this venture
is substantial - it comprises COMINT and Electronic intelligence stations
which can monitor and jam different bands for both voice/data as well as radar
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transmissions. In contrast to other such systems, Samyukta is an integrated
system, which can perform the most critical battlefield EW tasks in both COM
and Non-Com roles. The system will be the first of its type in terms of its
magnitude and capability in the Army. Its individual modules can also be
operated independently.[35] A follow on system known as Sauhard is under
development.[36]
The Safari IED suppression system for the army and paramilitary forces and
the Sujav ESM system meant for high accuracy direction finding and jamming
of communication transceivers.[37]
2) EW systems for the Air Force
Radar warning receivers for the Indian Air Force of the Tarang series. These
have been selected to upgrade most of the Indian Air Force's aircraft such as
for the MiG-21, MiG-29, Su-30 MKI, MiG-27 and Jaguar as well as selfprotection upgrades for the transport fleet.
The Tranquil RWR for MiG-23s (superseded by the Tarang project) and
the Tempest jamming system for the Air Force's MiG's. The latest variant of
the Tempest jamming system is capable of noise, barrage, as well as deception
jamming as it makes use of DRFM. The DRDO has also developed a High
Accuracy Direction Finding system (HADF) for the Indian Air Force's Su-30
MKIs which are fitted in the modular "Siva" pod capable of supersonic
carriage.[38] This HADF pod is meant to cue Kh-31 Anti-radiation missiles
used by the Su-30 MKI for SEAD.
DRDO stated in 2009 that its latest Radar warning receiver for the Indian Air
Force, the R118, had gone into production. The R118 can also fuse data from
different sensors such as the aircraft radar, missile/laser warning systems and
present the unified data on a multi-function display. The DRDO also noted
that its new Radar Warner Jammer systems (RWJ) were at an advanced stage
of development and would be submitted for trials. The RWJ is capable of
detecting all foreseen threats and jamming multiple targets simultaneously.
Other EW projects revealed by the DRDO include the MAWS project (a joint
venture by the DRDO and EADS) which leverages EADS hardware and
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DRDO software to develop MAWS systems for transport, helicopter and
fighter fleets. DRDO also has laser warning systems available.
A DIRCM (Directed Infra-Red Countermeasures) project to field a world class

DIRCM system intended to protect aircraft from infrared guided weapons.
The DRDO is also developing an all new ESM project in cooperation with
the Indian Air Force's Signals Intelligence Directorate, under the name of
"Divya Drishti" (Divine Sight). Divya Drishti will field a range of static as
well as mobile ESM stations that can "fingerprint" and track multiple airborne
targets for mission analysis purposes. The system will be able to intercept a
range of radio frequency emissions like radar, navigational, communication or
electronic countermeasure signals. The various components of the project will
be networked via SATCOM links.
Additional DRDO EW projects delivered to the Indian Air Force have

included the COIN A and COIN B SIGINT stations. DRDO and BEL
developed ELINT equipment for the Indian Air Force, installed on the
service's Boeing 737s and Hawker Siddeley Avro aircraft. DRDO has also
developed a Radar Fingerprinting System for the IAF and the Navy.
Another high accuracy ESM system is being developed by the DRDO for
the AEW&C project. The Indian Air Force's AEW&C systems will also
include a comprehensive ESM suite, capable of picking up both radars as well
as conducting Communications Intelligence.
Combat vehicles & engineering

Tanks and armoured vehicles
Ajeya upgrade (Sanskrit: Invincible): upgrade for the T-72 fleet, incorporating
a mix of locally made and imported subsystems. 250 have been ordered. Local
systems include the DRDO-developed ERA, a DRDO-developed laser
warning system and combat net radio, the Bharat Electronics Limited
advanced land navigation system consisting of fibre optic gyros and
GPS,NBC protection and DRDO's fire detection and suppression system
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amongst other items. Imported systems include a compact thermal imager and
fire control system and a new 1000 hp engine.
Anti-tank ammunition: DRDO developed the FSAPDS for the 125 mm calibre,
meant for India's T-72 tanks, the 120 mm FSAPDS and HESH rounds for
the Arjun tank and 105 mm FSAPDS rounds for the Army's Vijayanta and T55 tanks.[55] Significant amounts of 125 mm anti-tank rounds manufactured by
the Ordnance Factory Board were rejected. The problems were traced to
improper packaging of the charges by the OFB, leading to propellant leakage
during storage at high temperatures. The locally developed rounds were
rectified and requalified. Production of these local rounds was then restarted.
Since 2001, over 130,000 rounds have been manufactured by the OFB. The
DRDO said in 2005 that it had developed an Mk2 version of the 125 mm
round, with higher power propellant for greater penetration. In parallel, the
OFB announced in 2006 that it was also manufacturing 125 mm IMI (Israel
Military Industries) rounds. It is believed that this might assist in improving
the OFB's APFSDS manufacturing capability. These rounds and presumably
the Mk2 round and will be used by both the T-72 and T-90 formations in the
Indian Army.[56][57]
Various armour technologies and associated subsystems from composite

armour and explosive reactive armour to Radios (Combat Net Radio with
frequency hopping and encryption) and Battle Management systems. Firecontrol systems are currently in production at BEL for the Arjun tanks. The
first batch in production have a hybrid Sagem-DRDO system, with Sagem
sights and local fire control computer.[58]
Arjun tank: The penultimate design was accepted by the Indian Army and is
now in series production at HVF Avadi.
The Arjun follows a template similar to the tanks developed by western

nations, with containerised ammunition storage, with blast off panels, heavy
Composite armour, a 120 mm gun (rifled as compared to smoothbore on most
other tanks), a modern FCS with high hit probability and a 1,400 horsepower
(1,000 kW) engine and a four-man crew. Originally designed in response to a
possible Pakistani acquisition of the M1 Abrams, the project fell into disfavour
once it became clear that Pakistan was instead standardising on cheaper (and
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less capable) T type tanks[citation needed]. In such a milieu, acquiring the Arjun in
huge numbers is simply unnecessary for the Indian Army, given the additional
logistic costs of standardising on an entirely new type. The Indian
Army ordered 124 units in 2000 and an additional 124 units in 2010[59][60] and
work on Mark-II version of the tank has commenced.[61]
Naval research and development

Sonars
DRDO, BEL and the Indian Navy have developed and productionised a range
of sonars and related systems for the Indian Navy's frontline combat ships.
These include:
1) APSOH (Advanced Panoramic Sonar Hull mounted)
2) HUMVAD (Hull Mounted Variable Depth sonar)
3) HUMSA (Follow on to the APSOH series; the acronym HUMSA stands for
Hull Mounted Sonar Array)
4) Nagin (Towed Array Sonar)
5) Panchendriya (Submarine sonar and fire control system)
Other sonars such as the airborne sonar Mihir are in trials, whilst work is
proceeding apace on a new generation of sonars. Sonars may be considered one of
DRDO's most successful achievements as the Indian Navy's most powerful ships rely
on DRDO made sonars. The standard fit for a front line naval ship would include the
HUMSA-NG hull mounted sonar and the Nagin towed array sonar. The Mihir is a
dunking sonar meant for use by the Naval ALH, working in conjunction with its
Tadpole sonobuoy. The Panchendriya is in production for the Kilo class
submarine upgrades.[74][75][76]
Other projects
These have included indigenisation of various components (for instance,
adsorbent material for submarines, radar components and naval ship signature
reduction efforts and materials technology). DRDO has played a significant role in the
development of warship grade steel in India and its productionisation. DRDO has also
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assisted private industry in developing EW trainers, ship simulators for training and
health monitoring systems for on board equipment. Other equipment for the Navy
includes underwater telephone sets, and VLF communication equipment, for the Navy's
submarines. DRDO's IRDE has also developed optronic fire control systems for the
Navy's and the Coast Guard's ships.[82]
Missile systems
1. Integrated Guided Missile Development Programme (IGMDP)
2. Prithvi ballistic Missiles
3. Agni ballistic Missiles
4. Akash SAM
5. Trishul SAM
6. Nag anti-tank Missile
7. Brahmos Missile
8. Shaurya Missile
9. Sagarika Missile
10. Sudarshan Missile
11. Prahaar Missile
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DARE, DRDO
Defence Avionics Research Establishment (DARE) is a laboratory of the
Indian Defence Research and Development Organisation (DRDO). Located
in Bangalore, Karnataka, India, it is the main DRDO lab involved in the Research &
Development of Airborne Electronic Warfare and Mission Avionics systems.
DARE was established in 1986 as a Project Laboratory, then named "Advanced
Systems Integration and Evaluation Organisation" (ASIEO). On 1 June 2001, it became
a full-fledged DRDO lab, and was renamed as DARE.
DARE has two major wings the Electronic Warfare (EW) wing and the
Mission Avionics Wing (MAW). The EW wing concentrates on development of Radar
Warning Systems and EW suites for aircraft. The MAW conducts Research and
Development in the area of Mission Avionics. In addition to development, DARE also
conducts testing and integration of the systems into aircraft.
DRDO's avionics program has been a success story; DARE being the lead
designer in several of these efforts. Its Mission computers, radar warning receivers,
high accuracy direction finding pods, airborne jammers, flight instrumentation, are used
across a wide variety of Indian Air Force aircraft. The organization began developing
these various items for its upgrades, and for the LCA project. Variants were then
developed for other aircraft.
The DRDO is also co-developing more advanced avionics for the Light Combat
Aircraft and the IAF's combat fleet. These include a range of powerful Open
Architecture computers, better Defensive avionics including modern RWR's, selfprotection jammers, missile approach warning systems and integrated defensive suites,
optronics systems (such as Infrared search and track systems) and navigational systems
such as Ring Laser Gyro based inertial navigation systems.
Some products developed by DARE include:
AEW Systems: Built for Indian Air Force and Navy aircraft, these consist of
Electronic Support Measures and Self-Protection Jammers.
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Radar Warning Systems: Developed for fighter aircraft in 1997. The units are
being produced by Bharat Electronics Limited (BEL) for use in all IAF and Indian
Navy aircraft & Helicopters.
Mission Avionics: DARE has developed the Mission computers and avionics for
various aircraft, including the HAL Tejas, Jaguar DARIN-II and the Su-30MKI.
The mission avionics includes a Mission Computer, Display Processor and Radar
Computer. All have been indigenously developed, and represent major
breakthroughs in achieving technical proficiency in these technologies.
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CHAPTER 2
ABOUT THE DEPARTMENT

The EW wing concentrates on development of Radar Warning Systems and EW
suites for aircraft.
DRDO's avionics program has been a success story; DARE being the lead
designer in several of these efforts. Its Mission computers, radar warning receivers,
high accuracy direction finding pods, airborne jammers, flight instrumentation, are used
across a wide variety of Indian Air Force aircraft. The organization began developing
these various items for its upgrades, and for the LCA project. Variants were then
developed for other aircraft.
Electronic warfare
1) EW systems for the Army
It is India's largest electronic warfare system. It is a land based EW project,

consisting of 145 vehicles. The Samyukta consists of ESM and ECM stations
for both communication and non-com (radar etc.) systems. The Indian Army
has ordered its Signal Corps to be a prime contributor in the design and
development stage, along with the DRDO's DLRL. The scale of this venture
is substantial - it comprises COMINT and Electronic intelligence stations
which can monitor and jam different bands for both voice/data as well as radar
transmissions. In contrast to other such systems, Samyukta is an integrated
system, which can perform the most critical battlefield EW tasks in both COM
and Non-Com roles. The system will be the first of its type in terms of its
magnitude and capability in the Army. Its individual modules can also be
operated independently.[35] A follow on system known as Sauhard is under
development.[36]
The Safari IED suppression system for the army and paramilitary forces and
the Sujav ESM system meant for high accuracy direction finding and jamming
of communication transceivers.[37]
2) EW systems for the Air Force
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Radar warning receivers for the Indian Air Force of the Tarang series. These
have been selected to upgrade most of the Indian Air Force's aircraft such as
for the MiG-21, MiG-29, Su-30 MKI, MiG-27 and Jaguar as well as selfprotection upgrades for the transport fleet.
The Tranquil RWR for MiG-23s (superseded by the Tarang project) and
the Tempest jamming system for the Air Force's MiG's. The latest variant of
the Tempest jamming system is capable of noise, barrage, as well as deception
jamming as it makes use of DRFM. The DRDO has also developed a High
Accuracy Direction Finding system (HADF) for the Indian Air Force's Su-30
MKIs which are fitted in the modular "Siva" pod capable of supersonic
carriage.[38] This HADF pod is meant to cue Kh-31 Anti-radiation missiles
used by the Su-30 MKI for SEAD.
DRDO stated in 2009 that its latest Radar warning receiver for the Indian Air
Force, the R118, had gone into production. The R118 can also fuse data from
different sensors such as the aircraft radar, missile/laser warning systems and
present the unified data on a multi-function display. The DRDO also noted
that its new Radar Warner Jammer systems (RWJ) were at an advanced stage
of development and would be submitted for trials. The RWJ is capable of
detecting all foreseen threats and jamming multiple targets simultaneously.
Other EW projects revealed by the DRDO include the MAWS project (a joint
venture by the DRDO and EADS) which leverages EADS hardware and
DRDO software to develop MAWS systems for transport, helicopter and
fighter fleets. DRDO also has laser warning systems available.
A DIRCM (Directed Infra-Red Countermeasures) project to field a world class

DIRCM system intended to protect aircraft from infrared guided weapons.
The DRDO is also developing an all new ESM project in cooperation with
the Indian Air Force's Signals Intelligence Directorate, under the name of
"Divya Drishti" (Divine Sight). Divya Drishti will field a range of static as
well as mobile ESM stations that can "fingerprint" and track multiple airborne
targets for mission analysis purposes. The system will be able to intercept a
range of radio frequency emissions like radar, navigational, communication or
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electronic countermeasure signals. The various components of the project will
be networked via SATCOM links.
Additional DRDO EW projects delivered to the Indian Air Force have

included the COIN A and COIN B SIGINT stations. DRDO and BEL
developed ELINT equipment for the Indian Air Force, installed on the
service's Boeing 737s and Hawker Siddeley Avro aircraft. DRDO has also
developed a Radar Fingerprinting System for the IAF and the Navy.
Another high accuracy ESM system is being developed by the DRDO for
the AEW&C project. The Indian Air Force's AEW&C systems will also
include a comprehensive ESM suite, capable of picking up both radars as well
as conducting Communications Intelligence.
Radars
The DRDO has steadily increased its radar development. The result has been
substantial progress in India's ability to design and manufacture high power radar
systems with locally sourced components and systems. This began with the
development of short-range 2D systems (Indra-1) and has now extended to high power
3D systems like LRTR intended for strategic purposes. Several other projects span the
gamut of radar applications, from airborne surveillance (AEW&C) to fire control radars
(land based and airborne). The DRDO's productionized as well as production-ready
radar systems include:
INDRA series of 2D radars meant for Army and Air Force use. This was the first
high power radar developed by the DRDO, with the Indra-I radar for the Indian
Army, followed by Indra Pulse Compression (PC) version for the Indian Air Force,
also known as the Indra-II, which is a low level radar to search and track low flying
cruise missiles, helicopters and aircraft. These are 2D radars which provide range
and azimuth information and are meant to be used as gap fillers. The Indra 2 PC
has pulse compression providing improved range resolution. The series are used
both by the Indian Air Force and the Indian Army[39]
Rajendra fire control radar for the Akash SAM: The Rajendra is stated to be ready.
However, it can be expected that further iterative improvements will be made. The
Rajendra is a high power Passive electronically scanned array radar (PESA), with
the ability able to guide up to 12 Akash SAMs against aircraft flying at low to
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medium altitudes. The Rajendra has a detection range of 80 km with 18 km height
coverage against small fighter sized targets and is able to track 64 targets, engaging
4 simultaneously, with up to 3 missiles per target. The Rajendra features a fully
digital high speed signal processing system with adaptive moving target indicator,
coherent signal processing, FFTs and variable pulse repetition frequency. The
entire PESA antenna array can swivel 360 degrees on a rotating platform. This
allows the radar antenna to be rapidly repositioned and even conduct all round
surveillance.[40]
Central Acquisition Radar, a state of the art planar array S-Band radar operating on
the stacked beam principle. With a range of 180 km, it can track while scan 200
fighter sized targets. Its systems are integrated on high mobility, locally built
TATRA trucks for the Army and Air Force; however it is meant to be used by all
three services. Initially developed for the long-running Akash SAM system, seven
were ordered by the Indian Air Force for their radar modernisation programme and
two of another variant were ordered by the Indian Navy for their P-28 Corvettes.
The CAR has been a significant success for radar development in India, with its
state of the art signal processing hardware.[41][42] The ROHINI is the IAF specific
variant while the REVATHI is the Indian Navy specific variant. The ROHINI has
a more advanced Indian developed antenna in terms of power handling and
beamforming technology while the REVATHI adds two axis stabilisation for
operation in naval conditions, as well as extra naval modes.
BFSR-SR, a 2D short-range Battle Field Surveillance Radar, meant to be man

portable. Designed and developed by LRDE, the project was a systematic example
of concurrent engineering, with the production agency involved through the design
and development stage. This enabled the design to be brought into production
quickly.[43][44] The radar continues to progress further in terms of integration, with
newer variants being integrated with thermal imagers for visually tracking targets
detected by the radar. Up to 10 BFSR-SR can be networked together for network
centric operation. It is in use with the Indian Army and the BSF as well as export
customers.
Super Vision-2000, an airborne 3D naval surveillance radar, meant for helicopters

and light transport aircraft. The SV-2000 is a lightweight, high performance,
slotted array radar operating in the X-Band. It can detect sea-surface targets such
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as a periscope or a vessel against heavy clutter and can also be used for navigation,
weather mapping and beacon detection. The radar can detect a large vessel at over
100 nautical miles (370 km). It is currently under modification to be fitted to the
Advanced Light Helicopter and the Navy's Do-228's. Variants can be fitted to the
Navy's Ka-25's as well.[45] The radar has been inducted by the Indian Navy and a
more advanced variant of the Super Vision, known as the XV-2004 is also
operational, and features an ISAR, SAR Capability.
Swordfish Long Range Tracking Radar, a 3D AESA was developed with assistance
from Elta of Israel and is similar to Elta's proven Green Pine long-range Active
Array radar. The DRDO developed the signal processing and software for tracking
high speed ballistic missile targets as well as introduced more ruggedisation. The
radar uses mostly Indian designed and manufactured components such as its critical
high power, L Band Transmit-Receive modules and other enabling technologies
necessary for active phased array radars. The LRTR can track 200 targets and has
a range of above 500 km. It can detect Intermediate-range ballistic missile. The
LRTR would be amongst the key elements of the Indian Ballistic Missile Defence
Programme. DRDO would provide the technology to private and public
manufacturers to make these high power systems.[46]
3D Multi-Function Control Radar (MFCR) was developed as part of the Indian

anti-ballistic missile programme in cooperation with THALES of France. The
MFCR is an active phased array radar and complements the Swordfish Long Range
Tracking Radar, for intercepting ballistic missiles. The MFCR will also serve as
the fire control radar for the AAD second tier missile system of the ABM
programme. The AAD has a supplementary role against aircraft as well and can
engage missiles and aircraft up to an altitude of 30 km. The MFCR fills out the
final part of the DRDO's radar development spectrum, and allows India to
manufacture long-range 3D radars that can act as the nodes of an Air Defence
Ground Environment system.
2D Low Level Lightweight Radar (LLLR) for the Indian Army, which requires
many of these units for gap-filling in mountainous terrain. The Indian Air Force
will also acquire then for key airbases. The LLLR is a 2D radar with a range of
40 km against a 2 square metre target, intended as a gapfiller to plug detection gaps
versus low level aircraft in an integrated Air Defence Ground network. The LLLR
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makes use of Indra-2 technology, namely a similar antenna array, but has roughly
half the range and is much smaller and a far more portable unit. The LLLR
can track while scan 100 targets and provide details about their speed, azimuth and
range to the operator. The LLLR makes use of the BFSR-SR experience and many
of the subsystem providers are the same. Multiple LLLRs can be networked
together. The LLLR is meant to detect low level intruders, and will alert Army Air
Defence fire control units to cue their weapon systems.[47]
3D Short Range Radar for the Indian Air Force - ASLESHA: The ASLESHA
radars have a range of approximately 50 km against small fighter-sized targets and
will be able to determine their range, speed, azimuth and height. This radar will
enable the Indian Air Force Air Defence units to accurately track low level
intruders. The radar is a semi-active phased array with a 1-metre square aperture.
The DRDO was in discussions with the Indian Navy to mount these systems on
small ships.
Multi-mode radar, a 3D radar is a HAL project with DRDO's LRDE as a subsystem

provider. This project to develop an advanced, lightweight Multi-mode fire control
radar for the LCA Tejas fighter had faced challenges and was delayed. It has now
been completed with Elta's (Israel) assistance. The multi-mode radar has range (for
detection of a small fighter target) greater than 100 km, can track 10 targets, can
engage 2 targets and uses lightweight system. It has been revealed that an all new
combined signal and data processor had been developed, replacing the original
separate units. The new unit is much more powerful and makes use of
contemporary ADSP processors. The radar's critical hardware has also been
developed and validated. The software for the air-to-air mode has been developed
considerably (including search and track while scan in both look up and look down
modes) but air-to-ground modes are still being worked upon. The radar
development was shown to be considerably more mature than previously thought.
At Aero India 2009, it was revealed that the 3D MMR project has been superseded
by the new 3D AESA FCR project led by LRDE. The MMR has been completed
with Elta Israel's assistance and now involved Elta EL/M-2032 technology for Airto-Ground mapping and targeting. This "hybrid" MMR has been tested, validated
and will be supplied for the initial LCA Tejas fighters.
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DRDO has indigenised components and improved subsystems of various other

licence produced radars manufactured at BEL with the help of BEL scientists and
other researchers. These improvements include new radar data processors for
licence produced signal radars as well as local radar assemblies replacing the
earlier imported ones.
Apart from the above, the DRDO has also several other radar systems currently under
development or in trials, these include:
1) BEL Weapon Locating Radar: A 3D Radar successfully developed from the
Rajendra fire control radar for the Akash system, this radar uses a passive
electronically scanned array to detect multiple targets for fire correction and
weapon location. The system has been developed and demonstrated to the Army
and orders have been placed [48] In terms of performance, the WLR is stated to be
superior to the AN/TPQ-37, several of which were imported by India as an interim
system while the WLR got ready.
2) Active Phased Array radar: a 3D radar for fighters, a MMR follow on, the APAR
project aims to field a fully-fledged operational AESA fire control radar for the
expected Mark-2 version of the Light Combat Aircraft. This will be the second
airborne AESA programme after the AEW&C project and intends to transfer the
success DRDO has achieved in the ground based radar segment to airborne
systems. The overall airborne APAR programme aims to prevent this technology
gap from developing, with a broad based programme to bring DRDO up to par with
international developers in airborne systems, both fire control and surveillance.
3) Synthetic aperture radar & Inverse synthetic aperture radar: the DRDO's LRDE is
currently working on both SAR and ISAR radars for target detection and
classification. These lightweight payloads are intended for both conventional fixed
wing as well as UAV applications.
4) Airborne Warning and Control: a new radar based on active electronically scanned
array technology. The aim of the project is to develop in-house capability for high
power AEW&C systems, with the system covering the development of a S-Band
AESA array. The aircraft will also have data-links to link fighters plus
communicate with the IAF's C3I infrastructure as well as a local SATCOM
(satellite communication system), along with other on-board ESM and COMINT
systems.[49]
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5) Medium Range Battlefield Surveillance Radar: in 2009, the LRDE (DRDO) noted
that it was working on a Long-range battlefield surveillance radar. It is possible
that the BFSR-LR project has replaced this earlier project and the Indian Army will
utilise the BEL built ELTA designed BFSR-MR's for Medium Range surveillance
while using the LRDE designed systems for Long Range surveillance. The 2D
radar will track ground targets and provide key intelligence to the Indian Army's
artillery units, with the resultant information available on various tactical networks.
6) 3D Medium Power Radar: a spin-off of the experience gained via the 3D MFCR
project, the 3D Medium Power Radar project is intended to field a radar with a
range of approximately 300 km against small fighter sized targets. Intended for the
Indian Air Force, the radar is an active phased array, and will be transportable. It
will play a significant role being used as part of the nodes of the Indian Air Force's
enhanced Air Defence Ground Environment System.
7) 3D Tactical Control Radar: a new programme, the TCR is an approximately
150 km ranged system for use by the Indian Army and Air Force. A highly mobile
unit, it will also employ open architecture to provide easy upgrades, and a variety
of modes and capabilities depending on the software fit. The aim of the 3D Medium
Power Radar and TCR is to offer systems which can be deployed in a variety of
roles, from fire control to surveillance, and not be tied to one role alone.
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CHAPTER 3
VERIFICATION
OF
DIGITAL
RECEIVER
SYSTEM ARCHITECTURE
INTRODUCTION
Digital Receiver is a device used to decode and also to receive the digitally
transmitted television services and related deals via cables, satellite or terrestrial
antenna, particularly in DVB format. These Digital Receivers are also called SET-TOP
BOX or DIGITAL DECODER. These receivers can be either integrated directly into
play back devices such as tuners or also as stand-alone devices.
There are also receivers with integrated hard drivers which help in storage of
previously stored data. It receives RF signals from 2 channels of ADC and they are
sampled. It then generates Pulse Description Word from 2 signals coming from 2
channels of ADC and transfers the PDW's to the processor.
Threats are Land-based, Ship based or Airborne and are of different types e.g.:
Search or Target Acquisition
Target Tracking
Missile Guidance
Target illuminator
Airborne Interceptor
Fire Control
Threats have different Signal Characteristics like, Pulse, CW, ICW, RF, PRI,
PW stable / variable, Intra-Pulse Modulation characteristics (e.g. Barker Code, Chirp),

Steady or Scan characteristics (ms to several seconds). Threats are distributed over a
wide frequency range (0.5 GHz to 40 GHz). Simultaneously the Scenario contains
multiple CW, ICW or Pulse emitters generating a pulse density of several Million
Pulses per sec. In addition non-military electro-magnetic signals are in the air (Civil
Radars and Communication).
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Radars are an active system, which transmit RF and does the processing with
the reflected signal; hence bandwidth requirement for processing will be as low as few
MHz. The EW receivers are passive receivers, which blindly look around in the
interested frequency bands which will be of the order of GHz. Hence for high
probability of intercept instantaneous bandwidth should be high, typically of the order
of GHz.
Radar is interested in its own return, it can use a matched filter detection
scheme to get the processing gain. An EW Receiver does not know the incoming
signals, it cannot use matched filter detection but has to use a bank of filters covering
the entire BW for detection.
In case of Digital TV's, these Digital Receivers are used in conjunction with
a decoder card also called SMART CARD for decryption of coded TV offers. The card
contains PIN (unique identification number) which is necessary to unlock the card and
it also helps in enabling the decoder to decode the encrypted data stream. The
commonly known decryption methods are INTER ALIA, SYSTEMS NAGRA
VISION, SECA or BETA CRYPT.
Digital Receiver or also called as CHANELLIZER have the following characteristics:
1) Performance
Signal separation id possible even if overlapping in time domain is done

(multiple signal detection and measurement).
Processing gain improves signal to noise ratio.
Real-time and detailed measurement of standard and complex signal

parameters.
2) Reliability
Digital hardware elements are more reliable.
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MULTI-BIT DIGITAL RECEIVER
Fig 1: Multi-bit Digital Receiver Architecture

Fig. shows a Multi-bit Digital Receiver architecture which consists of:
1. Analog to Digital Converter [ADC]: An analog-to-digital converter (ADC) is a
device that converts a continuous physical quantity (usually voltage) to a digital
number that represents the quantitys amplitude.
2. Field Programmable gate Array [FPGA]: A field-programmable gate array
(FPGA) is an integrated circuit designed to be configured by a customer or a
designer after manufacturing hence field programmable. The FPGA
configuration is generally specified using a hardware description language
(HDL).
3. Digital Signal Processor [DSP]: Digital signal processing (DSP) is the
numerical manipulation of signals, usually with the intention to measure, filter,
produce or compress continuous analog signals. It is characterized by the use of
digital signals to represent discrete time, discrete frequency, or other discrete
domain signals in the form of a sequence of numbers or symbols to permit the
digital processing of these signals.
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DIGITAL RECEIVER SYSTEM ARCHITECTURE
Multi-bit Digital Receiver is an FPGA based Electronic Support Measure
(ESM) system whose main functionalities are:
Sampling of 2 RF signals.
Real time processing of sampled signals for Pulse Parameter Extraction.
Pulse Description Word (PDW) generation for RF pulses coming on two

channels.
Operations performed by Digital Receiver are as follows:
Signal Detection is based on Fast Fourier Transform (FFT) processing.
75% overlapped FFT processing is used.
Software configurable threshold determines the sensitivity of the system.
96 FFT filters of 5.27 MHz each are employed to cover 500 MHz Band width.
Up to 4 peaks are detected in each FFT frame.
Up to 4 peaks are tracked from one FFT frame to next FFT frame to detect the
fall of pulse.
Fine parameter measurement is performed on FFT filter outputs.
Generation of Pulse Descriptor Word for each intercepted pulse.

The system should process data from 2 RF channels in real time. The incoming
RF signal is a band-limited signal of 750MHz to 1250 MHz. The instantaneous

bandwidth at any time is 500 MHz. The incoming data is being sampled at 1350 MHz
at ADC. The system outputs Pulse Description Words (PDW) after processing the RF
input signals. The system should be capable of handling up to 4 overlapping pulses and
generate the PDWs for them. The system must be capable of handling up to 2.5 million
pulses per second per RF channel.
PDWs of individual channels should be combined based on center Frequency
and Pulse Width. The merging happens for 16 unique type of PDWs. Every 50 s the
accumulated PDWs from each channel are written to the common FIFO. Criteria for
combining the PDWs shall be: frequency deviation of 2 MHz, Pulse width deviation of
20 ns & signal power of 1dB. The system provides sufficient number of status registers
for debugging purposes.
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Fig 2: Digital Receiver System Overview

This fig. shows the Digital Receiver System. It consists of the following blocks
which when interfaced will perform the required function.
1) ADC Interface
2) Wind FFT
3) Receiver Channel Processor
4) Frame Info Buffer
5) Blanking Interface Top
6) Saturation Indication
7) RF Control Interface
8) Parameter Measurement
9) PDW Merging Top
10) FPGA Register Interface
11) Programming Sequence
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The Receiver should intake data from the 2 ADC channels at 337.5 MHz DDR.
The ADC programming serial interface should operate at 50MHz. The programming
interface of Integrated Frequency Synthesizer should operate at 12.5 MHz. The entire
processing in the Digital Receiver should happen at 168.75 MHz. It should be capable
of generating up to 2.5 million Pulse Description Words (PDWs) per second. The
system must be able to detect up to 4 overlapping pulses.
ADC INTERFACE MODULE

The ADC interface module captures the data from a dual channel ADC.
Provides the captured data through a FIFO interface for further processing. Programs
the ADC through Serial Interface.
The main functionalities include:
Converting differential data into single ended data by instantiating IBUFDS.
Converting the differential source synchronous clock into a single ended clock
by instantiating IBUFGDS.
Perform calibration of ADC.
Programs the registers of ADC through serial interface.
Provides clock to the ADC serial program interface.
Uses ODDR component for driving the clock.
To facilitate meeting of timing at the ADC side, the clock is inverted.
Instantiate 2 instances of logic for ADC Data Capture.

ADC Interface Module captures the data from the dual channel ADC operating
at 337.5 MHz DDR and stores them in the memory for further processing.
It consists of:
1) ADC Data Capture Wrapper Module:
It converts 8 bit DDR data to 16 bit SDR data.
It rearranges delayed and non-delayed data of 16 bit into 32 bit for

storing into FIFO as per the sample order.
It instantiates ADC Data Capture module.
2) ADC Data Capture Module:
Instantiates a BRAM configured as Simple Dual Port RAM.
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The write port of BRAM is 32-bit wide and has 1024 locations.
The read port of BRAM is 64 bit wide and has 512 locations.
BRAM is configured to register the data read twice in order to improve

the timing.
The control logic associated with BRAM configures it as a packed based

FIFO. The packet is fixed size of 256 Bytes.
Generates control signals for writing and reading into the BRAM.
3) ADC Control:
Performs on command calibration after power on calibration of the

ADC.
Programs the ADC control registers through serial interface.
Instantiates ADC calibration module.
Instantiates ADC programming module.
4) ADC Calibration FSM:
Reads the commands from the command FIFO.
Programs the ADC registers through the serial interface of ADC.
To enable IOB registering, data and chip select are registered

unconditionally.
5) ADC Programming FSM
WIND FFT MODULE

The Wind FFT Module accepts data from both the channels and performs
windowing followed by FFT computation.
It consists of following sub modules:
1) Two instantiations of Window Function
2) 256 point FFT module
Outputs from the Window function module are real values. A single FFT engine
can be used to process data from 2 channels with real values. Hence data from channel
0 is given as real part of data sample, while data from channel 1 is given as imaginary
part of data sample.
Window Function
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This performs windowing on the input data samples. The main functionalities include
Generation of read address for retrieving coefficients from Coefficient banks
Performs windowing by multiplying the input data samples with the coefficients
It consists of:
1) Co-efficient Block
2) Co-efficient Bank
3) Co-efficient generation
FFT Module
It performs the processing of 256 point FFT. 4 points are taken at a time and are
processed with Radix-4 butterfly to yield 4 point result. This operation is performed
over all the points. This operation is repeated for log4256 = 4 stages iterations with
different twiddle factors and different points.
The input data is coming at 160MHz with 8 samples every clock. Thus 256
samples are received in 32 clocks. To maintain this throughput, the FFT engine has to
work in such a way that each pipelined stage completes its operation in 32 clocks.
This is possible if each stage finishes its operation in 32 clocks with 2 Radix4 butterflies processing in total 8 points at every clock. Note that the data is accepted
by each butterfly in a particular order and the result is in digit-reversed fashion. Input
data is arranged in the required order by the Pre-processor module and the digitreversed data is converted into normal order by the Post-processor module.
Data obtained in the Normal order is a result of complex inputs fed to the FFT
engine. Real and imaginary parts of complex inputs consist of two different independent
real sequences. So a final stage of processing is required to extract the real and
imaginary parts of FFT data corresponding to individual channels.
FFT Architecture Module consists of:
1. Pre-Processor Module
2. Stage Control
3. Memory Module
4. Compute Unit
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5. Radix 4
6. Twiddle Multiplier
7. Control Block
8. Twiddle Block
9. Twiddle Memory
10. Real_rom256_2_16
11. Imag_rom256_2_16
12. Post Processor Stage
13. Post Processor Module
14. Channel Processor Stage
15. Channel Processor Module
RECEIVER CHANNEL PROCESSOR

This module instantiates following modules:
1. Peak Detector
2. Filter bank
Peak Detector Module
Peak Detector module has the following functionalities:
Accept the data from the FFT module.
Computes the magnitude of the complex data samples received.
Determine 4 peaks with highest magnitude from every frame, taking into
consideration side lobe rejection.
Determine the starting address, end address, time of arrival of the peaks from
the time of appearance of the peak to their disappearance.
Computes power and number of frames across the pulse. Power is calculated by
adding FFT power with attenuation value.
Form the Detector Words for every peak detected, and at regular intervals for
peaks that are present continuously (CW signals).
Peak Detector module consists of following sub-modules:

1. Peak Data In Write
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2. Peak Serializer Memory
3. Peak Data Out Reader
4. Detector Word Generator
5. Peak FIFO DEMUX
6. Peak Info Buffer
Filter Bank Module
The Filter Bank Module performs the following functions:
Instantiates 4 Filter modules.
Interacts with Peak detector module.
Separates out the data from individual emitters and gives it to Pulse Parameter
Measurement module.
FRAME INFO BUFFER

This module stores the time of arrival and start address values of the frame.
Instantiates a XILINX FIFO to store the values.
Read and write ports are 32 bit wide and have a depth of 32.
BLANKING INTERFACE TOP
This module instantiates:

o 4 instances of Blanking Interface Wrapper
o 2 Instances of Blanking Info Buffer
Computes the blanking information for each frame and write them into two
FIFOs corresponding to the two channels.
Blanking Interface Top consists of:

1) Blanking Interface Wrapper
2) Blanking Interface
3) Blanking Info Buffer
SATURATION INDICATION
This module generates ADC over range flag.
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ADC over range flag will be asserted high when there is a saturation indication
from ADC.
RF CONTROL INTERFACE
This module is to provide interface between narrow band FPGA and different RF
modules.
PARAMETER MEASUREMENT
Parameters are measured for both the channels. PDWs are compared between
the channels based on TOA, frequency and PW. If there is a match, a single PDW is
generated merging both the channel PDWs.
The Parameter Measurement consists of:
1) Fine Frequency Measurement
2) PW & TOA Measurement
PDW MERGING TOP

The PDW Merging module implements the following functionalities:
Merging is done when frequency, pulse width and time of arrival from the two
channels are matching and PDWs from both the channels are available within
five clock cycles.
Up convert the frequency from 750-1250 MHz to 1-18 GHz using local
oscillator settings.
The resolutions of the parameters are updated in this module.
The PDW Merging module operates at 168.75MHz.
This module instantiate the following module:

1) PDW Merging Module
2) PDW Merge FIFO Top Module
3) Parameter Translate Module
4) PDW Trans FIFO Top Module
5) Wideband FPGA Interface Module
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Tag Hi (4)
1011
Ant ID
(4)
Amplitude2
(10)
Amplitude1
(10)
TagLo(4)
0010
Time of Arrival in ns (32)

CH_ID
(2)
MOP
(2)
ADC Sat
(1)
Phase Difference (9)
Timer Overflow
(13)
CW FLAG
(1)
Frequency in 100s of
KHz (18)
Pulse Width in ns (18)
Spare (32)
Fig 3: PDW Format Overview
FPGA REGISTER INTERFACE MODULE
This module contains set of registers required for the operation of digital
receiver.
Registers can be updated from DSP host interface or embedded sub-system

interface based on the mode.
Registers can be accessed from DSP host interface or embedded sub-system

interface based on the mode.
When debug mode is enabled, updating and accessing happens through

embedded subsystem module else DSP host interface is selected.
PROGRAMMING SEQUENCE
Clock Requirements
The input Reference clock to IFS is 80 MHz.
Serial programming clock is of 12.5 MHz.
IFS to generate 1350 MHz frequency. This clock is used by ADC for sampling
the input data.
Register Programming Sequence

1) First R counter latch is programmed.
Control bits Bit-0 and Bit-1 are assigned values 1 and 0 respectively.
This selects the R counter latch for Programming.
Reference counter bit-set is programmed with a value of 80.
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ANTIBAND
BACKLASH
RESERVED SELECT TMB LDP
PULSE
CLOCK
WIDTH
CONTROL
BITS
14 BIT REFERENCE COUNTER
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig 4: R Counter Latch Overview

2) Then Program Control latch.
This selects the Control latch for Programming.
MUX out Control bit-set is set to 001 to select Digital Lock Detect
output (Active High).
Pre-scale value bit-set is set to 00 to fix the pre-scaler ratio to 8/9.
Mute Till Lock Detect (Bit-11) is set to 1.This ensures that Outputs are
COUNTER
RESET
CP
3 STATE
OUTPUT
POWER
LEVEL
CURRENT
SETTING 1
CP GAIN
CURRENT
SETTING 2
MUTE
TILL LD
POWER
DOWN 1
PRESCALE
VALUE
POWER
DOWN 2
not switched on until the PLL is locked.
MUXOUT
CONTROL
PDP
CORE
POWER
LEVEL
CONTROL
BITS
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig 5: Control Latch Overview

3) Finally Program N counter latch.
This selects the N counter latch for Programming.
RESERVED
B counter bit-set is programmed with a value of 168.

GAIN
13-BIT B COUNTER
CP
DIVIDE
BY 2
A counter bit-set is programmed with a value of 6.
DIVIDE
BY 2 SEL
CONTROL
BITS
5-BIT A COUNTER
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig 6: N Counter Latch Overview

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VERIFICATION PLAN OF DIGITAL RECEIVER SYSTEM
ARCHITECTURE
VERIFICATION PLAN TABLE
Test Case ID
Test
Case
Name
Test Case Description
Expected Results
System Level Tests

1. After initial set-up, feed 1.
The
PDWs
the signal provided by the generated

TC_SYS_01
Processing the customer.

test signals
should
correspond
to
2. Observe the PDWs expected

generated by the system. provided
3. Repeat the above steps.
results
by
the
customer.
ADC Interface Module

1. Program the ADC to
capture
2.
data.
Connect
signal
generator to channel 0.
3. Through user interface,
programmed to capture
Capturing
TC_ADC_01
Data - Data
integrity
data of 4KB (4 kilo

samples).
4. Read the data captured
data
through
UART
interface and dump to a

file.
5. Plot the data and
The
plotted
data
(captured for channel

0 as well as channel 1)
should correspond to
sine wave of 800
MHz. There should
not be any samples
which show abrupt
changes.
examine the waveform.

6. Repeat the above steps
for channel 1 data
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Test Case ID
Test
Case
Name
Expected
Results
SSRAM Interface Module

1.
Through
UART
user
interface, enter the command for

""mem
test
<chip
id>""
2. The software writes the data to The software

the chip id (0, 1, 2 or 3) and reads should report
TC_RAM_01
User Specified back the data and verifies it. the

data test
test
3. Repeat the above steps for all "passed"

the memory interfaces (chip all
ids)."
as
for
memory
interfaces
4. User data can be walking

ones, incremental data or any
other arbitrary data.
Precision Clock Conditioner Interface Module
1. This is the default setting for
Program
TC_FSY_01
to clock
generation.
generate 1350 2. After the boot-up, check the

MHz clock for clock
ADC
generated
Frequency
by
the
synthesizer
at
appropriate TP.
1. This is the default setting for
Program
TC_FSY_02
to clock
generate
168.75
generation.
2. After the boot-up, check the

MHz clock
for the FPGA
generated
Frequency
by
the
synthesizer
at
appropriate TP.
2015-16
Clock
generated
should
correspond to
1350 MHz.
Clock
generated
should
correspond to
168.75 MHz.
Page 35

Test Case ID
Test
Case
Name
Test Case Description Expected Results

1.
Though
UART
interface, program the

Frequency synthesizer
TC_FSY_03
Program
to to generate a clock of
generate
any frequency provided by
clock given by the

the user.
User.
2. Check the clock

generated
by
Clock generated should

correspond
to
user
provided value.
the
Frequency synthesizer
at appropriate TP.
RF Control Interface Module
TC_RFC_01
Check
Input pins
the
1.
Through
interface
user The values read and the
read
the inputs supplied should
values of input pins
be same
Pulse Parameter Measurement Block

Corresponding to every
1. Feed a Pulse of width
10
samples
clocks
separated by around 1
Measuring
TC_PPM_01
us
continuously
to
Time of Arrival channel 0 of the DUT.

of Pulse
2. Examine the PDW

generated by the DUT
3. Repeat the above
procedure for channel 1
pulse fed to the DUT, a

PDW
should
be
generated.
Examine the Time of
Arrival field in the
PDW generated. Time
of
arrival
should
be
measured
separated
exactly by the amount

as given in input with
25 ns tolerance
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Test
Case Test
ID
Case
Name
Expected Results
1. Feed a Pulse of width 10 pulse fed to DUT, a

samples clocks separated PDW
by
around
should
us generated.
continuously to channel 0 Examine
TC_PPM_02
of
the
2.
Examine
DUT. width
the
be
the
field
Pulse
in
the
PDW generated PDW. This
Measuring
generated by the DUT should match the input
Pulse Width
3.
Repeat
the
above [Determined
through
procedure by generating frequency and Duty

pulses of different width in cycle
values].
the range 25 ns to 200 us in The measured values

steps.
4.
should be correct with
Repeat
the
above tolerance of +/- 25 ns or
+/-1% of pulse width,

whichever is bigger.
1. Feed pulses of width 10

sample clocks separated by
around 200 ns continuously
to channel 0 of the DUT.
2.
Measuring
TC_PPM_03 Carrier
Frequency
Examine
the
PDW
generated by the DUT

3.
Repeat
the
above
procedure by generating
pulses with different carrier
frequency in the range 750
MHz to 1250 MHz in steps.
4.
Repeat
the
PDW
should
be
generated.
Frequency field in the
PDW should indicate
the frequency with an
accuracy of 5 MHZ.
above
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Test Case ID
Test
Name
Case Test
Case
Description
Expected Results
1. Feed pulses with

Frequency
modulation to channel
0 [See notes section]
2. Examine the Type
TC_PPM_04
Detecting
FMOP
of Modulation field in
the PDW generated
3. Repeat the above
procedure
different
with
signals
4. Repeat the above
PDW
should
be
generated.
Type of modulation field
in
the
PDW
indicate
should
Frequency
modulation on Pulse
procedure for channel

1
1. Feed pulses with
Phase modulation to
channel 0 [See notes
section]
2. Examine the Type
TC_PPM_05
Detecting
PMOP
of Modulation field in
the PDW generated
3. Repeat the above
procedure
different
with
signals
4. Repeat the above
PDW
should
be
generated.
Type of modulation field
in
the
indicate
PDW
should
Phase
modulation on Pulse
procedure for channel

1
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Test
ID
Case Test Case

Name
Expected Results
1. Feed pulses with Frequency Corresponding
to
modulation + Phase modulation every pulse fed to

to channel 0 [See notes section] the DUT, a PDW
Detecting
TC_PPM_06 FMOP+
PMOP
2.
Examine
the
Type
of should be generated.
Modulation field in the PDW Type of modulation

generated
field in the PDW
3. Repeat the above procedure should

with
different
indicate
signals Phase modulation as
4. Repeat the above procedure for well as Frequency

channel 1
modulation on Pulse
1. Feed pulses of width 10 sample

clocks separated by around 200
ns continuously to channel 0 of Corresponding
Detecting
signals
TC_PPM_07 with
no
modulatio
n
the
to
DUT. every pulse fed to
2. Examine the PDW generated the DUT, a PDW

by
the
DUT should be generated.
3. Repeat the above procedure by Type of modulation

generating pulses with different field in the PDW
carrier frequency in the range 750 should indicate No
MHz to 1250 MHz in steps. modulation scheme
4. Repeat the above procedure for
channel 1
1. Feed pulses of width greater
than 200 us to channel 0 of the
Detecting
TC_PPM_08 CW
signals
DUT.
2. Examine the PDW generated
by
the
DUT.
3. Repeat the above procedure for

channel 1
Corresponding
to
every pulse fed to

the DUT, a PDW
should be generated.
Examine the CW
flag in the PDW
generated. It should
be set.
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Test Case ID
Test Case
Name
Expected Results
1. Feed pulses of width

10
sample
clocks Corresponding to every
separated by around 200 pulse fed to the DUT, a

ns
continuously
to PDW should be generated
channel 0 of the DUT. -
TC_PPM_09
when
the
pulse
Measuring
2. Examine the PDW amplitude crosses noise
Pulse
generated by the DUT floor.
amplitude
3. Repeat the above Examine
the
Pulse
procedure by generating amplitude field in the

pulses
with
signal
different PDW generated. It should

strength. correspond
to
given
4. Repeat the above input.

Table 1: Verification Plan
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VALIDATION TEST CASES TABLE
Test Case Test
Name
Case
Description
Test Bench Requirements
1. Test signal generated

through Octave is fed to the
DUT. Note that test signal is
Test-bench
feeds given to both the channels of
Data
on pulses on both the ADC.
both
the ADC channels and 2. Test signal consists of
channels
generated CFWs are Emitter which emits pulses

examined.
of
100
separated
ns,
by
which
1
are
us.
3. Read the CFWs generated

and examine the results
Expected
Results
1. PDW should
be generated for
each
of
the
pulses correctly
by
both
the
ADC channels.
CFWs
should
give the average

power,
pulse
width
and
frequency of the
pulses.

Pulse
Test-bench
feeds
width
2000 pulses on one of
Measurem
the ADC channel.
ent
The generated CFWs
Accuracy
are examined.
DUT.
2. Test signal consists of four
Emitters which emits pulses
of
100
ns,
which
are
separated by 1 us and are

exactly
overlapped.
CFWs will not

be
generated
since the pulse

width
is
less
than 100 ns.
3. Read the CFWs generated

and examine the results
CFWS
Mode of Operation
Mode
of
Operation
for both the channels

of
the
assigned
values.
DUT
are
specific
generated
Test bench assigns values to should have the
mode of operation ports of value
both the channels of the mode
DUT
in
the
of
operation filed
as assigned in
the test bench.
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Test Case Test
Name
Case
Description
Test Bench Requirements
Expected
Results
CFWS
generated
Mode of Operation
Antenna
Info
for both the channels Test bench assigns values to

of
the
DUT
assigned
are antenna info ports of both the
specific channels of the DUT
should have the

value
in
the
mode
of
operation filed
values.
as assigned in
the test bench.
DUT. Note that test signal is
given to both the channels of
ADC.
Performan
ce
Measurem
ent
Provide 10000 pulses

to both the channels
of DUT.
2. Test signal consists of

Emitter which emits pulses
of 100 ns, with a PRI of 500
ns with different frequency
than
the
frequency
of
previous pulse. Frequency
Some
of
the
pulses will be
missed since the
current
filter
module cannot
handle
this
bandwidth.
separation should be more

than
5.27
MHz
3.examine the results

Pulses stored in data
files are fed to one
channel of the DUT.
Customer
The test cases are
test cases
tabulated
in
separate table called

"Customer
CFWS
Test bench feeds the data
stored in the data files
provided by the customer.
Test
to
be
generated with
the parameters
mentioned
the
in
expected
results.
Cases "
Table 2: Validation Test Cases
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VERIFICATION TEST CASES TABLE
Test Case Test
Name
Case
Description
Expected Results
Observed Results
frequency = 750 frequency = 750 +/- 1 frequency = 749.125

MHz
MHz
Pulse
power=7dbm
power=7 +/- 1dBm power=1.325dBm
Width
pw=100ns
pw=100ns +/- 25 ns pw=97.8ns
Resolution pri=1us
pri=1us
Measurem
TOA=0
ent
MHz
+/-
25 ns pri=1.00048
us
TOA=0
TOA=7.575
us
FMOP=NILL
FMOP=NILL
FMOP=NILL
PMOP=NILL
PMOP=NILL
PMOP=NILL
no of pulses=10
no of pulses=10
no of pulses=10
frequency = 750 frequency = 750 +/- 1 frequency = 750.375

MHz
MHz
power=7dbm
power=7 +/- 1dBm power=
Frequency
pw=100ns
pw=100ns +/- 25 ns pw=100.75
ns
Measurem
pri=10us
pri=10us +/- 25 ns pri=
us
ent
TOA=0
TOA=0
TOA=7.494us
FMOP=NILL
FMOP=NILL
FMOP=NILL
PMOP=NILL
PMOP=NILL
PMOP=NILL
no of pulses=2
no of pulses=2
no of pulses=2
MHz
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-1.30
9.987
dBm
Page 43

Test Case Test
Name
Case
Description
frequency = 900 MHz
Pulse
Width and
PRI
Measurem
ent
power=7dbm
Modulatio
pri=1us
TOA=0
FMOP=NILL
PMOP=NILL
frequency = 900 +/- 1 frequency = 901.04

MHz
MHz
pw=0.1us +/- 25 ns pw=100.75
ns
pri=1us
us
+/-
25 ns pri=
TOA=7.574us
FMOP=NILL
FMOP=NILL
PMOP=NILL
PMOP=NILL
No of pulses =5
no of pulses=5
freq=800+/- 1 MHz
pri=50us
pri=50us +/- 25 ns
pw=10us
pw=10us +/- 25 ns
of
9.987
TOA=0
freq=800MHz
no
Observed Results
power=7 +/- 1dBm power= -1.54 dBm
pw=0.1us
Mo of pulses = 2
Frequency
Expected Results
pulses=2 no
of
pulses=2
TOA=0ns
TOA=0ns +/- 25 ns
power=7dbm
power=7 +/- 1dBm
FMOP=YES(centre
FMOP=YES(centre
freq +/- 100 MHz)
freq +/- 101 MHz)
freq=1050MHz
freq=1050+/- 1 MHz freq=1050.25 MHz
pri=50us
pri=50us +/- 25 ns pri=NA
pw=10us
pw=10us +/- 25 ns pw=675.75
of
pulses=2 no
of
pulses=2 no
of
ns
Phase
no
pulses=2
Modulatio
TOA=0ns
TOA=0ns +/- 25 ns TOA=0ns +/- 25 ns
power=7dbm
power=7 +/- 1dBm power= 1.5 dBm
FMOP=NILL
FMOP=NILL
FMOP=NILL
PMOP=Present(barker PMOP=Present(barker PMOP=Present(bar

code 13)
code 13)
2015-16
ker code 13)
Page 44

Test
Case
Name
freq
750
MHz
length of data =50us

phase difference= pi/2
Instantaneous
radian
Phase
power=7dbm
Measurement
toa=0ns
CW
25
ns
phase difference= pi/2
toa=0ns
+/+/-
1dBm
25
type=
ns
CW
NILL
PMOP= NILL
0ns; TOA = 0ns +/- 25 ns;
pw=
Measurement
length of data =50us +/-
FMOP=
PMOP= NILL
Resolution
freq = 750 +/- 1 MHz
power=7
FMOP=NILL
Frequency
Results
radian
type=
TOA
Observed
Expected Results
1us pw= 1us +/- 25 ns
PRi=10us
PRi=10us +/- 25 ns
power=-3dbm
power=-3
+/-
1dBm
no of pulses in first no of pulses in first

pattern=
frequency
5 pattern=
of
first frequency
5
of
first
pattern = 850 MHz pattern = 850 +/- 1 MHz

frequency
of
second frequency
pattern = 856 MHz
of
second
pattern = 856 +/- 1 MHz
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Test
Case
Name
Observed
Expected Results
Results
PW = 400ns +/- 25 ns and

PW = 400ns and PRI=
1.6us for all the patterns.
no of pulses in each
pattern =50 TOA= 0ns
power =7 dbm for all the
Maximum
Number
of
Pulses
Measurement
patterns
pattern 1 freq = 750
MHz
MHz
MHz
pattern 4 freq = 825 Mhz
PRI= 1.6us +/- 25 ns for

all the patterns +/- 25 ns.
pattern =50 TOA= 0ns +/25
ns
power =7 +/- 1dBm for

all the patterns +/- 25 ns
pattern 1 freq = 750 +/- 1
MHz
MHz
MHz
MHz
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Test
Case Test
Name
Case
Description
filename
case1_overlapped.da
t
750
MHz
pw=0.1us
TOA=0ns
case1_overlapped.dat
freq= 750 +/- 1 MHz freq=
770
+/-
ns pw=100
ns
TOA=0ns +/- 25 ns pri=994
ns
+/-
25
1dBm TOA=0ns +/- 25 ns
pattern2:
pattern2:
MHz
pw=0.1us
power=2.375dBm
freq= 770 +/- 1 MHz pattern2:

pw=0.1us +/- 25 ns freq= 769.75 MHz
pri=1us
pri=1us
749.000
pw=0.1us +/- 25 ns MHz
power=7
power=7dbm
+/-
25
ns pw=94
ns
TOA=0ns +/- 25 ns pri=1us +/- 25 ns
TOA=0ns
Overlapped
power=7dbm
Pulses
pattern3:
Detection
freq=
790
power=7
+/-
1dBm TOA=0ns +/- 25 ns
pattern3:
MHz
pw=0.1us
power=-2.375dBm
freq= 790 +/- 1 MHz

pw=0.1us +/- 25 ns pattern
pri=1us
pri=1us
+/-
25
4:
ns freq=
812.125
TOA=0ns +/- 25 ns MHz
TOA=0ns
power=7
power=7dbm
pattern
freq=
filename
pri=1us
pri=1us
freq=
Observed Results
pattern1:
pattern1:
freq=
Expected Results
4:
810
MHz
pw=0.1us
TOA=0ns
power=7dbm
FMOP
NILL
PMOP
NILL
pattern =100
1dBm pw=94
pattern
ns
4: pri=1us +/- 25 ns
freq= 810 +/- 1 MHz TOA=0ns +/- 25 ns

pw=0.1us +/- 25 ns power=-2.25dBm
pri=1us
pri=1us
+/-
+/-
25
ns FMOP
NILL
TOA=0ns +/- 25 ns PMOP
NILL
power=7
+/-
1dBm no of pulses in
FMOP
NILL each pattern =100
PMOP
NILL
pattern =100
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Test
Case Test
Name
Case
Description
TOA
pw=
Expected Results
Observed Results
0ns; TOA = 0ns +/- 25 ns; frequency of first

0.1us pw= 0.1us +/- 25 ns pattern = 801.75
PRi=1us
PRi=1us
power=0dbm
power=0
+/+/-
25
ns Mhz
1dBm pw=
97.875
ns
no of pulses in first no of pulses in first PRi=1us +/- 25 ns

pattern=
50 pattern=
50 power= - 2.36 dBm
frequency of second frequency

Time
of
second
of pattern = 900 MHz pattern = 900 +/- 1 MHz frequency
Arrival
TOA
30ns TOA = 30ns +/- 25 ns second pattern =
Pw=1us
PRI
Pw=1us
=
of
+/-
25
ns 900.00
power=0
pulses
+/-
Continuous
in no of pulses in second power=
Wave
Detection
FMOP=
PMOP= NILL
PMOP= NILL
750
MHz
dbm
type
:CW
length of data= 250us

freq=
800
pw=0.1
NILL FMOP=
PMOP= NILL
power= 7
+/- 1dBm
type
:CW
length of data= 250us

+/- 25 ns
MHz freq= 800 +/- 1 MHz

us pw=0.1 us +/- 25 ns
pri=1us
pri=1us
Amplitude
power=0dbm
power=0
Measureme
no of pulses =100 no
nt
TOA=0ns
of
+/-
25
ns
+/-
1dBm
pulses
=100
TOA=0ns +/- 25 ns
=
PMOP = NILL
NILL
freq= 750 +/- 1 MHz
Pulse
FMOP
-2.1875
10 dBM
FMOP=NILL
power=
ns
1dBm PRI = 9.9992 us
second pattern= 10 pattern=
freq=
MHz
10us PRI = 10us +/- 25 ns Pw=9992
power=0dbm
no
of
NILL FMOP
NILL
PMOP = NILL
freq= 801.75 MHz

pw=97
ns
pri=994
ns
power=
-2.375
Dbm
FMOP
NILL
PMOP = NILL
Table 3: Verification Test Cases
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VERIFICATION
OF
DIGITAL
RECEIVER
SYSTEM
ARCHITECTURE
Verification will be done at system level as well as at major module levels.

However, this document only details system level verification methodology and
is subjected to Customer Approval as part of Acceptance step.
Functional simulation as well as timing verification will be carried out for the
entire system.
After the successful completion of functional simulation, Timing simulations are

carried out. Timing simulation is done on the extracted net list produced after the
design is implemented. This is done so as to ensure that the design meets all the
timing parameters with respect to other devices on the board.
The timing characteristics of the hardware platform that will be used for hardware
validation and timing characteristics of the devices used on the hardware platform
are incorporated while doing timing simulation.
Verification will be automated that can be run in batch mode. Detailed test reports
will be generated for every test case that can be examined later.
Defect tracking tool Bugzilla will be used for Defect tracking during verification.
UNIT LEVEL TESTING

Unit Level testing is carried out at the following interface modules and the major
processing blocks:
1. ADC Interface Module
2. FFT Module
3. Peak Detector Module
4. SSRAM Interface Module
The purpose of unit level testing will be to functionally validate individual
modules exercising different corner conditions. In the following sections, the details of
test environment for unit testing, different test modules developed in order to facilitate
the testing, details of the test cases are given.
ADC Interface Module Unit Testing
This performs unit level testing of the ADC interface module.
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ADC behavioral module reads the data from a file and provides these values to
the ADC interface module. The test bench reads the output of ADC interface
module and compares it with data in the file. An error is generated if there is a
mismatch.
Test bench provides the ADC interface module with the values for register
programming of the ADC model through serial interface. The ADC model
shows the programmed values on transcript window, taking into consideration
timing-checks.
Processor Clock & Processor Reset
Clock & Reset

Generation Process
Sampling Clock
& Reset
ADC08D1500
Processor Interface
Process
System Clock
&
System Reset
sampled data
&
source synchronous clock
through LVDS interface
Q_DUMP
Data Analyser
Process
I_DUMP
I_FILE
Q_FILE
ADC serial programming

interface
ADC Interface Unit Test Test set-up

Fig 7: ADC Interface Module Unit Test Setup
1. Test bench includes Clock and Reset Generation process, which generates :
o Sampling clock of 1350 MHz for ADC model and corresponding reset.
o System clock of 168.75 MHz for ADC interface and corresponding
reset.
o Processor clock of 50 MHz for ADC interface and corresponding reset.
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2. Test bench includes Processor Interface Process, which generates :
o Start capture signal to enable the ADC interface module to capture the
ADC data.
o Signals required by ADC interface module for programming the ADC
model through serial interface.
3. Instantiates behavioral model of the ADC device.
4. Instantiates ADC interface module.
5. Test bench includes Data Analyzer process that compares the captured data with
data provided to ADC model, when enabled.
6. Provides input data files corresponding to two channels to ADC model.
7. Outputs from the ADC interface module are dumped onto two files
corresponding to two channels.
8. Includes inherent board connections between ADC model and ADC interface
module.
Test-bench includes the following processes of:
ADC Behavioral Model - ADC08D1500

o Mode Block module
o ADC Control Module
o ADC File Module
o DCLK Clock Generator Module
o Glue logic to output the data in differential format
Data Analyzer Process
Processor Interface Process
Clock & Reset Generation Process
Test Details
Name
tb_adc_interface.vhd
1) Program the registers of the ADC.
Test
Summary
2) Compares data received by the ADC interface module with data

provided to the ADC model
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1) After the de-assertion of resets, issue prog_adc=1 to start ADC
programming.
2) Wait for cal_run to go from high to low twice.
3) Program Configuration registers.
4) Program I channel offset register.
5) Program I channel full scale voltage adjust register.
Test
6) Program Q channel offset register.
Description
7) Program Q channel full scale voltage adjust register.

8) Program DES enable register.
9) Program DES coarse adjust register.
10) Program DES fine adjust register.
11) Issue start_capture = 1.
12) Read the data captured by the ADC interface module and
compare with data provided to ADC model.
Test
Functional
1) Calibration of ADC and Programming Write only registers of

ADC.
Coverage
2) Functionality of ADC interface module.
Test Duration
Program exits upon ADC finishing reading of the input file

1) Calibration: Test will issue a note in the transcript window if
power-on calibration of ADC is avoided.
2) Register programming: Messages are displayed on the transcript
Acceptance
Criterion
window after programming each of the registers. Structure of

the message is given below <register_name> Programmed
with the value : <register_value>.
3) Data capture: When a valid signal is issued then data is being
written onto the
files CHANNEL_I_CAPTURE.txt and
CHANNEL_Q_CAPTURE.txt.
Table 4: ADC Interface Test Details
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FFT Module Testing
This performs the Unit level testing for the functionality of the FFT module.
Numerical computation software is used to generate test vectors and also for
verifying the computed results from the FFT.
Numerical Computation Software
Channel 1
Imag Part
Channel 0
Real Part
fft_top_tb
18
18
Data Generator Process

i_valid_frame_t
36
i_sample_0_t ~ i_sample_7_t
o_sample_0_ch0
~ o_sample_3_ch0
36
o_valid_frame
fft_top
o_sample_0_ch1 ~
o_sample_3_ch1
36
Channel 1
FFT Result
Clock &
Reset
Generation
Channel 0
FFT Result
Write Results Process
Numerical Computation Software
Fig 8: FFT Module Unit Test Setup
Numerical computation software program is used to generate the desired signal

at sampling frequency. The sampled values are converted into fixed binary
format of 2.16. The results are dumped into two input files.
Test bench includes Clock and Reset Generation process, which generates the
system clock of 168.75 MHz for FFT modules operation.
Test bench instantiates the one FFT module.
Test bench includes a Data generation process for generating data and control
signals.
o It reads 8 time domain samples from each of the two input files and
supplies it to the FFT module. Data from channel-0 is given to FFT
module as real data (i_sample_#_t [35~18]), while data from channel-1
is given as imaginary data (i_sample_#_t [17~0]).
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o Each input frame consists of 256 samples; hence it takes 32 cycles to
feed one complete frame to the FFT module.
o Start of frame pulse is asserted along with the first data sample of the
frame.
o End of frame pulse is asserted along with the last data sample of the
frame.
o Data valid is asserted during the entire frame of data.
Output frame of FFT module consists of 128 samples and it outputs four
samples corresponding to each channel every clock. Thus it requires 32 clocks
to output one complete frame. Since the input consists of real data from each of
the channels, the result is symmetric.
The FFT module output is dumped into files by the Write Result Process. It
separates data from individual channels and into real and imaginary parts. The
fixed binary results are converted into real values while dumping.
Numerical computation software reads the values from the file. Finally the
magnitude and phase results corresponding to individual channels are plotted to
validate the results of the FFT module.
Test Details
Name
Test Summary
fft_top_tb.vhd
Generate test vectors for FFT module using Numerical
computation software.
Plot the results of FFT module using Numerical computation
software.
1) Matlab program fft_data_gen.m is executed. Chirp signals
Test
Description
corresponding to channels 0 and 1 are generated and dumped to

the files channel0_datain.dat and channel1_datain.dat.
2) Run the test bench.
3) The test bench reads the data from the files generated by
matlab program. The results of the FFT module are dumped to
files channel0_dataout.dat and channel1_dataout.dat.
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4) Matlab program fft_result_plot.m is executed. This program
reads the fft outputs from the files. The magnitude and phase
plots are shown in different windows for different channels.
5) Verify that magnitude peaks are observed between the chirp
sweep frequency signals only.
Test
All the sub modules of the FFT
Functional
Coverage
Test Duration
Simulation exits after at the end of simulation cycle on its own based
on assertion of severity in the test bench. In this case break on
assertion is set to Failure.
Acceptance
Two figure windows should appear on the screen corresponding to
Criterion
each of the channels.

Magnitude peaks displayed by the MATLAB should correspond to
the specified input chirp frequency range.
Table 5: FFT Module Test Details
Peak Detector Module Unit Testing

This performs the unit level testing of the peak detector module.
Test bench includes the clock and reset generation process, which generates the
system clock of 168.75 MHz for Peak detector modules operation.
Test bench includes one instantiation of one Peak detector module.
Test bench includes a Data generation process for generating data and control
signals. This module mimics the final output stage of the FFT processing
module.
o This feeds four samples at every clock to the Peak detector module.
o Each input frame consists of 128 samples; hence it takes 32 cycles to
feed one complete frame to the Peak detector module.
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o Start of frame pulse is asserted along with the first data sample of the
frame.
o End of frame pulse is asserted along with the last data sample of the
frame.
o Data valid is asserted during the entire frame of data.
Peak detector module generates pulse words as the outputs. Each word consists
of four parameters i.e. Centre frequency, start address, end address and time of
arrival values. Test bench includes a Data analyzer process for displaying the
pulse words generated by the Peak detector modules.
o This generates reads to Peak detector module only when the command
available (s_cmd_available_#) outputs are asserted.
peak_detector_tb_TC#
peak_detector
Clock and
reset
generation
s_end_frame
peak info buffers
detector word generator
peak dataout reader
s_sample_#
Data
36
generation
process s_start_frame
serializer memory
s_valid_frame
peak datain write
s_cmd_available_#
s_cmd_rd_valid_#
s_cmd_word_#
32
Data
analyzer
process
s_cmd_rd_enab_#
s_cmd_rd_done_#
Fig 9: Peak Detector Module Unit Test Setup

Test Details
Name
Test
Summary
peak_detector_tb_TC#.vhd
Formation of Pulse Command Words for different test cases, test
data being fed by individual test cases. Each of the test cases contain
different sequences of occurrences of peaks.
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Test
All the test cases associated with the Unit testing of Peak detector
Description
module are explained in Unit_Peak_Detector.
Peak detection taking side lobe into consideration.
Continuous wave detection.
Pulse word formation.
Test
Functional
Coverage
Simulation exits at the end of simulation cycle on its own based on

Test Duration assertion of severity in the test bench. In this case, break on
assertion is set to Failure.
Acceptance
Criterion
Centre frequency values of the four peaks are displayed on the

transcript window when analyzer generates reads to the Peak
detector module.
Table 6: Peak Detector Test Details
TOOLS USED
1. MATLAB for data generation and analysis.
2. ModelSIM for RTL simulation.
3. TextPad for RTL design changes.
MATLAB
MATLAB (matrix laboratory) is a multi-paradigm numerical computing
environment
and
fourth-generation
programming
language.
proprietary
programming language developed by MathWorks, MATLAB allows matrix

manipulations, plotting of functions and data, implementation of algorithms, creation
of user interfaces, and interfacing with programs written in other languages,
including C, C++, Java, Fortran and Python.
Although MATLAB is intended primarily for numerical computing, an optional
toolbox uses the MuPAD symbolic engine, allowing access to symbolic
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computing capabilities. An additional package, Simulink, adds graphical multi-domain
simulation and model-based design for dynamic and embedded systems.
In 2004, MATLAB had around one million users across industry and
academia.[3] MATLAB users come from various backgrounds of engineering, science,
and economics domains. It is now also used in education, in particular the teaching
of linear algebra, numerical analysis, and is popular amongst scientists involved
in image processing.[4]
Syntax
The MATLAB application is built around the MATLAB scripting language.
Common usage of the MATLAB application involves using the Command Window as
an interactive mathematical shell or executing text files containing MATLAB code.[7]
Variables
Variables are defined using the assignment operator, = . MATLAB is a weakly typed
programming language because types are implicitly converted.[8] It is an inferred typed
language because variables can be assigned without declaring their type, except if they
are to be treated as symbolic objects,[9] and that their type can change. Values can come
from constants, from computation involving values of other variables, or from the
output of a function.
MATLAB can call functions and subroutines written in the C programming language or
FORTRAN.[22] A wrapper function is created allowing MATLAB data types to be
passed and returned. The dynamically loadable object files created by compiling such
functions are termed "MEX-files" (for MATLAB executable).[23][24] Since 2014
increasing two-way interfacing with Python is being added.[25][26]
Libraries written in Perl, Java, ActiveX or .NET can be directly called from
MATLAB,[27][28] and many MATLAB libraries (for example XML or SQL support) are
implemented as wrappers around Java or ActiveX libraries. Calling MATLAB from
Java is more complicated, but can be done with a MATLAB toolbox[29] which is sold
separately by MathWorks, or using an undocumented mechanism called JMI (Java-toMATLAB Interface),[30][31] (which should not be confused with the unrelated Java
Metadata Interface that is also called JMI).
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As alternatives to the MuPAD based Symbolic Math Toolbox available from
MathWorks, MATLAB can be connected to Maple or Mathematica.[32][33] Libraries also
exist to import and export MathML.[34]
License
MATLAB is a proprietary product of MathWorks, so users are subject to vendor
lock-in.[3][35]Although MATLAB Builder products can deploy MATLAB functions as
library files which can be used with .NET[36] or Java[37] application building
environment, future development will still be tied to the MATLAB language.
Each toolbox is purchased separately. If an evaluation license is requested, the
MathWorks sales department requires detailed information about the project for which
MATLAB is to be evaluated. If granted (which it often is), the evaluation license is
valid for two to four weeks. A student version of MATLAB is available as is a homeuse license for MATLAB, SIMULINK, and a subset of Mathwork's Toolboxes at
substantially reduced prices.
It has been reported that EU competition regulators are investigating whether
MathWorks refused to sell licenses to a competitor.[38] The regulators dropped the
investigation after the complainant withdrew their accusation and no evidence of
wrongdoing was found.[39]
Version
Release name
Year
MATLAB 1.0
1984
MATLAB 2
1986
MATLAB 3
1987
Notes
Ran on MS-DOS but required at least

MATLAB 3.5
1990
386
processor.
Version
3.5m
required math coprocessor

MATLAB 4
1992
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Version
Release name
MATLAB 4.2c
Year
1994
MATLAB 5.0
Volume 8
MATLAB 5.1
Volume 9
1996
Notes
Ran on Windows 3.1. Required a math
coprocessor.
Unified releases across all platforms.
1997
MATLAB 5.1.1 R9.1
MATLAB 5.2
R10
1998
MATLAB 5.2.1 R10.1

MATLAB 5.3
R11
1999
MATLAB 5.3.1 R11.1
MATLAB 6.0
R12
2000
MATLAB 6.1
R12.1
2001
MATLAB 6.5
R13
2002
First release with bundled Java Virtual

Machine (JVM).
MATLAB 6.5.1 R13SP1

2003
MATLAB 6.5.2 R13SP2
MATLAB 7
Last
release
for
IBM/AIX,
Alpha/TRU64, and SGI/IRIX [42]
R14
2004
MATLAB 7.0.1 R14SP1

MATLAB 7.0.4 R14SP2
2005
Support for memory-mapped files.[43]
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Version
Release name
MATLAB 7.2
R2006a
Year
Notes
2006
MATLAB 7.3
R2006b
HDF5-based MAT-file support

New bsxfun function to apply element-
MATLAB 7.4
R2007a
by-element
binary operation
with
singleton expansion enabled.[44]

2007
MATLAB 7.5
Last
release
for
Windows
2000
andPowerPC Mac. License Server
R2007b
support for Windows Vista.[45] New

internal format for P-code.
Major enhancements to object-oriented
MATLAB 7.6
programming capabilities with a new
R2008a
class definition syntax,[46] and ability to

2008
MATLAB 7.7
manage namespaces with packages.[47]

New Map data structure.[48] Upgrades
R2008b
to random number generators.[49]

First release for 32-bit & 64-bit
MATLAB 7.8
R2009a
2009
Microsoft Windows 7. New external

interface
to
Microsoft
.NET
Framework.[50]
First release for Intel 64-bit Mac, and
MATLAB 7.9
R2009b
last for Solaris SPARC. New usage for

the tilde operator (~) to ignore
arguments in function calls.[51][52]
MATLAB 7.10
R2010a
Last release for Intel 32-bit Mac.
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Version
Release name
MATLAB 7.11
R2010b
Support for enumerations added.[53]
R2010bSP1
Bug fixes and updates.
R2010bSP2
Bug fixes.
MATLAB
7.11.1
MATLAB
7.11.2
MATLAB 7.12
R2011a
Year
Notes
New rng function to control random

2011
number generation.[55][56][57]
Access/change
parts
of
variables
directly in MAT-files, without loading

MATLAB 7.13
into memory.[58] Increased maximum
R2011b
local workers with Parallel Computing

Toolbox from 8 to 12.[59]
MATLAB 7.14
R2012a
2012
MATLAB 8
First
release
with
Tool
strip interface.[60] MATLAB Apps.[61]
R2012b
Redesigned documentation system.

MATLAB 8.1
New unit testing framework.[62]
R2013a
2013
MATLAB 8.2
New table data type.[64]
R2013b
Simplified compiler setup for building

MEX-files. USB Webcams support in
MATLAB 8.3
R2014a
2014
core MATLAB. Number of local

workers no longer limited to 12 with
Parallel Computing Toolbox.
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Version
Release name
Year
Notes
New
class-based
graphics
engine
(a.k.a. HG2).[66] Tabbing functionality

in
GUI.[67]Improved
user
toolbox
packaging and help files.[68] New

objects
for
date/time
manipulations.[69]Git/Subversion
integration
Data
IDE.[70]Big
in
capabilities
with
Reduce(scalable
MATLAB 8.4
Map
to
Hadoop).[71] New package for using
R2014b
Python from inside MATLAB, and a

new engine interface for calling
MATLAB from Python.[72][73] Several
new and improved functions: web
read(RESTful
web
JSON/XML
client(socket-based
services
support),
with
tcp
connections),hits
counts, histogram, animated line, and

others.
MATLAB 8.5
R2015a
2015
MATLAB 8.6
R2015b
Table 7: MATLAB History
MODELSIM
ModelSim is a multi-language HDL simulation environment by Mentor
Graphics,[1]
for
simulation
of
hardware
description
languages
such
as VHDL, Verilog and SystemC, and includes a built-in C debugger.[2][1]

ModelSim can be used independently, or in conjunction with Altera
Quartus or Xilinx ISE.[3] Simulation is performed using the graphical user
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interface (GUI), or automatically using scripts.
[4]
ModelSim is offered in multiple
editions, such as ModelSim PE, ModelSim SE, and ModelSim XE.[1][5]

ModelSim SE offers high-performance and advanced debugging capabilities,
while
ModelSim
PE
is
the
entry-level
simulator
for
hobbyists
and
students.[1] ModelSim SE is used in large multi-million gate designs, and is supported

on Microsoft Windows and Linux, in 32-bit and 64-bit architectures.[1]
ModelSim XE stands for Xilinx Edition, and is specially designed for
integration with Xilinx ISE.[5] ModelSim XE enables testing of HDL programs written
for Xilinx Virtex/Spartan series FPGA's without needed physical hardware.[5]
ModelSim can also be used with MATLAB/Simulink, using Link for
ModelSim.[6][7] Link for ModelSim is a fast bidirectional co-simulation interface
between Simulink and ModelSim.[7][6] For such designs, MATLAB provides a
numerical simulation toolset, while ModelSim provides tools to verify the hardware
implementation & timing characteristics of the design.[7]
Languages Support
ModelSim uses a unified kernel for simulation of all supported languages, and
the method of debugging embedded C code is the same as VHDL or Verilog.[1]
ModelSim enables simulation, verification and debugging for the following
languages:[1]
VHDL
Verilog
Verilog 2001
SystemVerilog
PSL
SystemC
TEXTPAD
TextPad is a text editor for the Microsoft Windows family of operating systems.
First released in 1992, this software is currently in its seventh major version. It is
produced by Helios Software Solutions.[1]
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Features
The ability to maintain block indents
Automatic code indentation (see indent style)
Regular expression based search and replace, including multiline regex
Macro recording feature to facilitate complex text transformations and data

processing.[3] Macro feature supports multiple regex searches (and
replacements) within a macro
Syntax highlighting (extendable to many different languages)[4]
Ability to call external programs (such as compilers)
Regex matching can be used to jump to a line number in a file given in the
output from external programs (e.g. to locate the cause of a compiler error)
Automatic integration with Java JDK, if JDK is already on the machine
Large file support[3]
Support for editing multiple files, with tabbed document selection[3]
Block select mode and Synchronized scrolling of multiple files
Clip libraries snippet management for reusable portions of text to insert into
documents
Clipboard history Allowing TextPad to function as a multiple clipboard tool
Bookmarking of lines, therefore allowing users to copy specific lines (e.g. log
file error messages), and then paste them to another document.
Multi-lingual support: User interface is available in seven languages with

spelling dictionaries available in ten languages.
Clip Library
The Clip Library is a TextPad sidebar that allows users to store small items
persistently, and then use them easily. This is done by double clicking clip names in the
Clip Library sidebar. In other editors such as Komodo, a clip library is known as
"snippets".
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TextPad comes with a number of pre-defined clip libraries, including ANSI
characters, HTML characters and HTML tags. A very useful clip library is
the Clipboard History. This is a list of previous Clipboard contents. So even though the
standard Windows Clipboard can only hold one piece of information, the TextPad
Clipboard History Clip Library can access a whole history of entries. See also clipboard
managers. You can create your own new clip libraries, and there are many clip libraries
available.[5]
Criticism
A lot of the criticism about TextPad is related to the practices of Helios Software
Solutions. After the release of TextPad 4.7.3 on June 4, 2004 the only statement that
was released from Helios Software Solutions was that "TextPad is still in development".
This had led many to believe TextPad was abandoned. Almost 3 years after the release
of TextPad 4.7.3, TextPad 5.0 was released on March 3, 2007. In the release
announcement it was stated that TextPad 5.0 is the "first of a planned series of upgrades
to TextPad this year." There have been regular updates since then.[7]
The release of TextPad 5.0, although a welcomed upgrade by many, received a
large amount of criticism. TextPad 5.0 was seen as "beta quality" by many
users,[8] needing further development before release. Only a month after the release of
TextPad 5.0, Helios Software Solutions released version 5.0.2 which either fixed issues
introduced in TextPad 5.0 or reintroduced features from version 4.7.3.[9][10] The release
of version 5.1.0 reintroduced other features from version 4.7.3 together with a German
user interface.[11]
Another criticism is that, as of version 7.1, TextPad is not Unicode-compatible,
even though it offers UTF-8 and UTF-16 as encodings in which files can be loaded and
saved.[12]Characters not available in your system code page are changed to question
marks. TextPad lacks a real-time spell checker option for those using the product for
editorial purposes.
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SIMULATION OF DIGITAL RECEIVER ARCHITECTURES
The digital receiver architectures are modeled in MATLAB. Additive white

Gaussian noise is used to simulate the noise. Sampling frequency is assumed to
be 1350 MHz. Pulse trains of 500 pulses with width 400 ns and PRI 1 are given
to the model and generated PDWs are analyzed. This is done to characterize the
parameter measurement over one complete FFT filter.
Pulses from minimum pulse width (PW) of 100 ns and PRI of 5 s are also
generated. Frequency is varied between 750 MHz to 1250 MHz. Pulse rise time
and fall time of the order of 25 ns was used while generating the pulses by
passing through appropriate FIR filter.
The parameter measurement accuracies simulation is carried out at around 10

dB SNR. Pulse density is computed for a 2 s PW. The simulation is set up to
handle four such overlapped pulses. Hence the input pulse density is 2 million
pulses per second (MPPS).
LIMITATIONS FOR VARIOUS PULSE PARAMETERS

PARAMETER
LIMITS
Number of test pulses that can be 1 to 4

generated in each channel
Power Level
-20 to 7 dBm
Type of signal
Pulse
Pulse Width
100ns to 200s
Frequency
750 to 1250 MHz
Type of Modulation
No Modulation
PRI
Greater than Pulse Width
Run-time
Greater than (PRI * no of repetition pulses )

Table 8: Limitations for Various Pulse Parameters
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MATLAB TEST CASE GENERATION
Fig 10: MATLAB Test Case Generation
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MATLAB TEST CASE PULSES OUTPUT
Fig 11: MATLAB Test Case Pulses Output

MATLAB TEST CASE FFT PLOT OUTPUT
Fig 12: MATLAB Test Case FFT Plot Output

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INFO
FILE
OF
GENERATED
TEST
CASES
WITH
ALL
PULSE
PARAMETERS
Fig 13: Info File of Generated Test Cases with All Pulse Parameters
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TEST CASE FILE
Fig 14: Test Case File

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MODELSIM OUTPUT
Fig 15: MODELSIM Output

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CHAPTER 4
REFLECTION ON MY INTERNSHIP
In this chapter I reflect on the internship. Regarding my learning goals I shortly
discuss my experiences; if I have achieved my goal, whether I experienced difficulties
and what I think I have to improve.
1) TECHNICAL OUTCOMES
I have learnt the MATLAB tool for generating test cases.
I have learnt the MODELSIM tool for simulation.
I have learnt the TEXTPAD tool for editing.
I have learnt coding in VERILOG and VHDL.
I have learnt TCL scripts.
I have learnt to execute the test cases individually and also automate the execution
of test cases.
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This is the MATLAB window where the inputs of various pulse parameters are given
and the test case file which is a digital one is obtained.
These are the test case pulses and FFT plot output waves generated by the MATLAB
tool.
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This is the info file generated by the MATLAB tool along with the test case file.
This is the example of test cases file generated.

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This is the output file which is generated by simulating the code using MODELSIM.
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2) NON-TECHNICAL OUTCOMES
The functioning and working conditions of a government organization

At the beginning I did not have any experience of working at an industry. Firstly
I understood the organization structure and also the industry environment. Then a
project was assigned to me. Trying to operate with the organization I saw the
importance of team work and personal capacity. The dependence on extern
institutions and people force you to have a flexible attitude. During my stay I also
experienced the dependence. There was often uncertainty whether and when
projects could start. In the first instance the dependence and uncertainty was
annoying, but it forced me to be flexible and to see what other things I could do.
Enhancing communication skills

More than I had expected I experienced language difficulties. I thought that I
could communicate well in English, however the majority of persons I worked with
talked in English. Therefore I was reserved in communication at the beginning, but
in the course of months it went better. My stay has contributed to my
communication skills, but I would like to pay more attention to it in the future. I
can come across as reserved and uncertain. To contribute more to projects and to
progress faster, I want to learn to make a more confident impression and to express
my ideas and opinions more certain.
The use of skills and knowledge gained in the university

It is difficult to say what skills and knowledge gained in my study I could put
in practice in my internship. I can think of the use of the experience from my thesis
for the necropsies. In the ecology courses that I have taken I learned about
ecological concepts and doing ecological research in general; I was taught some
basics on data collection, data processing and setting-up research projects. This is
reasonable and I have seen that within research projects you acquire the skills and
knowledge needed.
Skills and knowledge that might be improved to work in a professional

environment
Although you learn and develop the necessary skills and knowledge while
working in an organization, there are several things that I could improve already. I
did not have totally clear what activities I could have done to reach my learning
goals. Therefore during my stay I had some difficulties to determine tasks that I
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could carry out. In advance of my internship I talked with the organization about
the project in which I could participate, however clear agreements on my activities
were not made. A more assertive attitude from my side could have helped. To
prevent uncertainties in future projects I will pay more attention to making clear
agreements and back-up plans. Other aspects to which I want to pay attention in
general are: defining a clear research question and determine what data collection
and analysis is suitable. I often have the tendency to concentrate more on data
collection activities. Also in the internship I have seen that it is important to have
your research clear, because it guides you in the process. The participation in the
workshop made me enthusiastic. Before I had some doubts whether such
workshops could end in useful results, because there are many stakeholders each
with their own interests. However in this workshop all stakeholders were really
committed. It was interesting to hear the ideas and discussions between the
different stakeholders. These kinds of meetings are of importance, because they
contribute to a better understanding among the different parties. It permits that
information can be passed and topics can be discussed in more depth. It is also a
way to make each other enthusiastic and it stimulates to put things into action.
Through the workshop I learned about conservation and management, but I want
to learn more about it. Especially the regulation, protection and management by
policy and the way how human-animal conflicts could be mitigated are interesting
topics.
Organizing projects
Within the internship I did a lot of fieldwork. Because of this I have seen of
what aspects you have to think while organizing a project. Furthermore I have
learned how an education program can be set up and what things have to be taken
into account. It is important determine the knowledge present and to adjust the
program to each group. It is of importance to convey an objective and supported
message taking the viewpoints of people into account. I became also aware that
local people have a lot of knowledge that could help in research and conservation.
Before the internship I did not have any experience in environmental education and
I had no idea if it could work. In the future I would like to do some environmental
education, because I have seen now that people can be reached and that you can
receive a lot of new insights.
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The influence on future career plans

Before my internship, I had some doubts about my future career. I was not sure
if I would like to continue in research after finishing my M.Tech. I also did not
know what type of research I would like to do. Through this internship, I have seen
what elements of my career I like and I got enthusiastic again to continue in
research. I have found out that part of the research should contain fieldwork as I
did in the internship. I would like to continue in the research on river dolphins in
Bolivia. In this country, the research on dolphins is little so there are many
interesting aspects to study.
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REFERENCES
1. "India Strategic: Indian Defence News: Indias Defence Budget 2011-12".
Retrieved 2 July 2015.
2. "S Christopher appointed DRDO chief". The Times of India. Retrieved 2
July 2015.
3. "DRDO Scientist Job - DRDO Scientist B recruitment- Scientist recruitment
DRDO". Retrieved 2 July 2015.
4. John Pikes "Defence Research and Development Organisation (DRDO)".
Globalsecurity.org. Retrieved 31 August 2010.
5. "MoD Announces Major DRDO Restructuring Plan | Defence & Security News
at DefenceTalk". Defencetalk.com. 17 May 2010. Retrieved 31 August 2010.
6. "Defence Professionals". Retrieved 31 August 2010.
7. "Indian Army orders twelve Nishants" 12 February 2005. Retrieved 31
August 2010.
8. "Gallery of Dhruv, Nishant and armoured vehicles with detailed captions at"
Retrieved 31 August 2010.
9. "Modernization is a continuous process in OFB'". Retrieved 31 August 2010.
10. "DEFEXPO 2004 - Part 5" Retrieved 31 August 2010.
11. "Defense19". Retrieved 2 July 2015.
12. "Defence scientists plan artillery rockets with 100-km range". 18 September
2005. Retrieved 31 August 2010.
13. "Ordnance Factory Board". Retrieved 31 August 2010.
14. Ajai Shukla / Hyderabad 23 January 2008 (23 January 2008). "Missile mission
meets target". Business-standard.com. Retrieved 31 August 2010.
15. "Indian air force to induct indigenous SA missiles_English_Xinhua".
News.xinhuanet.com. 27 December 2007. Retrieved 31 August 2010.
16. "Missile boost for BEL". 3 February 2010. Retrieved 31 August2010.
17. "Army to upgrade OSA-AK system". 7 January 2006. Retrieved31
August 2010.
18. "Navy defends Barak deal". 5 April 2001. Retrieved 31 August 2010.
2015-16
Page 80

19. TNN, 18 October 2006, 02.39am IST (18 October 2006). "Trishul gets another
lease of life". Retrieved 31 August 2010.
20. "Maitri LLQRM". 20 March 2007. Retrieved 31 August 2010.
21. IANS (20 March 2003). "India seeks to boost military exports to Gulf".
SiliconIndia.com.
22. "The Hindu News Update Service". Chennai, India. 28 January 2008.
Retrieved31 August 2010.
23. "Israel Aerospace Industries Ltd". Retrieved 31 August 2010.
24. Rajat Pandit, TNN, 25 May 2010, 02.00am IST (25 May 2010). "India to gear
up for 'star wars' - India - The Times of India". Retrieved 31 August 2010.
25. "India Making Strides in Satellite Technology". Defence News. Retrieved 26
July 2012.
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Digital Receiver Verification

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Digital Receiver Verification

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Verification of Digital Receiver System Architecture

ABOUT THE ORGANIZATION

Verification of Digital Receiver System Architecture

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

and will feature canards and carry a range of

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

DRDO Imperial Eagle

Verification of Digital Receiver System Architecture

It is India's largest electronic warfare system. It is a land based EW project,

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

2) EW systems for the Air Force

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

A DIRCM (Directed Infra-Red Countermeasures) project to field a world class

Additional DRDO EW projects delivered to the Indian Air Force have

Combat vehicles & engineering

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

Various armour technologies and associated subsystems from composite

The Arjun follows a template similar to the tanks developed by western

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

Naval research and development

Verification of Digital Receiver System Architecture

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

ABOUT THE DEPARTMENT

It is India's largest electronic warfare system. It is a land based EW project,

2) EW systems for the Air Force

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

A DIRCM (Directed Infra-Red Countermeasures) project to field a world class

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

Additional DRDO EW projects delivered to the Indian Air Force have

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

BFSR-SR, a 2D short-range Battle Field Surveillance Radar, meant to be man

Super Vision-2000, an airborne 3D naval surveillance radar, meant for helicopters

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

3D Multi-Function Control Radar (MFCR) was developed as part of the Indian

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

Multi-mode radar, a 3D radar is a HAL project with DRDO's LRDE as a subsystem

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

DRDO has indigenised components and improved subsystems of various other

Verification of Digital Receiver System Architecture

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture

Search or Target Acquisition

PW stable / variable, Intra-Pulse Modulation characteristics (e.g. Barker Code, Chirp),

VLSI Design & Embedded Systems, Dept. of ECE

Verification of Digital Receiver System Architecture