Outline
Introduction
Linear model
Charge Pump PLL
Performance Metrics
Design Methodology
What is a PLL?
From a communications point of view, a phase-locked
loop is an optimum phase estimator
For an input r(t)=Asin(t + ), the PLL provides an
estimate Asin(t + ML)
Where is it used?
Frequency Synthesis
Reference frequency for modulation and
demodulation
Clock reference
Radio, Television
Clock Recovery
Serial interfaces (Computers, optical networks)
FM demodulation
Radio
in
Phase
Detector
Loop
Filter
f
VCO
out
Phase
Detector
Loop
Filter
Frequency
Divider
fout
VCO
f out = N f in
N Integer
->
N Fractional ->
Linear Model
A PLL depends on nonlinear
operations to work properly
in
div
Kpd(in-div)
+
Kpd
G(s)
KVCO
s
fVCO (t ) = KVCOVctrl (t )
Integrating both sides
t
1
N
VPFD = K PD
GVCO ( s ) =
VCO ( s ) KVCO
=
Vctrl ( s )
s
= in div
G (s )
H out ( s ) =
out ( s )
K PD KVCO G ( s )
=N
in ( s )
Ns + K PD KVCO G ( s )
H ( s ) =
out ( s )
K VCO G ( s )
=N
( s )
Ns + K PD K VCO G ( s )
Hold Range: the frequency range over which the PLL is able to statically maintain phase
tracking: H = KPDKVCOG(0).
Lock Range: the frequency range within which the PLL locks within one single-beat note
between the reference frequency and output frequency: L KPDKVCOG().
The Pull-In and Pull-Out Range: The pull-in range, P, is defined as the frequency range
in which the PLL will always become locked. The pull-out range, PO, is defined as the
limit of dynamic stability for the PLL. No simple relationships for these.
Type I PLL
For a Type-I PLL with different Loop Filters G(s) we have the following responses
H out1 ( s ) =
G ( s ) = G1 ( s ) = 1
K PD KVCO
out ( s )
=N
in ( s )
Ns + K PD KVCO
n =
G ( s) = G2 ( s) =
G ( s ) = G3 ( s ) =
1
s + 1
s 2 + 1
s ( 1 + 2 ) + 1
R1
Vin
Vout
R2
H out 2 ( s ) =
K PD KVCO /
s + s / + K PD KVCO / N
2
2n s + n2
H out 3 ( s ) = 2
s + 2n s + n2
K PD KVCO
N
1
N
2 K PD KVCO
n =
K PD K VCO
N ( 1 + 2 )
1
2
K PD K VCO
N
+ 2 +
N ( 1 + 2 )
K PD K VCO
1=R1C1
2=R2C1
C1
Type I PLL
Magnitude (dB)
10
0
|Hout3(s)|
-10
|Hout1(s)|
-20
|Hout2(s)|
-30
-40
-2
10
10
-1
0
10
Phase (Degree)
0
Hout3(s)
-50
-100
Hout1(s)
-150
Hout2(s)
-200
-2
10
-1
10
Frequency [Hz]
0
10
10
Loop Filter
UP
fin
PFD
Iin
Vvco
DWN
fout
VCO
R1
fdiv
Advantages:
Increased locking range
Speed up in capture process
Phase Frequency Detector (PFD)
Charge Pump (CP) combination
creates extra pole at zero
frequency
This pole provides infinite gain at
DC, which results in zero phase
error in ideal locked state
C2
C1
Charge Pump
1
N
Note: This PLL is also known as Digital PLL since the phase comparison and
frequency division are performed digitally
Disadvantages:
Sampled operation introduces
spurious tones at the VCO output
Loop bandwidth limited by stability
considerations
11
Phase-Frequency Detector
VDD
"1"
D
In
UP
CLR
Out
DWN
CLR
Div
"1" D
Conceptual PFD-CP
fREF
UP
DWN
fDIV
12
up=0
dn=0
ref
ref
div
up=0
dn=1
div
up=1
dn=0
ref
div
-1
-0.1
-0.05
0
Phase error (2rad)
0.05
0.1
UP
DWN
ton
tref
14
Charge Pump
VDD
"1" D
In
Icp
Q
UP
S1
CLR
DWN
CLR
S2
C1
Div
"1" D
Vout
Icp
UP
DWN
Icp
Total
CP
current
Vout
t
Charge Pump
Calculating the Detector Gain:
The time the UP/DWN signals are
asserted is:
t up =
T
2
I pd = I cp
2
T
Which gives an overall phase
detector gain Kpd of:
I cp
K pd =
2
16
Current mismatch
Mismatch between source and sink
currents in the charge pump introduces
a finite phase error.
Current leakage
When the source/sink currents are off,
leakage currents can flow and modify
the VCO control voltage of the VCO by
charging/discharging the loop filter.
Spurs are introduced.
Charge sharing
Parasitic capacitances from the switches
share charge with the loop filter when
the nodes they are connected to have a
large change in their voltage.
icp
ileak
ton
Charge injection
Occurs when switches are turned off
and the charge in their channels is
injected/extracted to the loop filter.
Spurs are introduced
17
V
in
R1
C2
C1
z =
p2 =
vco
R1
1
R1C1
1
C1 C 2
1
R1C 2
C1 + C 2
18
Loop Filter
140
130
120
|Z(s)| [dBohm]
V
1 + sR1C1
Z ( s) = VCO = R1
I in
s[R1C1 R1C2 s + R1 (C1 + C2 )]
110
100
90
80
70
K K Z ( s)
H ol ( s) = div = PD VCO
in
N
=
KVCO I cp
2N
R1
60
50
2
10
1 + sR1C1
s[R1C1 R1C2 s + R1 (C1 + C2 )]
c = z p 2 = z
C1
+1
C2
3
10
4
5
10
10
Frequency [Hz]
7
10
6
10
c
1 c
m = tan tan
z
p2
1
19
p2
1
m = tan
z
tan 1 z
p2
C1
1
1
m = tan
+ 1 tan 1
C
C
2
1
+
1
C
z =
1+
C1
C2
p 2 = c 1 +
C1
C2
c =
I cp K vco
N
I cp K vco R1
C1
R1
C1 + C2
N
20
Magnitude
[dB]
50
z
p2
-50
10
10
10
10
10
-100
PLL.
PM
-120
Phase Degree
-100
2
10
-140
-160
-180
2
10
10
10
f
(Hz)
10
10
10
Performance Metrics
The design of frequency synthesizers for RF
systems involves complying to a large set of
specifications, such as:
22
Tuning range
(GHz)
Frequency Resolution
Frequency Accuracy
Bluetooth
2.400 2.479
1 MHz
75 kHz
IEEE 802.11a
5.150 5.350
5.750 5.850
20 MHz
60 kHz
IEEE 802.11b
2.400 2.479
5 MHz
60 kHz
IEEE 802.11g
2.400 2.479
20 MHz
60 kHz
DCS1800
1.710 1.785
1.805 1.880
200 kHz
5 kHz
Phase Noise
Phase noise is a measure of the spectral purity of a signal and is one of the
most important parameters for characterization of the synthesizer
Phase noise degrades the quality of the data in a communication system
Assume the PLL output is a sinusoidal tone at
Power
0
carrier
dBc/Hz
0m
()
0+m
The oscillator output voltage power spectral density (PSD) is related to the
phase noise PSD
A2
SV ( ) =
2
1
1
)
+
(
)
+
(
)
0
2
2
S ( ) =
m2
2
( m )
S (m )
SV (0 + m )
{} = 10 log
10
log
=
[dBc]
2
2
2
The units dBc/Hz refer to the ratio between the noise and the carrier
in dB in a bandwidth of 1 Hz.
26
27
Syn. Output
Desired
Channel
Unwanted Channels
fRF
Desired Tone
Spurious tone
Phase Noise
fLO
Receiver Output
Received Signal
Noise
Desired signal
fIF = fRF - fLO
28
{}(dBc/Hz) < Psig _ min (dBm) Pblk _ max (dBm) f BW (dBHz) SNR (dB)
29
A margin has to be added to the obtained value since there are more
contributions to the degradation of the signal to noise ratio (SNR), generally
this margin is related to the overall noise figure of the system and can be as
large as 4dB
30
-n
Spurious Signals
The periodic phase variation at the output of the oscillator
generates spurious tones (also named spurs)
Spurs are generated due to the sampled nature of the
charge-pump PLL.
The spur specification is calculated in a similar fashion as the phase noise,
but now the noise is concentrated in a single frequency, instead of being
smeared in the channel bandwidth.
spur ( )(dBc) < Psig _ min (dBm ) Pblk _ max (dBm ) SNR (dB)
For Bluetooth the carrier-to-interferer ratio at a 2MHz offset
is 30dB, the SNR is 16dB and the spur results in:
m
2
The previous equation also shows that the amplitude of the spurious signals
Asp is related to the amplitude of the carrier signal A and to the peak phase
deviation m by
Asp = A
m
2
m = K vco Am cos(ref )d
0
=
max
K vco Am
ref
Asp
m
20
log
=
A
2
dBc
K A
= 20 log vco m
2
ref
Am =
2 ref
K vco
10
Asp
A dBc
20
34
There are two main effects which can generate reference spurious:
1. Leakage current in loop filter and charge-pump
If the charge-pump current Iout is considered as a periodic pulse train, the Fourier
series representation is
Am = 2 I leak Z ( jref )
A = 20 log
2f ref
dBc
A = 20 log
4f ref
dBc
The previous results are very important, since they allow the designer
to estimate the spurious tone magnitude during the initial design of
the charge-pump and without the need of close loop simulations
36
VCO(s)
VLF(s)
IN(s)
OUT(s)
Kpd
Z(s)
Kvco/s
1/N
DIV(s)
N K pd K vco Z (s )
( s)
H LP ( s ) = OUT
=
IN ( s) N s + K pd K vco Z (s )
H VCO ( s ) =
H LF ( s ) =
OUT ( s)
N s
=
VCO ( s) N s + K pd K vco Z (s )
OUT ( s)
VLF ( s )
N K vco
N s + K pd K vco Z (s )
37
VCO highpass
REF lowpass
38
Settling time
DEFINITION: The time required for the
PLL to change its output frequency from
fout(0) to fout() within a frequency error
smaller or equal to
f out (t ) f out ()
The closed loop transfer
function is:
N
f out = ( N + N ) f ref = N 1 +
f ref
N
Iin
R1
G ( s) = K f
1 + s
s
Vout
N (2 n s + n2 )
H (s) = 2
s + 2 n s + n2
C1
39
K pd K f K vco
n =
K pd K f K vco
N
sin (m )
=
2 cos(m )
= c cos(m )
f out ( s ) = Nf ref
Nf ref
N s
H ( s)
(2 s + )
n
2
n
Nf ref
= lim s0 s
H ( s ) = Nf ref
N
s
tlock = L1
H ( s ) f out () <
N s
s ( s 2 + 2 n s + n2 )
40
0 < <1
=1
>1
Underdamped
Critically Damped
Overdamped
Decomposing the
transfer function of
fout(s) in partial
fractions we obtain
the general form
n j 1 2
= n
n j n 2 1
1, 2
Nf ref 1
Nf ref 2
2
j2 1 2 n
Nf ref + j 2 1 n
+
s
s 1
s 2
(
)
n
n
Nf ref 1
Nf ref 2
2
Nf ref
j 2 1 n
j 2 2 1 n
+
+
s 1
s 2
s
<1
=1
>1
<1
=0
>1
41
e 1t e 2t
2
Nf ref 1 + 1
j 2 1 2 n
f out (t ) = Nf ref 1 - e nt (1 n t )
e 1t + e 2t
1
2
Nf ref 1 +
2 2 1 n
<1
=0
>1
Substituting in the equation for tlock (page40), the frequency error becomes:
2
1
e nt
2
1
Nf ref
sin n 1 t tan
2
= Nf ref e nt (1 n t )
-
nt
2
2
cosh( n 1t ) +
sinh ( n 1t )
Nf ref e
2 1
<1
=0
>1
42
tlock
Nf
ref
ln
2
1
= Solved numerically
Nf ref 2 1 +
1
ln
2
2
1
2
1
<1
=0
>1
43
Nf r
45
Normalized lock-time n
40
35
E=
Nfr
E=105
30
E=104
25
20
E=103
15
E=102
10
5
0.4
0.6
0.8
1
1.2
1.4
Damping Factor
1.6
1.8
44
Design Procedure
45
Charge Pump
Vdd
UP
35 A
VbiasP
Iout
VbiasN
Vdd
DWN
Loop Filter
Icp
+
R1
Vo
C2
C1
Trade offs
Settling Time
Close-in Phase Noise
Total Capacitance (area)
Charge Pump Current
Phase Noise Contribution of
R1
47
Vc
Trade offs
Ib
Vb
Phase Noise
Tuning Range
Power Consumption
48
Programmable Divider
Program
Counter
Prescaler
fIN
fOUT
%(N+1)/N
%P
%S
Reset
Swallow
Counter
Channel
Selection
( N + 1) S + ( P S ) N
f out = ( NP + S ) f in
P>S
49
Prescaler
50
Synchronous Prescaler
fin
3/4
MCi
fout
MC
MCi
SET
CLR
Q
Q
SET
Vout
CLR
Q
Q
CLK
51
Q
Q
A
CLK
Vb
CLK
CLK
CLK
Vbias
Mux
LO Port
f in /2
fin
/
2
5
GHz
I
Q
I
Q
2
/
2
2.5
GHz
Modulus
Control
Phase
Selection
fin /4
I /
I 2
Q
Q /
2
1.25
GHz
I
Q
I
Q
p0
p2
p4
p6
I
Q
I
Q
p1
p3
p5
p7
f in /8
625
MHz
Phase
Selection
fout
Modulus
Control
Modulus
Control
Phase
Selection
Mux
fin /4
I
Q
I
Q
p0
p2
p4
p6
I
Q
I
Q
p1
p3
p5
p7
2
/
2
1.25
GHz
f in /8
625
MHz
Phase
Selection
Modulus
Control
p5
p6
p7
1 2 3 4 1 2 3 4
Mux
1 2 3
fout
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8
fout
54
Implementation: High
Frequency
D Flip-flop in bipolar
technology
I
Q
I
Q
CLK
Q
Vdd
R
Q
Q
CLK
CLK
Vbias
Ibias
55
a)
New Architectures
Linearization techniques (spur reduction)
Digital PLL
Fast Settling
New and improved VCO
Reduced power frequency dividers
Low voltage low power PLLs
56
VDD
Loop Filter
BW2
Loop Filter
BW1
UP
fref1
100MHz
PFD
LPF
DWN
UP
fout
LPF
VCO1
DWN
fref2
PFD
800kHz
VCO2
Charge Pump
Charge Pump
1
X
1
N
SSB
Mixer
N=16
1
N
X=4
Channel
Selection
T. Kan and H. C. Luong, A 2-V 1.8-GHz Fully Integrated CMOS Frequency Synthesizer for DCS-1800 Wireless Systems, VLSI Circuits, pp: 234 - 237, 2000.
VDD
VDD
Loop Filter
BW1
UP
fref1
1.6MHz
PFD
LPF
DWN
VCO1
Charge Pump
Loop Filter
BW2
UP
DWN
fout
LPF
VCO2
Charge Pump
1
N
Channel
Selection
1
N
fref2 = 205MHz
57
W. Yan and H. C. Luong, A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers, IEEE JSSC, vol. 36, pp: 204-216, February 2001.
VDD
Loop Filter
BW1
Loop Filter
BW2
UP
fref1
PFD
DWN
UP
LPF
PFD
fout
LPF
DWN
IF
VCO
RF
VCO
Charge Pump
A.N. Hafez and M.I. Elmasry, A FullyIntegrated Low Phase-Noise NestedLoop PLL for Frequency Synthesis,
CICC, pp: 589 592, 2000.
Charge Pump
1
N1
1
N2
Channel
Selection
fref
Ip1
Vcont
UP
PFD
DWN
Ip2
T. C. Lee and B. Razavi, A Stabilization Technique
for Phase-Locked Frequency Synthesizers, VLSI
Symposium, pp: 39 - 42, 2001
fout
CP1
C1
VCO
CP1
1
N
58