INTEGRATED CIRCUITS
AND SYSTEMS
Kenneth R. Laker
University of
Pennsylvania
Willy M. C. Sansen
Katholieke Universiteit
Leuven
Belgium
McGraw-Hill, Inc.
New York St. Louis San Francisco Auckland Bogota Caracas
Lisbon London Madrid Mexico City Milan Montreal
New Delhi San Juan Singapore Sydney Tokyo Toronto
Preface
MOS Transistor Models
Introduction
1-1
MOSFET and Junction FET
1-1-1 JFET
1-1-2 MOST
1-1-3 MOST and pMOST
1-2
Capacitances and MOST Threshold Voltages
1-2-1 MOS Capacitance
1-2-2 Junction Capacitance
1-2-3 MOST and JFET
1-2-4 MOST Threshold Voltage
1-2-5 Enhancement and Depletion MOST
1-3
MOST Linear Region and Saturation Region
1-3-1 Large VGS, Small t>os, and Zero VBS
1-3-2 Large VGS, Large VDS, and Zero VBS
1-3-3 Large VGS, Small VDS, and Large VBS
1-4
MOST Current-Voltage Characteristics
1-4-1 Linear Region
1-4-2 Linear Region: First-Order Model
1-4-3 MOST in Saturation: First-Order Model
1-4-4 Parameters K' and n
1-4-5 Plots of ios versus VGS and VBS
1-4-6 Effective Channel Length and Width
1-5
Small-Signal Model in Saturation
1-5-1 Transconductance gm
1-6
1-7
1-8
1-9
1-10
1-11
1-12
CONTENTS
26
26
27
27
29
30
32
32
32
33
35
36
38
41
43
45
45
47
47
49
49
50
50
51
52
52
53
55
56
57
58
58
60
62
62
65
66
67
69
69
71
71
73
74
74
77
78
79
CONTENTS
2-2
2-3
2-4
2-5
2-6
XI
81
81
83
84
85
86
86
86
90
91
92
92
92
96
96
96
100
101
102
102
102
103
106
106
106
107
110
110
112
112
116
117
121
121
121
121
125
126
126
127
130
131
131
131
132
132
134
134
XII
CONTENTS
137
139
139
139
142
142
143
144
145
146
146
147
147
147
149
150
151
151
152
153
153
153
155
156
157
157
159
160
160
160
161
162
162
164
169
170
Introduction
3-1
Feedback Theory
3-1-1 Basic Feedback Concepts and Definitions
3-1-2 Feedback Configurations and Classifications
3-2
Analysis of Feedback Amplifier Circuits
3-2-1 Analysis When the Feedback Network is One of the Four Basic
Configurations in Fig. 3-7
3-2-2 Blackman's Impedance Relation
3-2-3 The Asymptotic Gain Relation
3-3
Stability Considerations in Linear Feedback Systems
3-3-1 Effect of Feedback on the System Natural Frequencies
3-3-2 The Use of Bode Plots in Stability Analysis
170
172
177
185
188
189
194
198
200
202
212
3-4
CONTENTS
Xi
219
221
222
226
231
232
238
241
244
245
245
247
247
249
252
261
269
276
277
277
280
281
283
288
291
292
300
307
308
308
313
314
316
316
324
326
329
332
334
337
341
343
343
345
346
352
353
XIV
4-7
4-8
CONTENTS
354
355
357
357
359
372
378
378
379
381
383
387
391
393
401
407
408
Introduction
5-1
The Op Amp Schematic Symbol and Ideal Model
5-2
Analysis of Circuits Involving Op Amps
5-2-1 Inverting Configuration
5-2-2 Noninverting Configuration
5-3
Practical Op Amp Characteristics and Model
5-3-1 Gain-Bandwidth and Compensation
5-3-2 Step Response and Settling
5-3-3 Slew Rate and Fll Power Bandwidth
5-3-4 DC Offsets and DC Bias Currents
5-3-5 Common Mode Signals
5-3-6 Noise
5-4
Differential and Balanced Configurations
5-5
The Operational Transconductance Amplifier (OTA)
5-5-1 Ideal Model
5-5-2 OTA Building Block Circuits
5-5-3 Practical Considerations
Summary
Exercises
References
408
410
414
414
425
434
434
442
444
448
452
453
456
462
463
464
465
467
467
474
475
Introduction
6-1
Design of a Simple CMOS OTA
6-1-1 Gain of the Simple CMOS OTA
6-1-2 The GBW and Phase-Margin
6-1-3 Design Plan
6-1-4 Optimization for Maximum GBW
6-2
The Miller CMOS OTA
475
477
478
479
482
482
CONTENTS
XV
486
489
491
497
500
500
502
503
504
505
507
510
511
513
515
519
522
523
524
527
532
535
535
537
539
540
543
544
546
546
548
548
552
556
556
558
562
563
567
569
572
575
575
583
585
587
591
XVI
6-8
6-9
CONTENTS
Design Options
6-8-1 Design for Optimum GBW or SR
6-8-2 Compensation of Positive Zero
6-8-3 Fully Differential or Balanced OTAs
Op Amp Examples
6-9-1 CMOS op Amp Configurations
6-9-2 Bipolar Op Amp Configurations
6-9-3 BIMOS and BIFET Op Amp Configurations
Summary
Exercises
Appendix 6-1: Pole-Zero Doublets and Settling Time
Appendix 6-2: Amplifier Configurations
References
595
595
598
601
607
607
608
610
612
612
622
628
646
648
648
649
652
652
657
666
668
670
671
672
672
675
678
679
681
684
685
686
687
688
690
696
703
704
708
713
718
723
724
732
756
CONTENTS
XV
758
Introduction
8-1
Parasitic Capacitances in Integrated Filters
8-2
Design of Practical Integrated Filter Components
8-2-1 Poly 1-Poly 2 Capacitor
8-2-2 MOST Analog Switch
8-2-3 Linearized MOST Resistor
8-2-4 Linearized OTA Transconductance
8-3
Parasitics and Filter Precision
8-3-1 Reducing the Effect of Parasitics on Filter Precision
8-3-2 Parasitic Insensitive Switched-Capacitor Structures
8-4
Automatic On-Chip Tuning
8-4-1 On-Chip Tuning Strategies
8-4-2 Frequency Tuning with PLL .
8-4-3 Q tuning with MLL
8-5
PSRR, Clock Feedthrough and DC Offset
8-5-1 Clock Feedthrough and DC Offset Cancellation
8-5-2 Layout Measures to Improve PSRR
8-5-3 Balanced Active-RC and SC Design
8-6
First-Order and Biquadratic Filter Stage Realizations
8-6-1 Realizing Real Poles and Zeros
8-6-2 Types of Biquads
8-7
Fleischer-Laker Active-SC Biquads
8-7-1 Evaluation of the General Active-SC Biquad
8-7-2 Synthesis of Practical Active-SC Biquads
8-7-3 Examples
8-8
Integrated Continuous-Time Fleischer-Laker Type Biquads
8-8-1 Active-RC Biquads using MOST-'s
8-8-2 Active-G m /C Biquads using MOST-G m 's
8-9
High-Order Filter Implementation Using Cascaded Stages
8-9-1 Cascading First- and Second-Order Filter Stages
8-9-2 Time-Staggered Active-SC Stages
8-9-3 Settling Error Analysis of Delay Equalizers Realized as a Cascade
of Active-SC AP Stages
8-10 High-Order Filter Implementation Using Active Ladders
8-10-1 Sensitivity
8-10-2 Realization Using Signal Flow Graphs
h
8-10-3 Realizing All-Pole LP Filters
" .
8-10-4 Realizing Symmetrie All-Pole BP Filters
8-10-5 Realizing Finite Transmission Zeros
Summary
Exercises
References
758
761
764
764
765
767
772
777
778
782
786
787
794
796
798
799
803
808
808
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815
822
826
830
837
843
843
847
849
849
852
856
858
860
862
865
870
872
874
876
885
Index
889