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14:332:437 Digital Systems Design (DSD)

Fall 2015
Department of Electrical and Computer Engineering
Rutgers University
September 3, 2015
Class Times: Thursday 6:40 9.40 pm
Class Room: WL-AUD, Busch Campus
Lab Times: M-W-F 1.40 3.00 pm, Friday 6.40 8.00 pm
Labs: EE-105, Busch Campus
Course Web Site: http://sakai.rutgers.edu
Instructor: Dr.Nagi Naganathan (Adjunct Faculty, Department of ECE)
e-mail: nagi@computer.org
Lab Instructor:Swapnil Mhaske
e-mail:smhaske@scarletmail.rutgers.edu
Teaching Assistant:Moliang Zhou
e-mail:mz330@scarletmail.rutgers.edu

Overall Educational Objective:


The goal of this course is to develop a comprehensive understanding of the underlying technologies
and design techniques used to build a digital system. The aim of the course is to provide a practical
view of whats under the hood of a computer.
The course builds on Digital Logic Design and will introduce logic design using hardware description
language such as SystemVerilog. The course will cover the SystemVerilog language in depth and will
explain on how to build complex combinational and sequential circuits.
The course will introduce the basics of RISC microprocessor. Itll then go in depth of the first RISC
microprocessor MIPS in depth. Will introduce the MIPS architecture, assembly language and
microarchitecture.
The course will also introduce ARM architecture for the first time in this course as over the past two
decades, the ARM architecture has become very popular. More than 50 billion ARM processors have
been shipped and nearly every cell phone and tablet has one or more ARM processors. Also more ARM
processors are used in implementing Internet of Things (IoT). So its vital to give exposure to ARM
processors.

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The course will present a systematic approach to digital implementation in the labs using
SystemVerilog using Altera FPGA boards. This will provide a valuable skill required for FPGA design
along with embedded software.

Labs:
The course is supported with the labs and Altera FPGA board will be used and students will be building several
circuits using SystemVerilog.

Course Learning Outcomes:


A student who successfully fulfills the course requirements will have demonstrated:

Digital Logic/System Design


Understand digital logic - Combinational and Sequential circuits
Apply the principles of abstraction, modularity, hierarchy and regularity in digital design
Design complex state machines thats present in all computers
Hardware Description Language
Design Digital Logic using SystemVerilog
Design high speed arithmetic circuits using FPGA
Use of CAD Tools
Simulation
Computer Architecture
Understand whats under the hood of a computer
Understand RISC Architecture
Develop a good understanding of MIPS and ARM Architectures

Pre-requisites:
1.
2.
3.

14:332:231 Digital Logic Design


14:332:233 Digital Logic Design Labs
14:332:252 Programming Methodology I

Pre-requisite by Topics:
1.
2.
3.
4.

Boolean algebra
General Computer Skills
K-Map minimization
Combinational, Sequential Circuits

Course Text Book:


1.

David Harris & Sarah Harris, Digital Design and Computer Architecture, 2nd Edition, Morgan Kaufman
Publishers, ISBN 978-0-12-394424-5

Supplemental Text Books: (No Need to buy this book)


1.

Sarah Harris & David Harris, Digital Design and Computer Architecture, ARM Edition, Morgan Kaufman
Publishers, ISBN 978-0-12-800056-4

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Reference Text Books:


1. Donald Thomas, Logic Design and Verification Using SystemVerilog, ISBN - 978-1500385781
2. J.Bhasker, A SystemVerilog Primer, Star Galaxy Publishing, ISBN 978-0-9650391-1-6
3. David Patterson, John Hennessy, Computer Organization and Design, The Hardware/Software Interface,
Morgan Kaufmann Publishers, ISBN- 978-0-12-407726-3

Course Material:
Slides from the Text books, my slides, additional slides from various sources such as web sites etc.,
intended only for academic use

Grading:
Home Works
Labs
Mid Term 1
Mid Term 2
Final Exam (Cumulative)

15%
30%
15%
15%
25%

Total

100%

Policies (Digital Systems Design):


Attendance and Participation: Students are expected to attend every lecture and lab sessions.
Home Work: Home Works (Class and Lab) are expected to be turned on time. Late homework will not be
accepted at any circumstances.
Exams: Exams are closed books and notes. Two midterms and a final examination will be given. The final will be
cumulative. Makeup exams will not be given except in the case of documented medical emergency.
Academic Integrity: Academic integrity is essential to the success of the educational enterprise and breaches of
academic integrity constitute serious offenses against the academic community. Students are responsible for
understanding the principles of academic integrity fully and abiding by them in all their work at the University.
http://academicintegrity.rutgers.edu/academic-integrity-at-rutgers 2008, Rutgers, The State University of New
Jersey, All rights reserved. Policy on academic integrity can be found at
http://academicintegrity.rutgers.edu/files/documents/AI_Policy_9_01_2011.pdf

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Tentative Schedule (Updated September 3, 2015)


1.
2.
3.
1.
2.
1.
2.
3.
4.
1.

1.

2.

Topic
Organizational issues. Information revolution. Basic hardware
concepts.
Number systems, Binary addition, subtraction, Representation of
negative numbers, 2s complement addition/subtraction.
Logic Signals and Gates
Switching algebra, Theorems, Standard representation of logic
functions
Combinational circuits, Truth table, Karnaugh maps, Minimization
techniques
Latches and Flip-Flops
Synchronous Logic Design
Finite State Machine (FSM)
Timing
Hardware Description Language SystemVerilog

Digital Building Blocks (Arithmetic Circuits)


a. Adder
b. Subtracter
c. Comparator
d. Multiplier
e. Counters, Shift Registers
Review

Book Chapters
Chapter 1 (From Zero to One)
Chapter 2 (Combinational Logic
Design)
Slides - Lectures #1, #2, #3

Dates
9/3/2015

Chapter 2 (Combinational Logic


Design)

9/10/2015

Slides - Lectures #3, #4


Chapter 3 (Sequential Logic Design

9/17/2015

Slides - Lecture #5
Chapter 4 (Hardware Description
Language)
Slides - Lecture #6
Chapter 5 (Digital Building Block)

9/24/2015

10/1/2015

Slides Lectures #7, #8

Mid Term 1 10/8/2015


1. RISC Architecture MIPS
2. Assembly Language
3. Programming
1. RISC Architecture ARM
2. Assembly Language
3. Programming
MIPS Microarchitecture
ARM Microarchitecture

1.
2.

Review
Memory and I/O Subsystesms

ARM Caches

Review

Chapter 6 ( Architecture)
Slides Lecture #9)

10/15/2015

Chapter 6 (Supplemental Book


Architecture)
(Slides Lecture #10)
Chapter 7 (Microarchitecture)
(Slides - Lecture #11)
Chapter 7 (Supplemental Book
Microarchitecture)
Slides Lecture #12
Chapter 8 ( Memory & I/O SubSystems)
Slides Lectures #13, #14

10/22/2015

Mid Term 2 11/19/2015


Chapter 8 (Supplemental Book
ARM Caches)
Slides Lecture # 15
Slides # 16
Finals - ??

10/29/215
11/5/2015

11/12/2015

12/3/2015

12/10/2015

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