DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING

Coimbatore-641 105
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Course code
Semester / Year
Faculty Name
Designation/ Dept.

:
:
:
:

EC6601(C314)
VI/III
Mrs. Janeera.D.A
Assistant Professor/ ECE

Course Title
Academic Year

:
:

VLSI Design
2015-2016

Prerequisite:
1. Engineering Physics
2. A basic knowledge on logic design, combinational and sequential logic
Aim:
To understand the concepts of CMOS technology including architecture, design, realization, operation and performance.
Objective:
1. In this course, the MOS circuit realization of the various building blocks that is common to any microprocessor or digital VLSI
circuit is studied.
2. Architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology are
discussed.
3. The main focus in this course is on the transistor circuit level design and realization for digital operation and the issues involved
as well as the topics covered are quite distinct from those encountered in courses on CMOS Analog IC design.
Outcomes
Sl.
No.
1.
2.
3.
4.
5.

Code
314.1
314.2
314.3
314.4
314.5

Outcomes
Explain the basic CMOS circuits and CMOS process technology
Discuss the factors of combinational logic design and power dissipation in CMOS circuits
Recognize different types of sequential logic circuits and compare low power memory circuits
Summarize architectures of arithmetic building blocks
Illustrate implementation strategies of FPGA architecture

PO-CO Mapping
CO
PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9

C314.1

C314.2

C314.3

C314.4

C314.5

C314

2.4

1.6

2.4

PO10 PO11 PO12 PSO1 PSO2

PO-CO Mapping Justification

C314.1
PO1: Basics of transistors, operation and properties are studied.
PO2: Study of electrical properties helps in identifying engineering problems in transistor design.
PO3: Stick diagram and layout diagrams allow component design based on the requirements specified.
PO12: Knowledge of advancements in VLSI technology creates inquisitiveness for continuous learning.
PSO1: MOS transistor principle gives an understanding of Electronic principles.
C314.2
PO1: Study of combinational logic design involves application of fundamental engineering knowledge.
PO2: Analysis of the best suited combination circuit for each application can be done.
PO3: Low power design principles assist in designing components meeting realistic constraints.
PO12: Knowledge of design principles creates inquisitiveness for continuous learning.
PSO1: Study of Combinational Logic Circuits gives an in-depth understanding of Electronic principles.
C314.3
PO1: Basic Digital principles are applied in understanding timing issues and clock strategies.
PO2: Speed and power issues are identified and analyzed in this chapter.
PO3: Understanding of low power memory circuits allows designing of components within realistic constraints.
PO12: Knowledge of memory circuits and their applications creates inquisitiveness for continuous learning.

PSO1: Study of Sequential Logic Circuits gives an in-depth understanding of Electronic principles.
C314.4
PO1: Basic Digital principles are applied in understanding operation of arithmetic building blocks.
PO2: Speed and area tradeoff is identified and analyzed in this chapter.
PO3: Understanding Speed and area tradeoff allows designing of components within realistic constraints.
PO12: Awareness on application of arithmetic circuits in VLSI creates inquisitiveness for continuous learning.
PSO1: Designing arithmetic building blocks gives an in-depth understanding of Electronic principles.
C314.5
PO1: An introduction to ASIC strengthens fundamental engineering knowledge in an application oriented perspective.
PO3: Building block architectures helps designing of components within realistic constraints.
PO12: Knowledge of design principles creates inquisitiveness for continuous learning.
PSO1: Implementation strategies of ASIC gives an in-depth understanding of Electronic principles.
Gaps Identified:
1. Technology related CAD issues and Manufacturing Issues
2. Need for testing of VLSI circuits
3. Introduction to HDL
Content Beyond Syllabus (CBS) Identified:
1. Semiconductor Memory- Trends and Evolution
2. NEMS in VLSI
Lecture Schedule
S.
No

Unit

Topics

2.

Introduction
to
Course
and
Outcomes
NMOS and PMOS
transistors

3.

1.

Process parameters
for MOS and CMOS

Hrs
Required

Planned
Hour/ Date

1/28.01.2016

3/30.01.2016

2/01.02.2016

Actual
Hour/ Date

Teaching
Aids

Knowledge
Level

Reference
Books

Chalk &
Talk
PPT
Chalk &
Talk

K1

R1

K3

T1

Web Resources
http://www.explainthatstu
ff.com/integratedcircuits.h
tml
http://web.cs.mun.ca/~pau
l/transistors/node1.html

Electrical properties
of CMOS circuits
and device modeling
Scaling principles
and fundamental
limits

4/01.02.2016

Chalk &
Talk

K2

R3

5/02.02.2016

Chalk &
Talk

K1

T1

1/04.02.2016
3/06.02.2016
2/08.02.2016
4/08.02.2016

Chalk &
Talk
Chalk &
Talk

K1

T1

K1

T1

4.

5.

6.

CMOS inverter
scaling

8.

Propagation delays

10.

Stick Diagram

5/09.02.2016

PPT

K4

R3

11.

Layout diagrams

1/11.02.2016

Chalk &
Talk

K4

R3

12.

GAP

Technology related
CAD issues and
Manufacturing Issues

3/13.02.2016

Chalk &
Talk

K4

R3

13.

II

Examples
of
Combinational Logic
Design

2/15.02.2016

Chalk &
Talk

K2

R1

14.

II

Elmores constant

4/15.02.2016

Chalk &
Talk

K1

T1

15.

II

Pass transistor Logic

Chalk &
Talk

K1

T1

17.

II

Transmission gates

Chalk &
Talk

K1

T1

19.

II

Static and dynamic

CMOS design

4/22.02.2016

Chalk &
Talk

K1

T1

20.

II

Power dissipation
Low power design

5/23.02.2016

K2

T1

5/16.02.2016
1/18.02.2016
3/20.02.2016
2/22.02.2016

Chalk &
Talk

https://www.youtube.com/
watch?v=9MBndFzBYtA

https://www.maximintegr
ated.com/en/appnotes/index.mvp/id/4243

principles

3/27.02.2016

Need for Testing

2/29.02.2016

Chalk &
Talk

K2

T1, R3

III

Static and Dynamic

Latches
and
Registers

4/29.02.2016

Chalk &
Talk

K1

T1

24.

III

Timing issues

5/01.03.2016

K1

T1

25.

III

Pipelines

1/03.03.2016

K1

T1

26.

III

Clock strategies

3/05.03.2016

K1

T1

27.

III

Memory architecture
and memory control
circuits

2/07.03.2016

Chalk &
Talk

K1

T1

28.

III

Low power memory

circuits

4/07.03.2016

Chalk &
Talk

K1

T1

29.

III

Synchronous
and
Asynchronous design

5/08.03.2016

Chalk &
Talk

K1

T1

22.

GAP

23.

Semiconductor
Memory- Trends and
Evolution

30.

CBS

31.

IV

Data path circuits

32.

IV

33.

IV

Architectures
for
ripple carry adders
Carry look ahead
adders

34.

IV

High speed adders

1/10.03.2016

3/12.03.2016

2/14.03.2016

4/14.03.2016

5/15.03.2016
3/19.03.2016

Chalk &
Talk
Chalk &
Talk
Chalk &
Talk

PPT /
Seminar

Chalk &
Talk
Chalk &
Talk
Chalk &
Talk
Chalk &
Talk

K4

K1

T1

K1

T1

K1

T1

K1

T1

http://anysilicon.com/indu
stry-trend-evolutionsemiconductor-chipcompanies-complexproduct-serviceorganizations/

36.

IV

Accumulators

2/21.03.2016

37.

IV

Multipliers

4/21.03.2016

38.

IV

Dividers

5/22.03.2016

39.

IV

Barrel shifters

1/24.03.2016

40.

IV

Speed
and
tradeoff

3/26.03.2016

41.

GAP

Introduction to HDL

2/28.03.2016

42.

Full custom and

Semi custom design

44.

Standard cell design

and cell libraries

46.

FPGA building block

architectures

48.

FPGA interconnect
routing procedures

50.

CBS

NEMS in VLSI

area

4/28.03.2016
5/29.03.2016
1/31.03.2016
3/02.04.2016
2/04.04.2016
4/04.04.2016
5/05.04.2016
1/07.04.2016

3/09.04.2016

Chalk &
Talk
Chalk &
Talk
Chalk &
Talk
Chalk &
Talk
Chalk &
Talk
Chalk &
Talk
Chalk &
Talk

K1

T1

K1

T1

K1

R1

K1

T1

K5

T1

K3

R1

K1

T2

Chalk &
Talk

K1

T2

Chalk &
Talk

K1

T2

Chalk &
Talk

K1

T2

PPT

K3

http://circuitcellar.com/tec
h-the-future/the-future-ofvery-large-scaleintegration-vlsitechnology/

Text Books:
T1. Jan Rabaey, Anantha Chandrakasan, B.Nikolic, Digital Integrated Circuits: A Design Perspective, Second Edition, Prentice
Hall of India, 2003.
T2. M.J. Smith, Application Specific Integrated Circuits, Addisson Wesley, 1997

Reference Books:
R1.N.Weste, K.Eshraghian, Principles of CMOS VLSI Design, Second Edition, Addision Wesley 1993
R2. R.Jacob Baker, Harry W.LI., David E.Boyee, CMOS Circuit Design, Layout and Simulation, Prentice Hall of India 2005
R3. A.Pucknell, Kamran Eshraghian, BASIC VLSI Design, Third Edition, Prentice Hall of India, 2007.
NPTEL Videos:

1. VLSI Circuits: http://nptel.ac.in/video.php?subjectId=117106092

2. VLSI Technology: http://nptel.ac.in/courses/117106093/1
3. VLSI Design: http://www.nptelvideos.in/2012/12/vlsi-design.html
Internal Assessments:
S.No
Test
1.
Internal Test 1
2.
Internal Test 2
3.
Model Exam

Tentative dates
February 25, 2016
March 17, 2016
April 21, 2016

Portions
Unit 1, Unit 2 up-to Pass Transistor Logic
Unit 2 from Transmission Gates, Unit 3
All 5 Units.

Assignments:
S.No

Unit

1.
2.
3.
4.
5.

I
II
III
IV
V

Assignment topic
Stick Diagram
Power Dissipation
Low power memory circuits
Power reduction techniques
FPGA architecture

Resources
R3, Internet (Not limited)
T1, Internet (Not limited)
T1, Internet (Not limited)
T1, Internet (Not limited)
T2, Internet (Not limited)

Additional Activities Planned:

S.No
Activity
1.
Seminar on Semiconductor Memory- Trends and Evolution
2.
One day National Level Workshop on VLSI system design

Mrs.D.A.Janeera,
Faculty Incharge

Date of
Announcement
09.02.2016
23.02.2016
07.03.2016
26.03.2016
04.04.2016

Date of
Submission
18.02.2016
01.03.2016
15.03.2016
02.04.2016
09.04.2016

Tentative Date
10/03/2016
01/04/2016

Dr.S.Malathy,
HOD