978-4-86348-009-4
these dipole shifting layers did not significantly affect the other key
parameters of the devices and this was part of the final piece of the
puzzle that allowed CMOS devices to simultaneously exhibit
acceptable mobility, Tinv, reliability, and threshold voltage [7].
Figure 4 shows a cross section of fully processed HKMG Transistor.
The AC performance benefit (Figure 5) using HKMG is realized
with a 40% RO delay improvement (at a fixed leakage) over
conventional 45nm SiON/Poly-Si process [8], which is a direct
reflection of increased drive current due to Tinv scaling and reduced
capacitance penalty due to Lgate scaling. Next generation HKMG
processes showing further reduction in Tinv targeted for 22nm are
also being reported [9].
As gate length scaling continues to dominate the
requirements for newer technology generations, it may become very
challenging for the high-k/metal gate process alone to provide
sufficient short-channel control for the 15nm technology node and
beyond. Device structures such as FinFET shown in Figure 6 and
ultra-thin-body SOI provide improved device electrostatics and offer
additional scaling of gate length [10]. A significantly improved
DIBL characteristic can also be achieved in a FinFET device making
it superior to a planar device for the same high-k/metal gate process.
The three dimensional nature of the fin changes the behavior of
typical device parasitics Rext (external resistance) and Cgd (gate to
drain capacitance). Careful engineering is required to minimize this
external resistance and stray capacitance. These alternate device
structures are strong contenders for replacing conventional planar
device structures by the 15nm technology node.
A nanowire FET with a wrapped-around gate conductor
provides the ultimate control over the channel. The coaxial-like
geometry also opens a path to a less aggressive scaling of the gate
dielectric due to the logarithmic dependency of the gate capacitance
on the gate dielectric thickness. Strain is easily coupled into the
channel since the nanowire diameter is of comparable dimension to
the gate dielectric and gate conductor. Both longitudinal and radial
strain need to be considered. The mobility enhancement for n-FETs
and mobility reduction for p-FETs has been demonstrated for
nanowire channels with a constant height and a variable width [11].
Reducing variability in these devices is a key challenge in making
nanowire FETs a viable technology. Figure 7 shows a TEM crosssection parallel to the FET gate line in nanowires. Although
nanowire sidewalls comprise several crystallographic planes, the
measured Id-Vg characteristics exhibit a low density of interface
states with subthreshold slopes ranging between 63-75 mV/dec. The
carrier transport as a function of the channel diameter has also been
investigated for nanowires fabricated with bottom-up and top-down
methods [12,13].
Carbon Electronics: Extending beyond Silicon
Graphene is a two-dimensional material comprising a monolayer of
carbon atoms arranged in a honeycomb lattice as shown in Figure
8(a). Since graphene was discovered in 2005 [14,15], its exceptional
electronic properties have attracted much attention. High carrier
mobility up to 200,000 cm2/Vs has been experimentally
demonstrated in suspended graphene [16,17]. Owing to its 2D nature,
ultimate electrostatic short channel control can be expected in
graphene. Graphene has symmetrical energy dispersion for electrons
and holes, so equivalent p-type and n-type FET behaviors are
expected for CMOS type applications. Experiments have already
demonstrated the ability to take advantage of existing lithographical
and patterning techniques to fabricate graphene as shown in Figure
8(b). Perhaps the most interesting and unique point about graphene
is the possibility to have different band gaps on the same graphene
sheet. [18,19].
Acknowledgements
The author acknowledges contributions from members of the
Science and Technology Department at IBM Research, in particular
Mukesh Khare, James Stathis, Vijay Narayanan, Timothy Dalton,
Wilfried Haensch, Chung Lam, Supratik Guha, Guy Cohen, Yurij
Vlasov, Steve Koester, and John Knickerbocker, for their valuable
discussions and suggestions.
10
978-4-86348-009-4
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[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
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[16]
[17]
[18]
[19]
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[21]
[22]
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
[32]
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[34]
[35]
[36]
[37]
[38]
[39]
[40]
[41]
[42]
[43]
[44]
[45]
4x / 2 years
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High-Performance
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15
Fig. 3 HRTEM and EELS of an n-FET band-edge gate stack process [7]. Fig. 4 TEM of a fully processed
HKMG Transistor.
HfSiON
nanowire
SiO2
Contact
Silicide
poly-Si
gate
Final Spacer
Gate
T iN g a te
Al
S/D
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Original Fin
under gate
S iO 2
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Fig. 8 Graphene
A: Two dimensional honeycomb
B: Lithography patterned nano-ribbons.
W TSV
Cooling
Substrate
Decoupling Capacitors
25 Pm
Die Stack
TSV
Top wafer
Vertical
Interconnection
Si Pkg or Pkg
Substrate or PWB
TSV
TSV
20 Pm
Bottom wafer
Fig. 12 Schematic cross section for A: 3D Fig. 13 3DI process on 300mm wafers [44,45].
silicon package and B: 3D die stacks.
11