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Code t 9EE'-24

II

Semester Diploma Examination, Nov./Dec.,

ELECTRONICS

IMax. Marks : 100

g.

(i)
(ii)

Note:

-I

Section

-l

is compulsoryt.

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Time : 3 Hours

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m

Register
Nwnber

Answer any six fulI questions taking two fulI questions from each section.

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rI

(a)

1.

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SECTION _ I

Fill in the blanks :

5x1:5

.p

Explain thermal runway.

SECTION _

(b)

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w

(i) If the PN junction is heavily doped, Breakdown voltage will


temperature co-efficient of resistance.
(ii) A semiconductor is
(iii) There are
digits in decimal number systems.
are the minority carriers.
(iv) In p type semiconductor
(v) A Boolean expression for two input AND Gate is

(a)

2.

II

Explain the structure of Germanium & Silicon.

intrinsic & extrinsic

semi conductor.

Di fferentiate between

Explain the working of PN Junction diode in Forward Bias

(b)
(c)

3.

(a)

Explain Zener diode

(b)

Derive the relationship between cr &

&

Reverse Bias

with neat diagram.

as voltage Regulator

B.

with neat circuit

diagram.

5
4

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For the circuit,given below,

Find

(a) Output voltage


(b) Voltage drop across series resistance
(c) The current through Zenerdiode

R=2kQ

(c)

g.
co

(b)
(c)

tl

Explain the three regions of operation,


saturation, active and cut offregion for
CE configuration.
6
Explain with sketch, the working of MOSFET.
7
List the applications of JFET.

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(a)

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4.

lll

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R1= 4 kf,)

t,h
i i,'

(a)
(b)
(c)

(a)

lt

(b)

ri

(c)

Define SSI, MSI, LSI, VLSI and ULSI.


Subtract (l1000)2 from (1001l), using
2,s

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II

SECTION _ III
Explain the necessity of heat sink for power
transistor.
Explain working of photo voltaic cell.
List any two applications each for LED,
LCD & LDR.

5.

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t+,

Convert the following


(35)ro to Binary

(i)
(ii)

iF
I

I
i

7. (a)

(b)

(t234.56)rcto Octal
(Vgg.t2)rcto Hexadecimal

(iii)

(123.236)Bto Decimal

Define:

Bit
Nibbte

(iii) Byte

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I

\i.-

4
6

(i)
(ii)
(i)
(ii)

(ABC),6 to Decimal

Convert the following

compliment method.

.p

'l

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3

SECTION

- IV

(a)

Explain different laws in Boolean Algebra.

o)

Realize oR Gate,

(c)

Minimize the following Boolean expression

Gate

& Ex-oR Gate using NAND


:

Draw Logic Diagram, Logic Symbol, Expression and Truth Table for universal

(iiD

Propagation Delay
Noise Margin

List any three characteristics of TTL family.

aw

(c)

Threshold voltage

ik

(i)
(ii)

.p

ed
i

(a) State Demargon's Th@re,rns.


p) Explain how to interface TTL with LEDS.
(c) Explain how to interface CMOS with motors.

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.4:r---

ib

Define

lo

Gates.

O)

Y=(AE(C+B)+As)C

(a)

Gates only.

g.
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Nor

4
6
5