A 1.

7mW All Digital Phase-Locked Loop with

New Gain Generator and Low Power DCO
Tzu-Chiang Chao and Wei Hwang
Department of Electronics Engineering & Institute of electronics, and
Microelectronics and Information Systems Research Center,
National Chiao-Tung University, HsinChu 300, Taiwan
ctc.ee9 1 g(n
du.tw, Hwangmai .nctu .edu.tw
Abstract-In this paper, a new architecture and algorithm for
all digital phase-locked loop (ADPLL) is proposed. By using
the new search algorithm, it can accomplish phase lock process
within 18 input clock cycles. By using the new architecture, we
can combine the functions of the frequency comparator, phase
detector and gain generator in one hard block. Also, a new
digitally controlled oscillator (DCO) structure for low power,
small area is presented and its frequency range is from 200
MHz to 750 MHz with a supply voltage 1.2v. The total power
consumption of ADPLL is 1.7mW. This ADPLL has
characteristics of fast frequency locking, small hard cost and
lower power consumption. This ADPLL is designed and

Inrual

MJodified BiEary Search

nleal
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INTRODUCTION

)2006 IEEE

Propose Search

Figure 1. Modified Binary Search VS. Dynamic Control

Gain Search

A phase-locked loop (PLL) is a widely used circuit for

clocking digital IP-blocks. Traditionally, a PLL is made as
an analog building block. However, integrating an analog
PLL in a digital noisy systems-on-a-chip (SoC) environment
is challenging. In addition, the analog PLL is sensitive to
process parameters and must therefore be redesigned for
each new technology.
Digitally controlled clock generators cannot compete
with analog implementations in terms of high clock rate
combined with low phase noise, but are much easier to
implement without targeting at a specific technology.
Assuming that all digital phase-locked loop (ADPLL) is
implemented with only active components such as transistors,
it will scale with technology. Capacitors and resistors, which
are used in analog circuits will not scale with technology to
the same extent [1,2]. Also, integrating an analog circuit
with digital circuit has the noise problem. The digital noise
effect the performance of the analog circuit. It is difficult to
isolate the noise which generated from the digital part. It is a
good idea that using the ADPLL in digital systems.
The rest of this paper is organized as follows: Section II
will describe the proposed dynamic control gain search.
Section III will describe the proposed ADPLL architecture.
Section IV will show the simulation result and layout.
Section V is conclusion.

0-7803-9390-2/06/$20.00

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implemented by TSMC's 0.13um CMOS technology.

I.

Target

II.

THE ALGORITHM ANDARCHITECTURE OF ADPLL

A. Algorithm
In this section, we will discuss the algorithm of the
ADPLL. The conventional ADPLL [3] uses four modes of
operation: frequency acquisition, phase acquisition,
frequency maintenance and phase maintenance. Each mode
is like a "search" algorithm with different adaptive scheme.
Phase lock begins with frequency acquisition. When
frequency acquisition is complete, the ADPLL enters phase
acquisition mode. After phase lock completes, the ADPLL
enters both frequency maintenance and phase maintenance.
In frequency acquisition mode, in order to find the target
frequency, the conventional ADPLL uses a modified binarysearch algorithm. The modified binary-search algorithm [3]
was shown in Fig. 1. The modified binary-search algorithm
sweeps the digitally controlled oscillator (DCO) frequency
range to match the target frequency. On every change in
search direction the frequency gain is reduced by a factor of

2.

Fig. I also shows the proposed search algorithm.

Comparing the modified binary search with our proposed
search, the difference is the change of gain value. In new
algorithm, the frequency comparator can find the optimized
gain value and reduce the searching step by the optimized
gain value. So in new searching algorithm, ADPLL do not

4867

ISCAS 2006

need to sweep the overall DCO frequency range to match the

external frequency.
In phase acquisition mode, our ADPLL aligns the
buffered output (do not need divider circuit) of the DCO to
the matched delay reference clock. In new algorithm, we
execute the frequency acquisition and phase acquisition at
the same time. So we use only one mode to finish the
frequency acquisition, phase acquisition and frequency/phase
maintenance. In our ADPLL algorithm, the operation is just
like the digital phase-locked loop (DPLL) but the design of
the building block is all digital circuit.
Architecture
There are some major building blocks in the proposed
ADPLL. They are phase/frequency detector (PDF), gain
register, DCO, Control unit, DCO enable generator and
multiplexer. Fig.2 shows the block diagram of the proposed
ADPLL.

B.

Register

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Figure 2. ADPLL Architecture

The function of each block will be described in the

following:
(1) PFD

The proposed PFD can detect the frequency and phase

error between internal signal and external signal. It generates
two types of signals, the first type of signal is Fast/Slow
signal. The second type of signal is the gain value for gain

register.

(4) DCO Enable Generator:

The DCO enable generator will generate the enable
signal and disable signal for digital controlled oscillator. By
using this DCO enable generator we can align the first rising
edge of external signal and internal signal every two
reference cycles. When the enable signal is low, the DCO
will be disabled and the disable time is very short.

III.

A. Phase/Frequency Detector
In conventional ADPLL, the frequency comparator
accepts the reference clock and the output of DCO output
buffer as its inputs. The frequency comparator will generate
the Fast signal or the signal Slow. The phase detector also
detects the reference clock and the output of the DCO output
buffer and generates the Ahead signal or the Behind signal.

In our ADPLL, we combine the two function blocks

(frequency detect and phase align) and they work in one
mode. So our proposed PFD detects the frequency and the
phase at the same time. The PFD also provides the
information of the gain value without using modified binary
search. The proposed PFD was shown in the Fig.3.
As shows in the Fig.3, our PFD detects the frequency and
phase every two reference cycles so the frequency of the
reference clock was divided by two. The positive edge block
will generate a pulse signal at rising edge of the input signal.
The output of the positive edge block will clear the output of
each D Flip-Flop at the rising edge of every two references
lclocks. The fourteen D Flip-Flops detect the frequency and
generate the information of gain value. The D8 1 signal was
delayed by two inverters from D8 signal so the D8 signal and
D8_1 signal was very closely.
The waveform of our PFD was shown in the Fig.4, it was
shown the case when the ADPLL frequency/phase was
locked. The detected point is at the rising edge of the
reference clock, when the ADPLL was locked, the D8 signal
was low and the D8_1 signal was high at the detected point.
If the D8 signal is already high at the detect point, it means
the DCO frequency is faster than the target frequency. In
other words, if the D8 signal is low at the detected point, it
means that the DCO frequency is slower than the target
frequency. So our ADPLL lock the frequency by the D FlipFlop and align the phase by the delay method.

B.

(2) Multiplexer
Because the PFD will generate two different gain values
(one is for fast case and another is for slow case) so we need
a multiplexer to select the gain value,

(3)DCO
DCO is the heart of the ADPLL. It is a ring oscillator and
it is constructed by inverters. The frequency control
mechanism is through the binary weighted control word and
the control word is generated by the DCO register.

CIRCUIT DESIGN

Gain Generator

In our algorithm, we don't use the modified binary

search algorithm and we generate the gain value by the
output information of the PFD. By the output of the PFD,
we can get two different gain values. The ADPLL select
the two gain values by the fast signal. In the Table 1, we
show the relation between the gain value and the output of
the PFD. For example, ifthe DCO frequency is 600MHz

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Table I. Gain Value V.S ds PFD Output Signals

Gain value bit
Gain|
PFD
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value
Inp Output |[0][1][2] [3][4][5][6][7]v
Signal,
4Dt 1 D8 5 D9 DIODI DI 0 0
~~~~~~~~~~~~DCO
Frequency

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Figure 3. PFD circuit

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(When the DCO frequency is bigger than the target frequency)

High

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Digital Controlled Oscillator

Like most voltage-controlled oscillator, the DCO consists
of a frequency-control mechanism with an oscillator block.
There are two parameters to modulate the frequency of the
ring oscillator. One is the propagation delay time of the
inverter and another is the total number of inverter. In our
DCO design, we only modulate the parameter of the inverter
propagation delay time. But the propagation delay time of
the inverter is controlled by two mechanisms. One
mechanism is the width of the inverter and another is the
turned on voltage of the switch.
C.

Low

Figure 4. PFD waveform(when ADPLL in locked state)

(600MHz is faster than the target frequency 560MHz), the

D8 signal and the D8_1 signal are high at detected point and
the others (D8_5, D9-D 12) are low. When the DCO
frequency is 600MHz, the gain value is three. When the
DCO frequency becomes more far from the target frequency,
the gain value becomes larger. The gain generator just likes
the charge pump, it provide the magnitude to the Add/Sub
block. When the DCO frequency is slower than the target
frequency, the fast signal becomes low and the gain value is
provided by another output information (D4- D7_5) of the
PFD. The first case (fast signal is high) is similar with the
second case (fast signal is low). We only show the first case
in this section.

Our proposed DCO was shown in the Fig.5. The DCO

consists of coarse cell, fine cell, unit gain circuit and voltage
divider The DCO control word is the 8 binary weighted
control signals. The weighted control signals DCO[4]~
DCO[5] control the coarse cell and the others control the fine
cell. The switch of the coarse cell is turned on by the
Voltage_A and the switch of the fine cell is turned on by the
Vdd voltage or Gnd voltage. By the two stages method, we

4869

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area. The frequency range of DCO is from 200 MHz to

750 MHz with a supply voltage 1.2v. The total power
consumption of ADPLL is only 1.7mW and its area is
200um x 100um in a TSMC's 0.13um 1P8M CMOS

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ACKNOWLEDGMENT

|The work is supported by National Science Council,

R.O.C., under the project NSC 92-2220-E-009-01 1, NSC 932220-E-009-024 and TSMC grant. This work is also
supported by DoE/DoIT 94-EC-17-A-01-S1-034. The
authors would like to thank SOC Research Center in NCTU
for support of this research.

CO

REFERENCES

output

Figure 5. The proposed DCO

[1] T. Olsson and P. Nilsson, " A digital PLL made from standard cell,"

Voltage-A

[2]

[3]

OLj

7T Wl1

W141

p1

p2

lwlT
p

W171T
p4

in Proc. 15th ECCTD, pp.277-280, 2001.

T. Olsson and P. Nilsson, A digitally controlled PLL for SoC
applications," IEEE J. Solid-State Circuits, Vol. 39, pp.751 - 760,
May 2004.
J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An ALL
Phase-Locked Loop with 50-cycle Lock Time Suitable for
Digital
High Performance Microprocessors," IEEE J. Solid-State
Circuits,Vol.30, pp.412-422, Apr. 1995.
"

MP

IN

OUT
OUT
IN

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ni

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n4

1[71

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Figure 7. (a) Unit Gain Circuit

Voltage A

DCO Freq V.S. DCO control word

Figure.6 the coarse cell of the proposed DCO

can save the area and power consumption. The coarse cell of
the DCO was shown in the Fig.6. The fine cell is the same
with coarse cell but the Voltage A becomes Vdd voltage or
Gnd voltage. The Unit gain circuit was shown in the Fig.7(a)
and Fig.7(b) was simulation result of the DCO frequency vs.
DCO control word.
SIMULATION AND MEASUREMENT RESULTS
The layout was shown in the Fig.8 and the area is 200um
x 100um in a TSMC 0.13um CMOS technology. The DCO
runs up to 560MHz (70MHz x 8) with a supply voltage 1.2v
and the resolution is 8 bits. The ADPLL total power
consumption is 1.7mW and the jitter (by built-in jitter test) is
161.4ps at DCO output frequency range 560 MHz.

1000
200 l
0
`

CONCLUSIONS

In this paper, a new type ADPLL for fast lock process,

small

area

and

lOW

power

consumption

iS

proposed.

proposed PFD is used to reduce the lock cycle time. The

proposed DCO is used to reduce power consumption and

4870

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Digital Control Word

IV.

V.

Pg

Figure 7. (b) the frequency vs. control word

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Figure 8. Layout Implementation