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Introduction to

CMOS VLSI
Design

Layout, Fabrication, and


Elementary Logic Design
Adapted from Weste & Harris
CMOS VLSI Design

Overview
Implementing switches with CMOS transistors
How to compute logic functions with switches
Fabricating transistors on a silicon wafer and
connecting them together

Fabrication and Layout

CMOS VLSI Design

Slide 2

Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

Fabrication and Layout

CMOS VLSI Design

Slide 3

Dopants

Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)

Fabrication and Layout

CMOS VLSI Design

Slide 4

p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction

Fabrication and Layout

CMOS VLSI Design

Slide 5

nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator

Fabrication and Layout

CMOS VLSI Design

Slide 6

nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

Fabrication and Layout

CMOS VLSI Design

Slide 7

nMOS Operation
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

Fabrication and Layout

CMOS VLSI Design

Slide 8

pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

Fabrication and Layout

CMOS VLSI Design

Slide 9

Power Supply Voltage


GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

Fabrication and Layout

CMOS VLSI Design

Slide 10

Transistor Abstraction

3D structure formed by fabrication


2D planar layout view
Schematic symbol
Switch

CMOS VLSI Design

Slide 11

Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain

Fabrication and Layout

CMOS VLSI Design

Slide 12

Switching Logic
conducts iff
ab
(0 only)
a

conducts iff
a+b
(0 only)

s
b

a
s

b
d

s
b

conducts iff
a'b' or (a+b)'
(1 only)
CMOS VLSI Design

conducts iff
a'+b' or (ab)'
(1 only)
Slide 13

Implementation of Logic Gates


OR gate

a
1

f(a,b)

a+b

Two problems
1) when a=b=0, f(a,b) is undefined (floating)
2) n- type switches do not conduct 1 well
Two solutions
when f=0, connect output to 0v using n-type switches
when f=1, connect output to 1v using p-type switches
CMOS VLSI Design

Slide 14

Complementary CMOS Gates


Pull-up network consisting of p-type devices
Pull-down network consisting of n-type devices

1v (logic 1)

P
inputs

output
N

Example: an inverter
a

a'

pull-up

pull-down

0v (logic 0)

: a'
a

a'

: a

CMOS VLSI Design

Slide 15

CMOS Inverter
A

0
1

Fabrication and Layout

CMOS VLSI Design

Slide 16

CMOS Inverter
A

0
1

Fabrication and Layout

CMOS VLSI Design

Slide 17

CMOS Inverter
A

Fabrication and Layout

CMOS VLSI Design

Slide 18

CMOS NAND Gate


A

Fabrication and Layout

CMOS VLSI Design

Slide 19

CMOS NAND Gate


A

Fabrication and Layout

CMOS VLSI Design

Slide 20

CMOS NAND Gate


A

Fabrication and Layout

CMOS VLSI Design

Slide 21

CMOS NAND Gate


A

Fabrication and Layout

CMOS VLSI Design

Slide 22

CMOS NAND Gate


A

Fabrication and Layout

CMOS VLSI Design

Slide 23

CMOS NOR Gate


A

Fabrication and Layout

CMOS VLSI Design

Slide 24

3-input NAND Gate


Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

Fabrication and Layout

CMOS VLSI Design

Slide 25

3-input NAND Gate


Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

Fabrication and Layout

CMOS VLSI Design

Slide 26

Switch Logic vs. Gate Logic


Example: two-input multiplexer
a
b

2:1

f=a,

when s=0

f=b,

when s=1
f=s'a+sb

CMOS VLSI Design

Slide 27

Switch Logic vs. Gate Logic


Two-input mux with gate logic (14 transistors)

Two-input mux with switch logic (6 transistors)

complementary
pass transistor
CMOS VLSI Design

Slide 28

Implementing LUTs
Multiplexor logic simple switch network (a tree)
inputs: programming bits
Bit0 Bit1 Bit2 Bit3 Bit4
controls: inputs to CLB
A'
output: function value
However, series transistors A
are slow O(n2)

Bit5 Bit6 Bit7

B'
B

C'
C

CMOS VLSI Design

Slide 29

Programmable Interconnect
Switches connect wires at intersections
Can also be used to segment wire
Repeaters needed every so often
simple non-inverting buffers (2 inverters)
otherwise, too many switches in series slow down signal

CMOS VLSI Design

Slide 30

Master-Slave Register

CMOS VLSI Design

Slide 31

Dynamic Register

CMOS VLSI Design

Slide 32

Latch-Based Design
Switches and/or gates compute new values to store
on next clock cycle
straightforward implementation
CL
2

this circuit can use the entire clock cycle no wasted time - a form of retiming

CL

CL
2

CMOS VLSI Design

Slide 33

Static Memory Cell


8-transistor cell
N-transistor only: 6T cell
bit

bit'

rd or wr

(rd or wr)'

CMOS VLSI Design

Slide 34

Dynamic Memory Cell


1-transistor cell

precharge to
intermediate
voltage level

storage capacitor
is one end of transistor

charge sharing with


bus capacitance
(Ccell << Cbus)
extra demands on
sense amplifier to
detect small changes
in bus charge

destructive read
(must immediately
write back)

CMOS VLSI Design

Slide 35

Dynamic storage
Capacitor implemented by gate capacitance of
transistor
No capacitor is perfect
charge leaks away through imperfect switches
Must be replenished or refreshed
'memory' lasts about 1ms
Solution: periodically read the value and write it back

CMOS VLSI Design

Slide 36

Read-only Memory Cells


To store constants or other invariant data
Popular for control implementation
bit1

bit2

bit3

read1

read2

programmable logic array structure


(exploits distributed NOR gate structure)
CMOS VLSI Design

Slide 37

Multi-ported Register Cells


Augment 6T cell for more I/O
bus2'

bus1
row-bus1

row-bus2
bus2

bus1'
CMOS VLSI Design

Slide 38

CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

Fabrication and Layout

CMOS VLSI Design

Slide 39

The wafer
Czochralski process
Melt silicon at 1425 C
Add impurities (dopants)
Spin and pull crystal
Slice into wafers
0.25mm to 1.0mm thick
Polish one side

CMOS VLSI Design

CMOS VLSI Design

Crystal and wafer

Wand
(a finished 250lb crystal)

A polished wafer

CMOS VLSI Design

The mask
Illuminate reticle on wafer
Typically 4 reduction
Typical image is 2525mm
Limited by focus
Step-and repeat across wafer
Limited by mechanical alignment

CMOS VLSI Design

4X reticle

Wafer

Lithography
Patterning is done by exposing photoresist with light
Requires many steps per layer
Example: Implant layer

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Grow Oxide Layer

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Add Photoresist

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Mask

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Expose using UV Light

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Develop and Remove Resist

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Etch Silicon Dioxide

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Remove Resist

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Implant Dopant

CMOS VLSI Design


Reference:
FULLMAN KINETICS

Inverter Cross-section
Typically use p-type substrate for nMOS transistor
Requires n-well for body of pMOS transistors
Several alternatives: SOI, twin-tub, etc.

Fabrication and Layout

CMOS VLSI Design

Slide 53

Inverter Layout
Transistors and wires are defined by masks
Cross-section taken along dashed line

Fabrication and Layout

CMOS VLSI Design

Slide 54

Advanced Metallization - Copper

CMOS VLSI Design

Copper versus Aluminum


~ 40% lower resistivity
~ 10 less electromigration

A View of Interconnect
Layers

CMOS VLSI Design

Slide 56

Package-to-Board Interconnect

Digital Integrated Circuits


CMOS VLSI Design

2nd

Flip-Chip Bonding

Digital Integrated Circuits


CMOS VLSI Design

2nd

Package Types

CMOS VLSI Design


Digital Integrated Circuits2nd

Multi-Chip Modules

Digital Integrated Circuits


CMOS VLSI Design

2nd