Submitted to
Department of Electronic Engineering
by
Wang Huai
March 2012
Abstract- i
ABSTRACT
This thesis presents the findings of research on new high-voltage medium-power
dc-dc conversion technologies.
converter and two multi-level step-down high input voltage converters have been
investigated. A switched-capacitor snubber is proposed for zero-current-switching (ZCS)
of the four IGBTs in the full-bridge converter. The ZCS can be achieved with minimum
circulating current under different loading condition due to the self-adaptable resonant
energy in the snubber. Two kinds of energy-efficient solutions are presented to perform the
conversion from high input voltage to low output voltage. One is by using a multi-level
multi-phase topology with zero-voltage-switching (ZVS) to reduce the voltage stress on the
primary-side switches and improve the output current capacity. The other is by employing
a three-level converter featured with different voltage stresses on the two series-connected
switch pairs, allowing optimal selection of switching devices and wide soft-switching load
range. In practice, the low output voltages of the high-voltage converters are usually used
to supply various low-voltage converters which are exposure to momentary loads. To
improve the dynamic response, a generalized fast transient controller is proposed for
different type of low-voltage converters based on the derivation of a uniform second-order
switching surface. The considerable power loss and short lifetime of aluminum electrolytic
capacitors in power converters impose massive challenges to push up efficiency and
lifetime. Therefore, a novel concept to reduce the dc-link capacitance by introducing a
voltage compensator connecting in series with the dc bus line is proposed and studied. It
explores the possibilities to replace the electrolytic dc-link capacitors in high-voltage power
converters by long lifetime low power loss film capacitors without sacrificing power
Abstract- ii
The
principle and associated application limitation of switching surface control for dc-dc
converters will be illustrated. Available concepts and solutions to reduce dc-link capacitors
in power electronic systems will be presented.
In Chapter 2, the concept of adaptive snubber energy for ZCS will be presented.
The operating principles of the proposed current-fed full-bridge converter will be described.
The trade-off design and small-signal model will be given.
Implementations and
determine the dc conversion ratio and the ZVS conditions in an analytical form. The selfbalance property of the voltages across the input capacitors will be described. A 1500 V /
48 V, 2 kW prototype with four switch pairs in the primary-side is designed, implemented,
and evaluated.
In Chapter 4, another solution to convert 1500 V dc to 48 V dc will be presented
based on a novel concept, by which the voltage stresses on the series-connected two switch
pairs are asymmetric. The advantages of a three-level converter adopted the proposed
concept will be illustrated in terms of utilization of switching devices and load range for
Abstract- iii
boost converter prototype will be also analyzed to exhibit the performance of the controller.
In Chapter 6, a patent-pending technology for reducing dc-link capacitance in
capacitor-supported power electronic systems will be presented. The operation principle
and implementation of the proposed voltage compensator will be discussed. Simulation
and experimental results will be provided to verify the theoretical analysis.
In Chapter 7, conclusions and suggestions for future research on this topic will be
given.
ACKNOWLEDGEMENT
I would like to thank many people who made the work described here possible.
First of all, my gratitude is due to my supervisor Prof. Henry S. H. Chung, for his
choice to recruit me as a research student in 2007, for his sparkling ideas that brought me
into the world of power electronics and for his kind guidance and support during my study
at the City University of Hong Kong. The philosophy he embraces will continue to benefit
me both in research and life.
I am also deeply grateful to Prof. Adrian Ioinovici at Holon Institute of Technology,
for his critical questions in every single discussion, for his patient instructions from a single
word to a full research paper and for his encouragement during my research and life.
I would like to thank Prof. Ron S. Y. Hui, Dr. Wei Yan, Dr. Ricky W. H. Lau, Dr.
Norman C. F. Tse and Dr. K. F. Tsang, for their kind help during my study. I would like to
thank all of other research students and staff at the Centre for Power Electronics for their
help and friendship every single day.
Canales for their professional supervision during my internship at ABB Corporate Research
Center, Switzerland.
I would also like to thank Prof. Jason Lai from Virginia Tech, USA, Prof. Ashoka K.
S. Bhat from University of Victoria, Canada and Dr. L. F. Yeung from City University of
Hong Kong, Hong Kong, for serving on my Ph.D. oral examination committee.
Finally, my heartfelt appreciation goes toward all of my family members, who are
always there for me with their support and encouragement throughout my education.
TABLE OF CONTENTS
ABSTRACT
ACKNOWLEDGEMENT
TABLE OF CONTENTS
CHAPTER 1 OVERVIEW AND BACKGROUND OF RESEARCH ...................... 1
1.1. INTRODUCTION................................................................................................... 1
1.2. COMPONENT LEVEL ........................................................................................... 3
1.2.1. MOSFET and IGBT.................................................................................... 3
1.2.2. Aluminum Electrolytic Capacitor and Power Film Capacitor .................. 6
1.3. CIRCUIT LEVEL .................................................................................................. 7
1.3.1. Switch Pairs and Their Combinations ....................................................... 7
1.3.2. Soft-Switching Technology ....................................................................... 10
1.3.3. Selection of Topology ............................................................................... 12
1.4. SYSTEM LEVEL ................................................................................................ 14
1.4.1. Single-Step Conversion Concept .............................................................. 14
1.4.2. Fast Transient Control Methods for Load Converters ............................. 16
1.4.3. E-Cap Reduction Technology ................................................................... 20
1.5. ORGANIZATION OF THE THESIS......................................................................... 24
CHAPTER 2 HIGH OUTPUT VOLTAGE ZCS CURRENT-FED FULL-BRIDGE
CONVERTER WITH SELF-ADAPTABLE SOFT-SWITCHING
SNUBBER ENERGY ............................................................................... 26
2.1. INTRODUCTION................................................................................................. 26
2.2. CURRENT-FED ZCS FB CONVERTER AND ITS OPERATION PRINCIPLE .............. 27
Chapter 1-1
CHAPTER 1
OVERVIEW AND BACKGROUND OF RESEARCH
1.1. Introduction
The objective of this work is to provide essential basis for achieving energy-efficient
and environmental-friendly high-voltage dc-dc converters. Specifically, research on circuit
topology, soft-switching scheme, fast transient control method and electrolytic capacitor
reduction technology has been carried out.
The evolution of modern power electronics has witnessed its fast expanding in
emerging applications and its indispensable role in processing electric energy [1]-[4].
Extensive technological advancement in power electronic converters has significantly
improved the conversion efficiency and quality of electric power. Many efforts have been
made to the research on low-voltage power converters (below 1000 V) to push up the
efficiency, power density or switching frequency [5]-[15]. However, the research pace on
high-voltage power converters, especially on the high-voltage dc-dc converters, is much
less notable. High-voltage dc-dc converters are crucial parts in systems such as medical Xray diagnostic equipment [16], traveling wave tube amplifiers [17], electric railway [18][19], etc.
One of the key challenges in high-voltage dc-dc converters is that the advancement
of high-voltage switching devices is less impressive than that of low voltage ones in terms
of power loss, switching speed, reliability, availability and cost. Therefore, the circuit level
performance is limited due to the relatively low allowable switching frequency and high
power loss of high-voltage switching devices.
Chapter 1-2
Fig. 1.1 shows the block diagram of a typical switched-mode power converter.
Various topologies are formed by combining five different types of components in different
ways. The performance of the converter depends on the selected components and topology
and the applied control scheme. When a power conversion system consisting of more than
one converter is considered, the system performance depends on both the converters and
the electrical architecture of the system. Therefore, it is necessary to investigate into the
suitability of devices, corresponding topologies as well as specific power conversion
systems to tackle the challenges in high-voltage dc-dc power conversions.
Chapter 1-3
the components which are critical to the circuit level performance in this research work.
1.2.1. MOSFET and IGBT
Among various types of switching devices, the power metal-oxide-semiconductor
field effect transistor (MOSFET) and insulated gate bipolar transistor (IGBT) are widely
used in the modern power converters.
1)
On-state characteristics
During the on-state interval, the on-state resistance (i.e., rDS_on) of MOSFET and on-
state saturation voltage (i.e., VCE, sat) of IGBT induce forward voltage and thus conduction
losses.
Fig. 1.2 represents the on-state characteristics of typical MOSFET and IGBT
power dissipation and thermal management. According to Fig. 1.2, it can be noted that
a) The on-state current density is compromised by the on-state voltage drop.
b) For a given high on-state current density, IGBT has superior performance than
MOSFET in terms of on-state voltage drop, therefore, conduction loss is lower.
c) For a given current density, the on-state voltage drop VDS_on, thus the on-state
resistance rDS_on, increases significantly with the blocking voltage rating. As
discussed in [22], for high-voltage N channel MOSFET, rDS_on is approximately
given by
Chapter 1-4
rDS _ on
( )
(1.1)
where Vb is the rating of blocking voltage in volts and A is the die area in mm2. It should be
noted that with the introduction of vertical super-junction MOSFET [22] and CoolMOS
technology [23], rDS_on can be reduced significantly, however, only for MOSFET with
voltage ratings up to 800 V.
Fig. 1.2 Comparison of the on-state characteristics of IGBT and MOSFET structures with
different blocking voltage ratings [21].
Chapter 1-5
2)
Switching characteristics
According to the above analysis, IGBT has better performance than MOSFET
regarding the on-state characteristics for high voltage applications. However, the switching
speed of IGBT is normally slower than that of MOSFET, which is mainly due to their turnoff switching characteristics.
It can be
Therefore, MOSFET is
It is more
suitable for high frequency operation, which is crucial to achieve high power density
converters.
Chapter 1-6
Fig. 1.4 Typical turn-off transitions of MOSFET and IGBT with inductive load.
It imposes the specific challenge to select proper switching devices in high-voltage
medium-power converters as the compromised performance between the on-state
characteristics and switching characteristics of both MOSFET and IGBT.
electrolytic capacitors are widely chosen for the capacitor bank because of their high
volumetric efficiency and low cost.
Advances in film capacitor technology in the last two decades are emerging to be
applied for dc-link filtering [26]-[27].
aluminum electrolytic capacitor and power film capacitor for the dc-link. Power film
Chapter 1-7
voltage film capacitors still cannot compete with electrolytic capacitors, due to their
relatively low volumetric efficiency and high cost.
volumetric efficiency
relatively low
voltage ratings
capacitance tolerance
20% (typical)
ripple current
20 mA/ F (typical)
1 A/ F (typical)
ESR**
Low
lifetime
cost
relatively low
In this section, switch pairs, topologies and associated soft-switching schemes for
high voltage applications are evaluated.
1.3.1. Switch Pairs and Their Combinations
A switch pair is composed of two switches connected in series and driven by
complementary gate signals. Fig. 1.5 shows three possible switch pairs using MOSFETs
and IGBTs.
Chapter 1-8
full-bridge (FB) converter [28]-[29] with two switch pairs connected in parallel as shown in
Fig. 1.6(a). Several FB converters can be connected in input-series-output-parallel (ISOP)
to obtain a modular-based converter [30]-[33].
converter [34]-[43] with two switch pairs connected in series so as to withstand high input
voltage as shown in Fig. 1.6(b).
Chapter 1-9
examples, in Cases 2 and 5 listed in Table 1.2, the maximum operating voltage is
determined by the switch with the lower voltage rating in the switch pair. The maximum
limit of the input voltage and the optimal soft-switching scheme for each case are provided.
Table 1.2 Analysis of different combinations of switch pairs.
Combination of switch pairs
(Voltage ratings: MOS-V1, IGBT-V2)
(Assume V1 < V2)
In parallel
(FB)
In series
(TL)
Voltage
Input voltage
Optimal softdistribution
limitations switching scheme* between switch
pairs
Case 1
Two MOS-MOS
V1
ZVS
Case 2
Two MOS-IGBT
V1
ZVZCS
Case 3
Two IGBT-IGBT
V2
ZCS
Case 4
Two MOS-MOS
2V1
ZVS
Case 5
Two MOS-IGBT
2V1
ZVZCS
Case 6
Two IGBT-IGBT
2V2
ZCS
Case 7
IGBT-IGBT
+MOS-MOS
V1+ V2
Hybrid
ZVS-ZCS
Symmetric
Asymmetric
Chapter 1-10
1980s [49]-[52] from the resonant converters to reduce the switching loss and EMI [53][54], allowing the increase of switching frequency [55]. There are three types of softswitching: zero-voltage-switching (ZVS), zero-voltage-zero-current-switching (ZVZCS)
and zero-current-switching (ZCS).
The principle of ZVS is to provide energy to completely discharge and charge the
output parasitic capacitors of switches during commutation transitions. The energy for
achieving ZVS of the lagging switches in phase-shift FB converters is provided by the
leakage inductance of isolation transformer. Therefore, ZVS is only guaranteed above a
certain pre-designed load level. To extend the soft-switching range, additional energy
sources for achieving ZVS of the lagging switches are fulfilled by either linear inductor
[52], saturable inductor [28], coupled inductor [56]-[57], magnetizing inductor [58]-[59] or
output inductor [60]. To reduce parasitic ringing, auxiliary circuits are added in secondaryside [50], [61] or primary-side [52], [62]-[65]. These approaches increase the circuit
complexity, induce additional duty cycle loss and cause undesirable secondary-side ringing.
The magnetizing current of the transformer flows at its maximum value through the
primary switches during freewheeling mode, increasing the conduction loss.
In an isolated ZVZCS phase-shift FB converter, the ZVS of the leading switches is
ensured by energy stored in the output inductor. The ZCS of the lagging switches is
fulfilled by resetting the primary winding current during freewheeling mode. Accordingly,
various kinds of passive circuits or active circuits are proposed in [66]-[76] to assist ZCS, at
Chapter 1-11
the expense of either increasing circuit complexity and/or overvoltage across the
secondary-side rectifier.
Very little research has been devoted to FB ZCS converters: in [77] and [78], ZCS
is obtained in current-driven converters, by using a passive snubber [77], or an active
snubber [78].
snubber formed by a resonant inductance Lr (with the inclusion of the leakage inductance of
the transformer) and a resonant capacitor Cr (with the inclusion of the reflected winding
capacitance). However, ZCS is lost at high input current.
range, the characteristic impedance of the resonant tank has to be decreased, either by
decreasing Lr or increasing Cr. The former way leads to an increase in the current stress on
the primary switches, and the latter one results in an increase of the time duration for
discharging Cr, therefore, the loss of duty-cycle. Voltage-driven FB ZCS converters are
proposed in [79]-[83] by using snubbers in the primary side [79], [81]-[82] or in the
secondary side [80], [83].
Chapter 1-12
regulation ability under light loading condition compared to series type resonant converter
and smaller circulating current than that of parallel one. However, a large variation of the
switching frequency is required from full load to no load when operating above the
resonant frequency. There is still a trade-off between the upper switching frequency and
the circulating current [16] at light loads.
series-resonant converters, which is not desirable for converters employing IGBT with turn
off tail current.
Therefore, ZVS current-fed converters [88]-[91] and ZCS current-fed converters
[77] and [92] with capacitive output filter are proposed as an alternative solution for high
output voltage application. ZCS is preferable for converters employed IGBTs. However,
as discussed in Section 1.3.2, the ZCS load range is compromised by the light load
circulating current, thus, conduction loss in [77] and [92]. In Chapter 2, a current-fed ZCS
FB PWM converter is chosen for converting a 530 V to 15 kV with an adaptive resonant
snubber.
2)
Topologies for high input voltage and low output voltage application
The high input voltage to low load voltage application discussed here is specifically
The
Chapter 1-13
choices for dc-dc converters in terms of the circuit topology, single switch [93]-[94] or
combination of switch pair and soft-switching scheme with respect to various input voltage
and power levels.
In particular, there are two available solutions to convert the 1500 V line to low load
voltages in a single step as presented in the chart of Fig. 1.7.
converter [82]-[83] and [95], in which high-voltage devices are necessary. Switches with
voltage rating of 1.7 kV or 2.5 kV should be used on the primary side.
In [82], a
secondary-side snubber, with one active switch turned on and off twice in one cycle, is
added to assist ZCS of the IGBTs.
doubler rectifier, two active snubbers are needed for ZCS of all four IGBTs [96]. In [83],
two primary-side active snubbers are used to ensure ZCS of the four IGBTs, the auxiliary
switches in the snubber are submitted the same voltage stress as the main switches. The
second solution is a TL converter [97]-[98].
be used for the above specific application. Although ZCS is preferable for IGBTs as stated
above, these TL converters are implemented with ZVS.
In Chapter 3 and Chapter 4, two novel solutions are proposed with multi-level and
three-level (with asymmetric voltage stresses on the two switch pairs) circuit structures,
respectively. Current multiplier and current doubler [99] rectification circuits are applied
respectively to enhance the output current capacity.
Chapter 1-14
Fig. 1.7 Available options on topology, combination of switch pair and soft-switching
scheme for dc-dc power converters with different input voltages and output power levels.
voltage of 400 V, 60 Hz, and further rectified into a dc voltage of 110 V for charging of
backup batteries. The 110 V voltage is further converted to lower voltages for supplying
the low-voltage equipment (which requires input of 24 V, 32 V, 48 V or 64 V [101]). Fig.
1.8 shows the conventional architecture of the electrical system on metro trains.
As
illustrated, the energy supplied to the low voltage equipment goes through multiple power
conversion stages for converting the high voltage of several kilovolts into low voltages,
implying low overall power conversion efficiency. An alternative energy-efficient
approach would be to perform the high-voltage to low-voltage dc-dc conversion in a single-
Chapter 1-15
system level, it is possible to significantly improve the power conversion efficiency and
power density for converters used for on-board low voltage applications.
Fig. 1.8 Typical block diagram of the electrical network on metro trains.
Fig. 1.9 Proposed block diagram of the electrical network on metro trains.
Chapter 1-16
Therefore, it is
control theories to achieve fast dynamic response over wide bandwidth of supply and load
disturbances.
To overcome the limitations of conventional small-signal-based controllers, an
alternative concept is to design controllers directly in time domain to achieve fast dynamic
responses. One major class of them is switching surface control. The concept is to
determine the time sequences to turn on/off switches according to certain constrains,
namely, switching surfaces [103]-[106].
hysteretic control with zero-order switching surface as shown in Fig. 1.10(a)-(b) or slidingmode control (SMC) with first-order switching surface [107]-[116] shown in Fig. 1.10(c).
Chapter 1-17
Chapter 1-18
Fig. 1.10 Switching surface control methods with different switching surfaces.
Chapter 1-19
The hysteretic controller tightly regulates the inductor current at the current
reference. With further extension on regulating the output voltage, the SMC is the popular
choice in boundary control. However, the optimal sliding surface and the stability for fast
dynamic response depend on the supply and load characteristics. It is thus difficult to
design a set of well-defined control parameters for the sliding surface at all operating
points. The control parameters such as the slope of the switching function are sometimes
designed by trial-and-error, start-up profile, switching frequency, etc.
In general, the
converter requires taking several switching actions before settling to the steady-state. The
SMC is sometimes applied to the fast control loop and the output is regulated by a
proportional-integral (PI) controller.
Chapter 1-20
handle these issues, several techniques have been proposed for buck-converter [121]-[123]
to achieve fixed frequency, parameter independent solution or programmed inductor
current.
However, one remaining fundamental issue which poses great challenges is that
Cartesian x-y plane rather than the state plane is proposed and discussed in Chapter 5.
As discussed in Section 1.2.2, the widely used E-Caps suffer from short
lifetime, which will in turn affect the overall reliability of the system.
The replacement of
Chapter 1-21
E-Caps by power film capacitors can reduce the power loss and extend the lifetime,
however, at expense of considerable increase of cost and volume.
Therefore, a practical and feasible approach to deal with the above described issues
is to reduce the required capacitance.
classified as follows:
1)
Performance tradeoff - This simple method allows the dc-link voltage to have large
variation with smaller capacitance. However, such approach is practically less
impressive as the system performance is degraded. It is only suitable for certain
applications, like the ones discussed in [125] and [126]. In [127], a set of procedure
for designing an optimal value of the capacitor bank is discussed.
2)
Chapter 1-22
4)
reduction of the dc-link capacitance. They have been traditionally proposed on the ac side
for current harmonic reduction in distribution systems or power electronic converters [136][147]. There are shunt active filters [140]-[144], series active filters [145]-[147] and hybrid
ones [145]. In [148]-[155], active power filters are applied in high-voltage direct-current
(HVDC) transmission line and other dc distribution systems for harmonic reduction and dc
voltage stabilization. They require an external power source connecting to the input of the
Chapter 1-23
active filters to assist the active power control between the source and load. For the
application of reducing dc-link capacitance in power electronic conversion systems, the
concept of active filters is adopted in [156]-[170]. It is based on connecting an auxiliary
circuit in parallel with the dc-link capacitor as shown in Fig. 1.11(b). The added circuit
serves as an active impedance or energy source. Different methods of implementing the
auxiliary circuit are given.
dissipative resistor. In [161], a relay is placed at the input line and is activated, depending
on the dc-link voltage level, resulting in a stable dc-link voltage, but at the expense of
reducing the input power factor of the entire system. In [156], [160] and [163], an H-bridge
circuit with a current source (inductor) is used to minimize the ripple current of the dc-link
capacitor.
However, the high inductor current stress and high switching frequency
requirement in [163] are the major practical challenges of the method. A current injection
method was applied in [159]-[160], [162] and [164] by a half-bridge structure. In [165][166], a two-switch converter that can operate bi-directionally in both buck and boost
modes is used for the H-bridge front-end and dc current electrical load application.
In
[167], series-connected dual boost converter is as the shunt active filter for a three-phase
diode rectifier front-end conversion system. In [168], the ripple reduction circuit allows an
additional power port for enhancing the dynamic response of the whole system. The
common challenge of all these methods is that the components used in the auxiliary circuit
are under a high voltage stress, which could be as high as the dc-link voltage.
Chapter 1-24
This thesis contains seven chapters. In Chapter 2, the concept of adaptive snubber
energy for ZCS will be presented. The operating principles of the proposed current-fed FB
converter will be described.
determine the dc conversion ratio and the ZVS conditions in an analytical form. The selfbalance property of the voltages across the input capacitors will be described.
A 1500 V /
Chapter 1-25
based on a novel concept, by which the voltage stresses on the series-connected two switch
pairs are asymmetric. The advantages of a TL converter adopted the proposed concept will
be illustrated in terms of utilization of switching devices and load range for soft-switching.
A new concept of hybrid ZVS-ZCS scheme will be proposed. The evaluations on a 2 kW
prototype will be given to verify the theoretical predictions.
In Chapter 5, a uniform second-order switching surface for a fast transient
controller of dc-dc converters will be derived.
implementation will be discussed.
(i.e., boost converter, buck-boost converter, uk converter and SEPIC) will be presented to
verify the universal applicability of the proposed control method. Experimental results on
a 48 V/48 V buck-boost converter prototype will be also analyzed to exhibit the
performance of the controller.
In Chapter 6, a patent-pending technology for reducing dc-link capacitance in
capacitor-supported power electronic systems will be presented. The operation principle
and implementation of the proposed voltage compensator will be discussed. Simulation
and experimental results will be provided to verify the theoretical analysis.
In Chapter 7, conclusions and suggestions for future research on this topic will be
given.
Chapter 2-26
CHAPTER 2
HIGH OUTPUT VOLTAGE ZCS CURRENT-FED FULL-BRIDGE CONVERTER
WITH SELF-ADAPTABLE SOFT-SWITCHING SNUBBER ENERGY
2.1. Introduction
This chapter proposes a snubbering technology having an adaptive snubber energy
control for ZCS of current-fed dc-dc converters.
switched-capacitor circuit in which the charging and discharging processes of the capacitor
are controlled, depending on the loading condition.
The
conduction losses of switching devices are kept minimal while achieving soft-switching.
Based on the concept, a novel soft-switched, current-driven FB converter is
presented. An adaptive ZCS snubber is connected in series with the primary windings of
the isolation transformer. All primary switches are operated with ZCS and the snubber
switches are operated with ZVS.
charged up to the minimum required energy for ZCS of the switches. Thus, less resonant
energy is needed and the currents following through the primary switches never exceed the
input current.
Chapter 2-27
Fig. 2.1 Proposed current-fed full-bridge converter with adaptive ZCS snubber.
The proposed current-fed FB converter is shown in Fig. 2.1. L is the input inductor
to provide an input current source.
circuit and driven by phase-shift PWM signals. Np and Ns are the number of turns of the
primary windings and secondary windings of the transformer Tr, respectively.
leakage inductance of Tr.
Llk is the
connected in series with the primary windings of the isolation transformer. The snubber is
composed of two unidirectional transistors Sa1, Sa2, and one capacitor Cr. A diode bridge
formed by D1-D4 is used for the ac-dc rectification.
output side, which is preferable in high output voltage application. As defined in Fig. 2.1,
Vo is the output voltage, ip is the primary current of Tr, io is the rectified secondary current
before the output capacitor and vCr is the voltage across the snubber capacitor Cr.
Chapter 2-28
Chapter 2-29
Fig. 2.2 shows the timing diagram of the proposed converter in one switching cycle.
The upper two switches (S1 and S2) and the lower two switches (S3 and S4) are driven
complementarily, respectively. The driving signals for S1 and S4 have a phase difference of
180. The steady-state operations are cyclically divided into 12 modes and are symmetric
in the first and the second half cycles. Therefore, the following analysis is given for the
first half cycle.
For the sake of simplicity, the effect of the magnetizing inductance (3.9
Chapter 2-30
(d) Mode 3
(e) Mode 4
Chapter 2-31
(f) Mode 5
(g) Mode 6
Fig. 2.3 Operation modes of the current-fed FB converter (first half cycle).
Mode 1 [t0, t1] [Fig. 2.3(b)]: Before t0, the circuit topology is shown in Fig. 2.3(a).
The input energy is transferred to the load via diodes D2 and D3. At t0, a new cycle begins
with Sa1 turning off with ZVS.
i p (t ) Iin
vCr (t )
I in
t t0
Cr
(2.1a)
(2.1b)
Chapter 2-32
(2.1c)
I in
t1 t0
Cr
(2.1d)
i p (t )I in cos t t1
where Z p Llk Cr , 1
VCr nVo
sin t t1
Zp
(2.2a)
transformer.
The snubber capacitor voltage vCr is given by
(2.2b)
The topology ends when the primary current drops to zero, giving the duration of
this stage
t12
tan 1
I in Z p
VCr nVo
(2.2c)
Chapter 2-33
vCr (t2 )
VCr nVo I in Z p
2
nVo
(2.2d)
According to (2.2a), with a higher Iin, one needs a larger VCr to bring the primary
current to zero. When Iin is low, the required value of VCr is also low. Consequently, the
durations of the first and second switching intervals are only slightly dependent on the
value of Iin, no loss of duty-cycle arises from getting such a large ZCS range.
Mode 3 [t2, t3] [Fig. 2.3(d)]: At t2, ip reaches zero, S4 is switched off with ZCS. As
a result, the secondary current reaches zero, and the rectifier diodes turn-off naturally
(ZCS). The load voltage is assured by the output capacitor (freewheeling stage)
i p (t ) 0
(2.3a)
(2.3b)
(2.3c)
Mode 4 [t3, t4] [Fig. 2.3(e)]: The PWM dictates the instant t3 when S2 is turned on
with ZCS.
increases in absolute value, the presence of Llk in the ip path assures that the rectifier diodes
D1 and D4 are turned on with ZCS. The current through S1, iS 1 (t ) I in i p (t ) , decreases
i p (t )
(2.4a)
(2.4b)
The stage ends when the primary current in absolute value reaches the input current,
giving the duration of this topology
Chapter 2-34
t34
sin 1
I in Z p
VCrc nVo
I in Z p 2nVo
2
(2.4c)
(2.4d)
Mode 5 [t4, t5] [Fig. 2.3(f)]: At t4, ip reaches -Iin, the current through S1 drops to zero,
so S1 can be turned-off with ZCS. The energy is transferred from the line to the load. Cr is
discharged to the load, thus recuperating its energy.
i p (t ) Iin
vCr (t ) nVo
I in
t t4
Cr
(2.5a)
(2.5b)
t45
Cr nVo
I in
(2.5c)
Mode 6 [t5, t6] [Fig. 2.3(g)]: At t5, Sa2 turns on with ZVS, and the circuit operates in
this transfer-energy mode until a new half-cycle is commenced by turning off Sa2.
i p (t ) I in
(2.6a)
vCr (t ) 0
(2.6a)
It can be noted that, in neither stage, the primary current overpasses the input
current, keeping thus the conduction losses in the primary switches at their minimum value.
S1 is turned on with ZCS at t9 and is turned off with both ZCS and ZVS at t4. S3 is turned
on and off with ZCS at t1 and t8, respectively. The operations of S2 and S4 are the same as
those of S1 and S3, respectively. Thus, all of the four switches S1- S4 are switched with ZCS.
Chapter 2-35
VCrc
Z p 2nVo I in Z p nVo
2
in
(2.7)
It can be noted that ip in (2.4a) has to reach -Iin. It is equivalent to satisfying the
following condition
1
1
2
Cr > vCr (t3 ) nVo @ t Llk I in 2
2
2
(2.8)
That is, it requires sufficient energy in Cr for reducing the primary current from 0 to -Iin.
It can be seen from (2.7) that for a given converter (with certain values of Zp, n, Vo),
VCrc depends solely on the value of Iin, i.e. the resonant energy used to achieve ZCS is selfadaptable. As explained in Section 2.5, Iin is sensed, and the minimum necessary capacitor
voltage for ensuring ZCS at the measured value of the input current, VCrc , is calculated by
(2.7). In the first stage, Cr is charged. When the sensed value of vCr reaches the calculated
value VCrc , the switch S3 (respectively S4 in the second half-cycle) is turned on, marking the
end of this switching stage (i.e., determining the instant t1 in the timing diagram).
between S1 and S3 in the first half-cycle, and S2 and S4 in the second half-cycle. By
Chapter 2-36
assimilating the shift angle with a duty-cycle D, and operating as the boost converter where
the on-topology is characterized by the charging of the input inductor, one can define
(2.9)
(2.10)
tk
where ISk ip (t ) dt .
tk 1
By taking into account that t23DTs t12 t34 , t56 Ts / 2 DTs t01 t45 and using
(2.1a 2.5a), (2.1c 2.5c), (2.7) and (2.9), one gets
IS1 CrVCr
IS2 Cr Iin Z p nVo VCr
IS3 0
IS4 Cr Iin Z p
IS5 Cr nVo
IS6
1 2 D Ts I
2
in
CrVCr Cr nVo
By inserting the above formulas of ISk (k = 1,,6) in (2.10), the dc conversion ratio,
M, results
Chapter 2-37
Vo
1
Vin
Cr 2nVo 2 I in Z p
n 1 2 D
2
2
Z p 2nVo I in Z p
I inTs
in
(2.11)
Comparing it with the conversion ratio formula for a boost hard-switching FB:
M 1 / [ n (1 2 D )] it results that the intervals for forming ZCS lead to a loss of regulation
range (i.e. DTs cannot be reduced to zero, if so required for regulation purpose, but its lower
limit is t12+t34). This loss of regulation is expressed by Dloss as follows
Dloss
Cr 2nVo 2 I in Z p
Z p 2nVo I in Z p
2
in
(2.12)
I inTs
Fig. 2.4 Duty- cycle loss versus normalized input current under different snubber capacitor
values (Vo = 15 kV, n = 1/20, Llk = 3.6 H and fs = 20 kHz).
Chapter 2-38
Dloss is represented versus the normalized input current in Fig. 2.4 (the input current
is normalized with respect to its nominal value Iin,rated ).
with the value of Cr, but it always has a very small value.
Chapter 2-39
Fig. 2.6 Duration of charging and discharging intervals of the snubber capacitor versus Cr
under different Llk values (Vo = 15 kV, Vin = 0.8 Vin,rated ,and n = 1/20).
Chapter 2-40
1 2 D Ts
(2.13)
For ensuring the existence of the soft-switching assisting intervals (Modes 1, 2, 4, 5), the
boundary on the duty-cycle are given by the inequality
t12 t34
1 t t
D 01 45
Ts
Ts
2
(2.14)
By substituting (2.1c), (2.2c), (2.4c), (2.5c) and (2.7), the above inequality becomes
1
( tan 1
Ts 2
1 Cr
)D
2
2
2
Iin Z p 2nVo Iin Z p
I in Z p
Z p 2nVo I in Z p
2
in
I inTs
(2.15)
Fig. 2.7(a) gives the operating limits of the duty cycle versus the normalized output
current. The intersection between Dmin and Dmax represents the minimum load current for
which soft-switching is achieved. For the considered design specifications (i.e., Vo = 15 kV,
n = 1/20, Llk = 3.6 H, Cr = 0.022 F and fs = 20 kHz), the transistors can be soft-switched
for a load range starting from 20%. Clearly, ZCS can still be maintained at a heavy current.
In Fig. 2.7(b), the voltage on the resonant capacitor at instant t2, vCr(t2), is also given versus
the normalized load current within the designed input voltage range.
It can be noticed
that, except at the maximum load current, this voltage is always smaller than vCr,max,
confirming the self-adaptable characteristics of the proposed soft-switching solution, i.e. at
each actual value of the load current, the snubber will use the minimum
resonant energy to get ZCS for the primary switches.
necessary
Chapter 2-41
(a)
(b)
Fig. 2.7 (a) Lower and upper boundaries of the duty-cycle for soft-switching versus
normalized load current; (b) Adaptive snubber capacitor voltage vCr(t2) versus normalized
load current (Vo = 15 kV, n = 1/20, Llk = 3.6 H, Cr = 0.022 F and fs = 20 kHz).
Chapter 2-42
Deff D
I in Z p
1 1
1
Ts 2 I in Z p 2nVo
(2.16)
by applying a Taylor expansion of (2.12) and retaining the first three terms.
By superposing ac small-signal perturbations vin , iin , vo , io and d on the values of the
input voltage Vin, input current Iin, output voltage Vo, output current Io, and duty-cycle D,
respectively, after a few manipulations in (2.16), one can find the ac small-signal
perturbation in the effective duty-cycle as follows
deff d
nLlkVo
Ts 2nVo I in Z p
2 in
nLlk I in
Ts 2nVo I in Z p
nLlkVo
Ts 2nVo I in Z p
vo d di dv
, Qv
(2.17)
nLlk I in
Ts 2nVo I in Z p
Chapter 2-43
According to Fig. 2.9, the ac small-signal transfer functions of the power stage are
derived as follows
Gvg ( s)
Gig ( s)
v o ( s)
vin ( s)
d ( s ) io ( s ) 0
LCs L RL L C s 2 2 RL
(2.18)
iin ( s )
Cs 1 RL
vin ( s) d ( s ) io ( s ) 0 LCs L RL L C s 2 2 RL
(2.19)
Chapter 2-44
Gid ( s)
i in ( s)
d ( s)
2n CVo s I in Vo Vo RL
LCs L RL L C s 2 2 RL
(2.20)
Gvd ( s )
2n I in Vo LI in s
v o ( s )
d ( s ) vin io ( s ) 0 LCs 2 L RL L C s 2 2 RL
(2.21)
Ai ( s )
Zo ( s)-
v io ( s ) 0
in
iin ( s)
io ( s )
vo ( s)
io( s)
vin ( s ) d ( s ) 0
vin ( s ) d ( s ) 0
LCs L RL L C s 2 2 RL
Ls
LCs L RL L C s 2 2 RL
2
(2.22)
(2.23)
Chapter 2-45
Fig. 2.11 Bode diagram of Gid(s) (Vo = 15 kV, n = 1/20, Llk = 3.6 H, Cr = 0.022 F, RL
= 45 k and fs = 20 kHz).
Chapter 2-46
Fig. 2.12 Bode diagram of voltage-loop gain Tv ( s ) (Vo = 15 kV, n = 1/20, Llk = 3.6 H, Cr =
0.022 F, RL = 45 k and fs = 20 kHz).
According to Fig. 2.10, the current loop gain, Ti (s), results in
Ti ( s )
(2.24)
A PI controller is used for the current loop compensator. Thus, Gcc (s) can be expressed as
Gcc ( s )
K ip
K ii
s
(2.25)
Gid(s) rather than Ti(s) itself is measured in the experimental prototype to determine the
parameters Kip and Kii. Fig. 2.11 presents the Bode diagram of Gid(s) which provides the
information for the PI controller design.
1.25104, respectively.
The voltage loop gain, Tv, results in
The values chosen for Kip and Kii are 6.29 and
Chapter 2-47
Tv ( s)
(2.26)
A PI controller is used for the voltage loop compensator. Thus, Gvc(s) can be expressed as
Gvc ( s)
with Kvp = 39.45, Kvi = 3.72104.
K vp
K vi
s
(2.27)
frequencies to about 50 dB. The designed cross frequency of the voltage-loop is 842.4 Hz.
The phase margin is 65o and the gain margin is 14.5 dB.
Gvc(s) and Gcc(s) are transferred into the difference equation forms of
vn
vn 1 6.915(en en 1 ) 1.25en
(2.28)
vnc
(2.29)
Chapter 2-48
2) The ratings of the switches are chosen by considering the voltage and current
stresses. The voltage stress of the main switches is Iin,maxZp + 2nVo and that of the auxiliary
switches is Iin,maxZp + nVo. The current stress of all switches is Iin,max.
3) The value of the input inductor is chosen to limit the input current ripple 'iL at
2.5 % from its nominal value
L t nD 1 2 D TsVo 'iL
(2.30)
4) The value of the output capacitor Co is chosen to limit the voltage ripple 'Vo at 0.6%
of Vo.
Co ! 2Dmax IoTS / 'Vo
(2.31)
5) The output diodes are chosen by considering the voltage and current stresses.
The voltage stress and current stress of the diode are Vo and Po,max / Vo, respectively.
The four main switches are driven by phase-shift PWM signals with adaptable
durations of charging and discharging intervals of the snubber capacitor. The driven
signals of the two auxiliary switches are generated by detecting the zero-cross point of the
voltage of the snubber capacitor.
The component values are listed in Table 2.1. The switches used in the prototype
are IGBT modules (having anti-parallel diodes) connected in series with diodes. The
function is to perform unidirectional current flow operation.
the 5 kW experimental prototype.
Chapter 2-49
Table 2.1 Component values used in the analysis and experimental prototype.
Component
Value
S 1 ~ S4
Sa1 ~ Sa2
IGBT driver
2SD106AI-17
30 kV / 3 A
Cr
0.022 PF
Llk
3.6 PH
Co
0.2 PF / 30 kV
Transformer core
Ferrite EE160
15: 300
1:5000
Chapter 2-50
Fig. 2.14 Simplified software flowchart of the proposed control strategy ( is a small
numerical value).
The control system is implemented by a Digital Signal Processor (DSP)
TMS320F28335 with a soft-start scheme.
and output voltage Vo are sampled to provide the necessary information for the currentmode control and to calculate the minimum snubber voltage VCr for realizing ZCS using
(2.7). The instantaneous value of the snubber capacitor voltage vCr is sensed and compared
with the calculated value VCr .
reaches the calculated value, S3 (S4) is turned on, thus practically determining the instant t1
(t7) as a function of the input current/load.
snubber is the minimum one necessary to get ZCS for the actual input/load current.
The
maximum vCr(t1) for getting ZCS is reached at the upper limit of the range of the input
Chapter 2-51
current.
Fig. 2.14 presents the simplified software flowchart of the proposed control
strategy.
The experimental steady-state voltage and current waveforms of the primary
switches S1 and S3, and auxiliary switch Sa1 under full load, and at 25% loading condition,
are given in Fig. 2.15 and Fig. 2.16, respectively.
primary switches turn-on/off with ZCS, and the auxiliary switch turns-on/off with ZVS.
At a reduced load, soft switching is still maintained.
parasitic capacitance in parallel with the isolation transformer, the voltage acorss the
primary-side windings can not instantly increase and decrease. Therefore, the captured
waveforms of VS1 in Fig. 2.15(a) and Fig. 2.16(a) are not exactly the same as the
theorectical one during t8-t9 shown in Fig. 2.2.
(a) Waveforms of vS1 and iS1 (vS1: 500 V/div, iS1: 5 A/div and timebase: 5 s/div).
Chapter 2-52
(b) X-Y plot of vS1 and iS1 (vS1: 500 V/div, iS1: 5 A/div and timebase: 5 s/div).
(c) Waveforms of vS3 and iS3 (vS3: 500 V/div, iS3: 5 A/div and timebase: 5 s/div).
Chapter 2-53
(d) X-Y plot of vS3 and iS3 (vS3: 500 V/div, iS3: 5 A/div and timebase: 5 s/div).
(e) Waveforms of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 5 A/div and timebase: 5 s/div).
Chapter 2-54
(f) X-Y plot of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 5 A/div and timebase: 5 s/div).
Fig. 2.15 Switching waveforms of S1, S3, and Sa1 at full load.
(a) Waveforms of vS1 and iS1 (vS1: 500 V/div, iS1: 2.5 A/div and timebase: 5 s/div).
Chapter 2-55
(b) X-Y plot of vS1 and iS1 (vS1: 500 V/div, iS1: 2.5 A/div and timebase: 5 s/div).
(c) Waveforms of vS3 and iS3 (vS3: 500 V/div, iS3: 2.5 A/div and timebase: 5 s/div).
Chapter 2-56
(d) X-Y plot of vS3 and iS3 (vS3: 500 V/div, iS3: 2.5 A/div and timebase: 5 s/div).
(e) Waveforms of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 2.5 A/div and timebase: 5 s/div).
Chapter 2-57
(f) X-Y plot of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 2.5 A/div and timebase: 5 s/div).
Fig. 2.16 Switching waveforms of S1, S3, and Sa1 at 25% load.
The experimental Bode diagrams of Gid(s) and Tv(s) are given in Fig. 2.11 and Fig.
2.12, respectively, in order to compare the experimental values with the calculated ones.
The experimental results are in full agreement with the theoretical expectations.
The Bode
plot of the voltage loop gain proves a good stability, and good phase and gain margins, of
62 and 17 dB, respectively.
Fig. 2.17 presents the snubber capacitor voltage vCr(t2) (in percentage of vCr,max)
under different line / loading condition (a reduced input voltage attracts an increased input
current with a constant output power).
conditions, compared with its upper value reached at maximum input/load current.
proves the adaptive characteristic of the soft-switching solution proposed.
This
Chapter 2-58
Fig. 2.17 Measured vCr(t2) (in percentage of vCr,max) under different line / loading condition.
The experimental efficiency versus the load is given in Table 2.2. The efficiencies
are 93% at full load and 90.2% at 25% load. A comparative study into the efficiencies of
the converter at the nominal power with hard-switching and with an un-optimized ZCS
scheme (i.e., the designed values of Cr and Lr are not optimized and the energy provided to
achieve the ZCS is not minimum) has been performed. With the optimized RCD snubber in
the hard-switched converter, the conversion efficiency is 83%. With the un-optimized ZCS
scheme, the conversion efficiency is 89%, which is higher than the hard-switched
converter. Nevertheless, the efficiency is less than the one with the proposed self-adaptable
soft-switching snubber energy scheme. This confirms the advantages of the proposed
method.
Chapter 2-59
Table 2.2 Experimental efficiency versus load (Vin = 530 V, Io,rated = 1/3A).
Load (percentage)
Efficiency
25%
90.2%
50%
91.3%
100%
93%
The primary
switches are operated with ZCS, allowing the use of IGBT. The auxiliary switches are
operated with ZVS. The rectifier diodes are operated with ZCS naturally. The maximum
current stress on all the switches is the input current. Soft switching is achieved over a very
wide line and load range. The main characteristic of the solution is its self-adaptability: the
snubber energy necessary to get ZCS for the main switches is adaptable and is dependent
on the value of the primary current.
maximum load current and lower limit of input voltage range), the snubber capacitor will
be charged to the maximum level. For the other value of the input current, less snubber
energy is used. It can avoid unnecessary energy circulation, and thus reduce conduction
loss. In each cycle, all the energy accumulated in the snubber capacitor for soft switching
is recuperated to the load. A current-controlled feedback has been implemented with a
DSP. Experimental results measured on a 5 kW, 530 V/15 kV prototype confirm the
advantages of the proposed converter.
Chapter 3-60
CHAPTER 3
HIGH INPUT VOLTAGE MULTI-LEVEL MULTI-PHASE DC-DC CONVERTER
3.1. Introduction
This chapter presents a generalized multi-level multi-phase circuit structure for high
input voltage to low load voltage applications. The proposed structure is formed by n
switch pairs on the primary side, an n-phase isolation transformer with the primary
windings connected to dc-blocking capacitors, and an n-phase current multiplier on the
output side. The switching patterns applied to the switch pairs have a phase difference of
360 n , and the output inductor currents are interleaved correspondingly, making
necessary a smaller output filter. With input voltage Vin and load current Io, the converter
features Vin /n voltage stress on the primary-side switches, and Io /n current stress on the
secondary-side inductors and diodes. The primary-side switches are commutated with ZVS.
The proposed circuit structure is especially suitable for generating low voltages for
the on-board applications of metro trains from the widely used 1.5 kV or 3 kV dc line in a
single step. Moreover, as the switching devices on the primary side withstand a fraction of
the input voltage only, the most popularly chosen 500/600 V MOSFETs can be used in the
proposed circuit with several kilovolts supply voltage, allowing for a higher operation
frequency and lower conduction losses.
A 1500/48 V, 2 kW prototype with four switch pairs has been designed,
implemented and evaluated.
and low voltage stress of the primary-side switches, and low current flowing through the
rectifiers diodes and inductors.
Chapter 3-61
Fig. 3.1 General structure of the proposed multi-level multi-phase dc-dc converter.
Fig. 3.2 Circuit structure of the (k-1)-th and k-th switch pairs and rectifier branches.
The generalized structure of the proposed converter is shown in Fig. 3.1. It is
formed by n switch pairs on the primary side and an n-phase isolation transformer with
Chapter 3-62
turns-ratio m. The primary windings are connected to the switch pairs with each winding
having a series-connected dc-blocking capacitor, while the secondary windings are
connected to an n-phase rectifier. The dc-blocking capacitors have the same value. There
are n dc-link capacitors C1, C2, , Cn of the same capacitance to split equally the input
voltage Vin. Each switch pair SPk is connected across a dc-link capacitor Ck (k = 1, 2, , n).
The structure of the (k-1)-th and k-th switch pairs and associated rectifier branches is shown
in Fig. 3.2. The dc-blocking capacitors connected to the primary windings are CW1, CW2, ,
CWn. Each switch pair contains two switching devices, SkU and SkD (with the built-in diodecapacitor pairs DkU-CkU and DkD-CkD) operated in anti-phase. The switching patterns applied
to the two adjacent switch pairs have a phase difference of 360 n . The output current is
shared by n identical parallel diode-inductor branches D1-Lf1, D2-Lf2, and Dn-Lfn to reduce
the current stress of the inductors to one-nth of the load current.
Chapter 3-63
(b) Detailed timing diagram of the k-th switch pair in the k-th interval of Ts.
Fig. 3.3 Operation timing diagram of the proposed converter.
Chapter 3-64
The output voltage is regulated by varying the duty cycle, the same in each switch
pair.
Fig. 3.3(a) gives the timing diagram of the proposed converter in one switching cycle
and Fig. 3.3(b) presents the detailed operation timing diagram of the k-th switch pair in the
k-th interval Ts /n.
The duty cycle D is defined by the on-time of upper switch SkU over the
total duration of the k-th interval, Ts /n. A dead time is added for soft-switching transitions.
The operation modes for the switch pair SPk are theoretically analyzed based on the
following assumptions: a) the equivalent parasitic capacitors paralleled with each MOSFET
are of the same value Cs, b) the input voltage is shared evenly by the n input capacitors (this
will be proved in Section 3.3), and c) the leakage inductances of each transformer winding
have an identical value of Llk. The status of the other switch pairs keeps unchanged during
the discussed time interval. vWx denotes the voltage on the primary winding Wx, vwx denotes
the voltage across the secondary winding wx, iWx denotes the primary current flowing
through Wx, ipx denotes the primary-side current circulating through the switches, or their
parasitic capacitances, of switch pair SPx, and iDx is the current flowing through diode Dx.
During the considered k-th interval: [tk0, tk0+Ts /n], with the exception for the switches in the
pair SPk, all the other switches do not change their status: all the upper switches are in the
off-state and all the lower switches are in the on-state.
During the
Chapter 3-65
Chapter 3-66
Chapter 3-67
The converter is in a freewheeling mode. The values of the currents before tk0 will be
proven in Section 3.3.4. They are iW(k-1)(tk0) = (n-1) io /(mn2), iWk(tk0) = -io /(mn2), iWx (x =1,
2, ,n, x k-1, k) = -io /(mn2), iD(k-1)(tk0) = 0, iDk(tk0) = 2io /n, iD(k+1)(tk0) = io /n, iDx (x =
1,2, ,n, x k-1,k, k+1) = io /n. The voltages across the primary windings at tk0 are zero.
At tk0, SkD is switched off with ZVS due to the presence of CkD.
CkU is discharged
and CkD is charged in a resonant manner, providing the ZVS condition for SkU turn on at tk1.
In this mode, the voltage across CkD,vCkD, increases from 0 to Vin /n, and the voltage on CkU,
vCkU, decreases from Vin /n to 0. It can be assumed that the voltage across the dc-blocking
capacitor CW(k-1) keeps constant within one steady-state cycle with value of Vin /n (this will
be proved in Section 3.3.3).
loop formed by S(k-1)D in on-state, CW(k-1), CkU and primary winding Wk-1, it results that vW(k-1)
goes from a zero value to a negative one (-Vin /n). Similarly, by writing a KVL equation in
Chapter 3-68
the following loop, formed by CkD, Ck+1, CWk and primary winding Wk, it results that vWk
increases from zero to a positive value Vin /n. Therefore
i pk (t ) i pk (tk 0 ) cos(t )
vCkU (t )
i0
cos(t )
mn
(3.1)
Vin
i
Llk
o
sin t
n 2mn Cs
(3.2)
io
Llk
sin t
2mn Cs
(3.3)
vCkD (t )
io
Llk
sin t
2mn Cs
(3.4)
vW ( k 1) (t ) vCkU (t ) VCW ( k 1)
io
Llk
sin t
2mn Cs
(3.5)
iW ( k 1) (t ) iW ( k 1) (tk 0 )
i
i
1
vWk (t ) dt o 2 o 1 cos t
Llk
mn
2mn
(3.6)
n 1 io io 1 cos t
1
vW ( k 1) (t )dt
Llk
mn2
2mn
(3.7)
where 1 Llk Cs .
Taking into account that iDx= iLfx - isecx (x = 1, 2, , n) and that the inductor currents
keep their values at the transition instant, it results
iDk (t ) iLfk (t ) m iWk (t ) iW ( k 1) (t )
io
1 cos t
n
iD ( k 1) (t ) iLf ( k 1) (t ) m iW ( k 1) (t ) iW ( k 2) (t )
iD ( k 1) (t ) iLf ( k 1) (t ) m iW ( k 1) (t ) iWk (t )
io
i
1 cos(t ) o
n
2n
io
i
1 cos(t ) o
2n
n
(3.8)
(3.9)
(3.10)
Chapter 3-69
Diode Dk-1, which is off in the previous Ts /n period, starts conducting because the
primary-side current ip(k-1) becomes smaller than the corresponding reflected output inductor
current iLf(k-1), indicating the transition from an energy transfer mode to a freewheeling
mode of this rectifier branch.
During the first mode, all the diodes are on. Therefore, the converter is still in the
freewheeling mode. This mode ends when vCkD reaches Vin /n and vCkU decreases to zero.
From (3.2), the duration of this mode is given by
tk 01 tk1 tk 0
2mVin
sin 1
i L C
o lk s
1
(3.11)
Mode k_2 [tk1, tk2]: As vCkU (tk1) = 0, DkU conducts naturally. After a while, SkU turns
on with ZVS. The primary-side current ipk increases linearly, remaining less than the
reflected output inductor current iLfk. Therefore, the converter is still in the freewheeling
stage. According to Fig. 3.4(c)
(3.12)
vW ( k 1) (t ) VCW ( k 1) Vin / n
(3.13)
iW ( k 1) (t ) iW ( k 1) (t1 )
i
V
1
vWk (t )dt o 2 in t
Llk
mn nLlk
(3.14)
n 1 io Vin t
1
vW ( k 1) (t )dt
Llk
mn2
nLlk
(3.15)
i pk (t ) iWk (t ) iW ( k 1) (t )
io 2Vin
t
mn nLlk
i p ( k 1) (t ) iW ( k 1) (t ) iW ( k 2) (t )
io
V
in t
mn nLlk
(3.16)
(3.17)
Chapter 3-70
i p( k 1) (t ) iW ( k 1) (t ) iWk (t )
iDk (t ) iLfk (t ) mi pk (t )
Vin
t
nLlk
io
2i 2mVin
1 cos t o
t
n
n
nLlk
(3.19)
mVin
t
nLlk
(3.20)
io mVin
t
n nLlk
(3.21)
iD ( k 1) (t ) iLf ( k 1) (t ) mi p ( k 1) (t )
iD ( k 1) (t ) iLf ( k 1) (t ) mi p ( k 1) (t )
(3.18)
During this mode, the leakage inductance of the winding Wk is charged. The mode
ends when ipk reaches the reflected secondary-side current io /(mn), indicating the end of the
freewheeling stage.
Vin /n, while the voltage across the corresponding secondary winding wk is zero (the
secondary side is still in freewheeling mode, even if the primary-side switch is turned on
with the purpose of starting the transfer of energy. This phenomenon is typical for ZVS in
FB converters), resulting in a duty cycle loss.
interval is given by
tk 12 tk 2 tk 1
io Llk
mVin
(3.22)
At the end of the second mode, Dk turns off with ZCS according to (3.19) and (3.22).
At the instant tk2, according to (3.14)-(3.21), the values of the currents are: iWk(tk2) = (n-1)io
/(mn2), iW(k-1)(tk2) = -io /(mn2), ipk(tk2) = io /(mn), ip(k-1)(tk2) = 0, ip(k+1)(tk2) = -io /(mn), iDk(tk2) =
0, iD(k-1)(tk2) = io /n, and iD(k+1)(tk2) = 2io /n.
Mode k_3 [tk2, tk3]: The converter enters the energy-transfer stage. The voltages
across primary windings vWk and vW(k-1) are Vin /n and -Vin /n, respectively. In the secondary
side, the winding voltages vwk and vw(k-1) become the reflected voltage values of associated
Chapter 3-71
primary windings: Vin /(mn) and -Vin /(mn), respectively. The currents on both primary and
secondary sides are constant, by assuming that the current variations in the output inductors
are negligible.
Mode k_4 [tk3, tk4]: According to the controlled PWM signal, SkU is turned-off at tk3
with ZVS due to the parallel capacitance across the switch. The converter is commutated
from the energy-transfer stage to the freewheeling stage. CkU and CkD are charged and
discharged respectively by ipk /2
io
1
i pk (t )dt
t
2Cs
2mnCs
(3.23)
Vin
V
io
1
i pk (t )dt in
t
n 2Cs
n 2mnCs
(3.24)
vCkU (t )
vCkD (t )
vW ( k 1) (t ) vCkU (t ) VCW ( k 1)
Vin
io
t
n 2mnCs
Vin
io
t
n 2mnCs
(3.25)
(3.26)
This mode ends when CkD is fully discharged. According to (3.24), the duration is
tk 34 tk 4 tk 3
2mVin Cs
io
(3.27)
Mode k_5 [tk4, tk5]: At tk4, the body diode of SkD conducts naturally. Therefore, SkD
can be turned on with ZVS subsequently. From KVL written in the same loops as in the
first Mode, it results that the voltages across primary-side and secondary-side windings are
zero and no energy is transferred from the primary-side to secondary-side. The converter
operates in a new freewheeling stage.
values as the ones calculated at the instant tk2 during the third, fourth and fifth modes.
Therefore,
Chapter 3-72
iWk (t )
n 1 io , i
(t )
n 1 io ,
iwx (t )
iwk (t )
i pk (t )
mn
Wx
io
, ( x 1, 2, , n, x k )
mn 2
(3.28)
io
,( x 1, 2, n, x k )
n2
(3.29)
io
i
, i p ( k 1) (t ) o , i px (t ) 0,( x 1, 2, n, x k , k 1)
mn
mn
(3.30)
io
i
, isec ( k 1) (t ) o , isecx (t ) 0,( x 1, 2, n, x k , k 1)
n
n
(3.31)
iseck (t )
iDk (t ) 0, iD ( k 1) (t )
2io
i
, iDx (t ) o , ( x 1, 2, n, x k , k 1)
n
n
(3.32)
For the other n-1 Ts /n intervals in Fig. 3.3(a), the converter operates in a similar
manner.
tk 3
tk 2
Vin
V i DT
T
i pk (t ) dt in o s tk 01 tk12 Voio s
n
n mn n
n
(3.33)
tk01 is very short and thus negligible compared to tk12. Therefore, according to (3.22) and
(3.33), the conversion ratio M and duty cycle loss Dloss are given by
Vo
ni L
1
D o lk
2
Vin mn
mVinTs
(3.34)
Chapter 3-73
Dloss
nio Llk
mVinTs
(3.35)
1 io Llk 1 Vin
2Cs
2 mn 2 2 n
(3.36)
Moreover, the durations of the left and right dead time between the two PWM
signals of each switch pair should be long enough to fully discharge the parasitic capacitor
voltage
tdl tk 01
sin 1
tdr tk 34
2mVin
io Llk Cs
2mVin Cs
io
(3.37)
(3.38)
where tdl and tdr are the dead time of left and right sides respectively.
Chapter 3-74
implying an equality between the voltages on capacitors Ck and CW(k-1). In case that a
perturbation occurs, the current through the loop will equalize the two capacitor voltages.
VCW k 1 Vink
(3.39)
Fig. 3.5 Voltage loop during the freewheeling stage of k-th switch pair.
In practice, the voltage across the dc-blocking capacitor CW(k-1) is relatively constant
over one switching cycle. From KVL written in a loop formed by C(k-1)D, CkU, CW(k-1) and
Wk-1 in Fig. 3.2, as the winding average voltage is zero in a steady-state cycle, it results that
VCW ( k 1) vCW ( k 1) vCkU vC k 1 D , where vCkU and vC k 1 D represent the average value over
a cycle. Referring to Fig. 3.3(b), the average voltage vCkU in one cycle is given by
Chapter 3-75
vCkU
Ts tk 0
tk 0
vCkU (t )dt
Ts
tk 1
tk 0
tk 1
tk 0
tk 2
tk 3
tk 4
Ts tk 0
tk 1
tk 2
tk 3
tk 4
vCkU (t )dt 0 0
tk 4
tk 3
Ts
Ts
vCkU (t ) dt Ts Dk tk 34 Vink
n
Ts
vCkU (t ) dt
(3.40)
where Dk is the duty cycle of switch pair SPk. In Mode k_1, as the duration tk01 is very
short, sin t t , (3.2), (3.11), (3.23), (3.27), (3.40) give
D
vCkU 1 k
n
Vink
(3.41)
Dk 1
V
n in k 1
(k 1)
(3.42)
1
Dk 1Vin k 1 DkVink
n
(k 1)
(3.43)
Vin ( k 1)
Dk
(k 1)
(3.44)
A simple control scheme with only one voltage loop is configured for the proposed
converter. A pair of PWM signals is generated and then shifted by times of 360 n to drive
other switch pairs. Therefore, by neglecting tiny differences that could appear in the shifting
process, the duty cycles of the generated PWM driving signals are the same. Duty cycle
imbalances caused by the mismatched driver dead time and MOSFET switching
characteristics can be removed by system calibration [170], implying a negligible difference
Chapter 3-76
between Dk and Dk-1. As a result, regardless of the capacitors values, the voltage distribution
on each input capacitor will reach parity after a few switching cycles from start-up or other
dynamic perturbations, except for no load condition. According to (3.39), it implies that the
voltage across the dc-blocking capacitor CW(k-1) is equal to Vin/ n.
w 2,2
w1,2
Lf 2
o
(3.45)
where iwj,k denotes the current through the secondary-side winding wj in the k-th energy
transfer stage.
It can be observed from Fig. 3.3(b) that a winding current changes its value only
two times in a steady-cycle Ts. Such a change can take place only in the first two operation
modes after the transition from a Ts /n interval to the next Ts /n interval. For example, iwk,
which is -io /n2 before the beginning of the k-th interval, will change to (n-1)io /n2 during the
first two modes of the k-th interval and will change again to -io /n2 after the transition to the
(k+1)-th interval. Therefore, during the transition from the k-th energy-transfer stage to
(k+1)-th energy-transfer stage, the currents in the corresponding two adjacent windings wk
Chapter 3-77
and wk+1 decrease and increase respectively by the same amount of current defined as i ,
and those in other secondary windings keep constant. It can be shown that
iw1,1 iw1,n i, iw 2,1 iw 2,n , , iw ( n 1),1 iw( n 1),n , iwn ,1 iwn ,n i
iw1, n iw1,( n 1) , , iw ( n 2),n iw ( n 2),n 1 , iw( n 1),n iw( n 1),n 1 i, iwn ,n iwn , n 1 i
(3.46)
(3.47)
n 1 io ,
n
iwx , x
io
n2
( x 1,2, , n, and x k )
(3.48)
n 1 io ,
mn
iWx , x
io
mn 2
( x 1,2, , n, and x k )
(3.49)
n 1 io
n2
io
( x 1,2, , n, and x k 1)
n2
(3.50)
(3.51)
Based on (3.50)-(3.51), the initial currents flowing through the primary windings
and rectification diodes of the analyzed k-th interval in Section 3.2 are given by the
following equations (3.52) and (3.53), respectively.
Chapter 3-78
n 1 io
iW ( k 1) (t0 )
mn 2
i (t ) io ( x 1,2, , n, and x k 1)
Wx 0
mn 2
(3.52)
iD ( k 1) (t ) iLf ( k 1) iw ( k 1) iw ( k 2) 0
2i
io
(3.53)
Items
Values Units
Remarks
Vin,min
1350
Vin,rated
1500
Vin,max
1650
Vo
48
output voltage
2000
50
kHz
switching frequency
Io
10
current ripple
Vo
voltage ripple
Th
20
ms
Deff,designed
0.5
number of modules
Chapter 3-79
mVinTs .
n V
2
(3.54)
0.5 into (3.54), it results in m = 0.977. Thus, the value of m is practically chosen to be close
to such theoretical value.
between duty cycle loss and ZVS load range is considered. Consequently, Llk is selected
with the value of 20 H to achieve soft-switching from a 60% load and above.
The duty
cycle loss at nominal load will be 0.11 accordingly. It should be noted that the leakage
inductance of isolation transformer depends on the design and fabrication process conducted
by the manufacturer. On the one hand, it is unnecessary to design transformers with the
required leakage inductance because an external inductor can be placed in series with the
primary windings of the transformer. On the other hand, the leakage inductance is usually
pre-determined, provided by the manufacturer. The components used in the converter are
thus designed with the leakage inductance.
Chapter 3-80
0,30
10% load
30% load
50% load
80% load
100% load
0,25
0,20
0,15
0,10
0,05
0,00
0
10
15 20 25 30 35 40
Leakage inductance (H)
45
50
Fig. 3.6 Duty cycle loss versus leakage inductance under different loading condition
(Vin = 1500 V, Io,rated = 41.7 A, m = 1, n = 4, fs = 50 kHz).
100%
90%
80%
70%
60%
50%
40%
30%
20%
0
10
15 20 25 30 35 40
Leakage inductance (H)
45
50
Chapter 3-81
identical (i.e. Lf1 = Lf2 == Lfn) one can obtain the phase current ripple
Deff VoTs
iLfk 1
n Lf
(3.55)
io 1 Deff
VoTs
Lf
(3.56)
n D times of the
eff
phase current ripple. For n = 4, Deff = 0.5, the output current ripple will be 57% of the phase
current ripple. The output inductor is designed according to the required io in Table 3.1 as
Chapter 3-82
VoTs
io
(3.57)
vo
io Ts / n
8Co
I Co ,rms
io R ESR _ Co
2
3
io
6
(3.58)
(3.59)
The capacitance Co, equivalent series resistance (ESR) RESR_Co, and ripple current
rating IAC of the capacitor are selected to ensure that the output voltage ripple is less than 1%
of the nominal value, and ICo,rms is lower than IAC.
220 F, RESR = 212 m and IAC = 1.49 A are used in parallel for the testing prototype. The
power dissipation of the output capacitor is approximately equal to io2 RESR 12 .
is given by
Deff io
mn 2
Deff io
mn
kU
mn
mn 2
Chapter 3-83
VCk
n D i D
eff
mn Ck
eff
Ts
n D i R
eff
mn
ESR _ Ck
(3.60)
where R ESR _ Ck is the ESR of the selected capacitors to ensure VCk is within 1% of Vin /n.
The input capacitors are designed by considering the 20 ms hold-up time from 1500 V to
1200 V.
It results in
Cin
2 PoTh
V
Vin2, drop
2
in , rated
(3.61)
where Th is the designed hold-up time, Vin,rated is the nominal input voltage, Vin,drop is the
designed voltage drop within the hold-up time period, and is the designed efficiency ( =
90% for calculation). The minimum calculated value Cin is 109.7 F.
Accordingly, four
400 V (450 V surge) 680 F electrolytic capacitors with ESR of 150 m at 100 Hz are
selected for C1-C4.
Film capacitors are selected for the dc-blocking due to their high current capability
and low ESR properties. In dc-dc converter applications, the selection of film capacitors
applied for dc-blocking mainly depends on the required capacitance limited by voltage
ripple.
By neglecting the transition intervals, according to Fig. 3.3, the voltage ripples of
1 (n 1)io Ts
CWk mn 2 n
(3.62)
The value of the capacitance is designed to ensure the voltage ripple of each
capacitor is less than 2.5%. In the prototype, the voltages across CW1, CW2, CW3 are Vin /4
and the voltage stress of CW4 is (3 /4) Vin. Accordingly, 400 V/4.7 F metallized polyester
film capacitors with measured ESR of 14.3 m at 50 kHz are selected for CW1, CW2, CW3 and
Chapter 3-84
1200 V/1.5 F metallized polypropylene film capacitor with measured ESR of 9.9 m at 50
kHz is chosen for CW4.
cases, the widely used 500 or 600 V MOSFET can serve for implementing the proposed
converters.
Table 3.2 Number of switch pairs, turns ratio of transformer and voltage rating of
MOSFET for specific input voltage.
Vin (V)
600
3:2
500
750
15:8
600
1000
6:5
500
1500
1:1
600
2000
4:3
600
3000
1:1
600
Chapter 3-85
Chapter 3-86
Fig. 3.10 Measured PWM driving signals for switch pairs SP1 and SP2
(vGS1U, vGS1D, vGS2U and vGS2D: 10 V/div, Timebase: 2 s / div).
Fig. 3.11 gives the switching waveforms of switch pair SP1 under various loading
condition (i.e. 100%, 80% and 60% of the nominal load).
switching transistors are turned on/off with zero-voltage, implying a negligible switching
loss. With load variations, the reflected load current in the primary-side changed; therefore,
the slopes of the MOSFET voltages have a small difference during the ZVS commutation
intervals.
The voltage stresses on the two switches are only one-fourth of the total input
voltage. The switching waveforms of other switche pairs are similar with those of SP1.
Chapter 3-87
Fig. 3.11 ZVS turns on/off of one switch pair under different loading condition
(vGS1U and vGS1D: 10 V/div, vS1U and vS1D: 200 V/div, Timebase: 200 ns/div).
Chapter 3-88
Chapter 3-89
Fig. 3.14 Waveforms of driving signals and currents in one rectification branch.
Fig. 3.12 shows the waveform of the current iW1 flowing through the primary-side
winding of the isolation transformer. The current stresses, thus, the conduction losses of the
primary-side switches depend on the primary-side currents in the isolation transformer
windings.
Fig. 3.13 presents the waveforms of the four output inductor currents.
Due to the
self-balancing mechanism of the input capacitor voltages and well-balanced power stage
design, the prototype shows a good performance of output phase current sharing among
different rectification branches, with Ts /4 phase shift between two adjacent inductor currents.
It can be observed from the waveforms that the discrepancy between the largest inductor
current and smallest inductor current is 0.96 A, which is acceptable when considering the
design margin of the output inductors.
Chapter 3-90
Fig. 3.14 gives the inductor and diode currents in one rectifier branch.
It can be
noted that both the current stress of the inductor and average current of the diode are 1/n of
the output current.
Therefore, the magnetic size of the inductors and the conduction loss of
the diodes are reduced, giving an improved efficiency and well thermal distribution.
The
The
efficiency measured at around nominal power rating (Po = 2023 W) is 90.75%. The power
losses in different components are measured under full load as shown in Fig. 3.16. The
input power is 2229.2 W and the ratios between the power loss in specific component and
input power are also indicated in the figure. It can be noted that the major losses are in the
passive components, i.e. isolation transformers, output inductors and rectifiers, while the
total loss in the MOSFETs is only 2.51% of the input power.
of the MOSFETs is dominantly induced by the conduction loss and their switching loss is
negligible with the aid of ZVS switching.
Chapter 3-91
100
Hard-switching
Soft-switching
95
Efficiency (%)
90
85
80
75
70
65
60
800
1000
1200
2000
2200
Fig. 3.16 Measured losses in the components under full load (Pin = 2266.8 W and the ratios
between the power loss in specific component and input power are indicated in percentage).
Chapter 3-92
The voltage stress on the primary-side switches and the current stress in the
secondary-side inductors/diodes are reduced to 1/n of the input voltage and output current,
respectively. Therefore, it allows the use of MOSFETs with low voltage rating and diodes
with low current rating. ZVS of the switching devices achieves a negligible switching loss.
The voltages across the input capacitors and the currents through the output inductors are
well-balanced due to the intrinsic self-balancing mechanism. The current multiplier with
interleaved rectification in the secondary-side reveals high current capacity and reduced size
of magnetic components. The experimental evaluations on a 1500 /48 V 2 kW prototype
with four switch pairs verify the theoretical analysis. An efficiency of 90.75% is obtained
at nominal load. Compared with other available topologies, as shown in Table 3.3, the
proposed structure represents the optimum one with respect to the voltage stress on the
switches and number of switches. Especially, compared with FB- based ISOP converters,
the proposed converter withstands the same voltage stress, however, halves the number of
switches.
Table 3.3 Comparison of number of switches and voltage stresses in different topologies.
Topology
No. of switch
Voltage stress
FB converter
Vin
TL converter
Vin / 2
FB based ISOP
converter
4n
Vin / n
Proposed converter
2n
Vin / n
Chapter 4-93
CHAPTER 4
HIGH INPUT VOLTAGE THREE-LEVEL DC-DC CONVERTER WITH
ASYMMETRIC VOLTAGE DISTRIBUTION ON SWITCH PAIRS
4.1. Introduction
This chapter presents a power conversion concept with asymmetric distribution of
the high input voltage among switch pairs in multi-level dc-dc converters. Instead of same
voltage stress on the primary-side switches as those discussed in Chapter 3, it is
intentionally control the voltage distribution among the switch pairs by applying different
duty cycles for them.
The advantages of the proposed asymmetric conversion concept are twofold.
Firstly, it provides an additional degree of freedom to choose switching devices, allowing
optimal selection of their voltage ratings and thus overall performance.
The low-voltage
switch pairs can be implemented with MOSFETs, and the high-voltage switch pairs with
IGBTs. Secondly, it exhibits new properties which ensure ZVS of the MOSFET switch
pairs started from very light load without additional circuitry for ensuring soft-switching.
Based on the proposed concept, a TL converter with one IGBT switch pair and one
MOSFET switch pair is proposed. Besides the ZVS of the two MOSFETs, an active
snubber is introduced in the secondary-side to assist the ZCS of the two IGBTs. The ZCS
snubber energy is completely released to the load, leading also to a duty-cycle gain.
Therefore, the proposed soft-switching scheme is fundamentally different from ZVZCS and
is named as hybrid ZVS-ZCS. A 2 kW prototype, which performs the same function as the
one discussed in Chapter 3 (i.e., conversion from 1500 V dc to 48 V dc), is built and
evaluated to verify the theoretical analysis.
Chapter 4-94
Chapter 4-95
Fig. 4.1(a) presents the proposed converter with two switch pairs SP1 and SP2,
which are composed of two IGBTs S1, S2, and two MOSFETs S3, S4 connected in series,
respectively. The intermediate stage is a dc-blocking capacitor Cb and high frequency
isolation transformer.
and its leakage inductance is Llk. VC1, VC2 and VCb are the voltages across the dc-link
capacitors C1, C2 and the capacitor Cb, respectively.
capacity, a current doubler rectifier [99] is applied in the secondary side, formed by two
inductor-diode branches Lf1-DR1 and Lf2-DR2.
diode Da, capacitors Cr1, Cr2 and inductor Lr is shown in Fig. 4.1 to fulfill ZCS of S1 and S2.
Sa1 is used to provide ZCS condition for S1 while Sa2 is used to provide ZCS
condition for S2.
The function of Sa1 and Cr1 is to reduce isec, and thus ip, from positive
value to zero before S1 turns off. And the function of Sa2, Da, Lr and Cr2 is to increase isec
from negative to zero before S2 turns off.
VC 1
VC 2
D2
D1
(4.1)
where k is defined as the voltage distribution factor, D1 and D2 are the steady-state duty
cycles of upper switches in each switch pair, S1 and S3.
available solutions distribute the input voltage equally among the switch pairs (i.e., k = 1).
Referring to (4.1), the concept proposed here allows asymmetric voltage stresses on each
Chapter 4-96
additional degree of freedom to select switching devices and allow for optimal
combinations in terms of the operating frequency, switching loss, conduction loss and costeffectiveness.
of Sa1 depends on the turn off time of S1 (i.e., the control signal vcon). Sa2 is turned off at the
end of a switching cycle, implying a fixed turn on time instant. The voltages across C1 and
C2 are also sampled for overvoltage protection and fine tuning k if necessary for limiting the
discrepancy between the actual voltage stress distribution and the desirable one.
The operation consists of nine modes in one switching cycle. The timing diagram
for a steady-state cycle is shown in Fig. 4.2(a). Fig. 4.2(b) and Fig. 4.2(c) show the
detailed operation of the two auxiliary snubber switches Sa1 and Sa2, respectively. For sake
of simplicity, the analysis is referred to the secondary of the transformer. The equivalent
circuits in each operation mode are given in Fig. 4.3. The voltages across the input
capacitors C1, C2, and dc-blocking capacitor Cb are assumed constant in steady-state and
the output inductors Lf1 and Lf2 are large enough to be considered as constant current
sources. The parameters used in the following discussions are listed in Table 4.1.
Chapter 4-97
D2
D1
D2
tdl1
tdr1
tdl2
tdr2
Ts
ti-j
VC2-VCb
Leq
r1
Llk (Cr1 Cr 2 )
Llk (Cr 1 C r 2 ) m
Zr1
r2
Llk Cr1 m
Zr2
r3
Zr5
Lr Cr 2
Lr Cr 2
Zr4
r5
Zr3
r4
Llk C r 1
Leq Cr 2
Leq Cr 2
Chapter 4-98
Chapter 4-99
Chapter 4-100
Mode 1 [t0-t1] - Transition from freewheeling stage to energy transfer stage I [Fig. 4.3(a)]
Before S1 is turned on, the currents through diodes DR1 and DR2 keep constant and
the body diode of S2 is conducting as shown in Fig. 4.3(a)-(i) and Fig. 4.3(a)-(ii).
When S1
is on, the current in DS2 is diverted to S1 linearly due to the presence of parasitic inductance
LS1 as shown in Fig. 4.3(a)-(iii).
linearly due to voltage (VC1+VC2-VCb) /m applied on the leakage inductance Llk /m2. Thus,
the current in DR1 decreases and reaches zero at t1, while that in DR2 increases to the load
current. At t1, current isec increases to iLf1 and DR1 is finally blocked. The duration of this
mode is given by
t1 t 0 t 01 t dl1
VC1
mVC1 V
(4.2)
where iS2(t12) is the current flowing through DS2 at the instant t12, i.e. at the end of steadystate cycle, as given by (4.33). The absolute value of iS2(t12) depends on the loading
condition and increases with the reduction of the load. With practical design, at full load,
iS2(t12) is approximately equal to zero while at no load iS2(t12) is -iLf2,nom / m, where iLf2,nom is
the current flowing through Lf2 under the nominal load. Moreover, the duration in which iS1
increases from zero to iLf1/m is very short, as compared to the switching period. To simplify
the analysis, iS1 is assumed to increase linearly from zero to iLf1/m as shown in Fig. 4.2(a)
and the value of LS1 is negligible compared to Llk. Therefore, the duration of t0-1 in (4.2) is
approximated by
t1 t 0 t 01 t dl1
Llk i Lf 1
mVC1 VC 2 VCb
t dl1
Llk i Lf 1
mVC1 V
(4.3)
Meanwhile, Lr and Cr2 are in a resonant mode until iSa2 (current flowing through the
body diode of Sa2) reaches zero within t0-1 as shown in Fig. 4.3(a)-(i) and Fig. 4.2(c).
Chapter 4-101
(i)
(ii)
Chapter 4-102
(iii)
(iv)
Fig. 4.3(a) Mode 1 (t0-t1).
Chapter 4-103
isec (t ) i Lf 1
v C r 1 (t )
v Cr 2 (t )
VC1 'V
sin Z r1 (t t1 )
mZ r1
V C 1 'V
>1 cos Z r1 (t t1 )@
m
(4.4)
(4.5)
i S1 (t ) i p (t )
i Lf 1
m
VC1 'V
m 2 Z r1
sin Z r1 (t t1 )
(4.6)
After one-half resonant cycle, at t2, the capacitor voltages vCr1 and vCr2 reach their
maximum value 2(VC1+V) / m and the current isec returns to iLf1. The diode DSa1 and Da are
blocked and the voltages of Cr1 and Cr2 are clamped at the maximum level. The time
interval of this sub-stage is equal to half of the resonant cycle, that is
t 2 t1
t1 2
S Llk (C r1 C r 2 )
m
(4.7)
Sub-stage II [t2-t3] [Fig. 4.3 (c)] - Energy transfer with constant isec. During this
sub-stage, all of the voltages and currents in the circuits are assumed constant.
Sub-stage III [t3-t4] [Fig. 4.3 (d)] - Commutation of S1 with ZCS. At t3, Sa1 turns on
Chapter 4-104
with ZCS due to the presence of leakage inductance Llk, which starts resonating with Cr1 to
make the current through S1 drop to zero or become negative. The initial voltage of Cr1 is
vCr1(t3) = 2(VC1+V) / m as discussed above. Therefore, it can be obtained that
VC1 V
sin r 2 (t t 3 )
mZ r 2
(4.8)
VC 1 V
1 cos r 2 (t t 3 )
m
(4.9)
VC1 V
sin r 2 (t t 3 )
mZ r 2
(4.10)
isec (t ) i Lf 1
v C r 1 (t )
iSa1 (t )
It implies that
iS1 (t ) i p (t )
i Lf 1
m
VC1 V
sin r 2 (t t 3 )
m2Zr2
(4.11)
When the current through S1 drops to zero, and goes negative, DS1 conducts. S1 is
turned off at t4 with ZCS when iS1 reaches its negative peak value as shown in Fig. 4.2(b)
(iS1 = isec /m). Therefore,
v C r 1 (t 4 )
V C 1 V
m
t 4 t 3 t 3 4
Llk C r1
2m
(4.12)
(4.13)
Chapter 4-105
Chapter 4-106
(i)
(ii)
Fig. 4.3(d)
Chapter 4-107
Mode 3 [t4-t5]-Transition from energy transfer stage to freewheeling stage I [Fig. 4.3(e)]
After S1 is turned off at t4, isec increases to zero from negative values, and then the
body diode of S1, DS1, is blocked.
shown in Fig. 4.2(a). As the diode DR1 is still in the blocking state, iLf1 is fully supplied by
the capacitor Cr1 before S2 is turned on. After S2 is on, Cr1 is further discharged until its
voltage drops to zero as shown in Fig. 4.2(b). The duration of this mode is approximately
equal to
t 5 t 4 t 4 5
C r1 (VC1 V )
mi L f 1
(4.14)
It should be noted that although S1 is off during this period, the diode DR1 is still off
and the resonant energy of Cr1 is released to the load, contributing to a duty cycle gain.
(i)
Chapter 4-108
(ii)
Fig. 4.3(e) Mode 3 (t4-t5).
Mode 4 [t5-t6]-Freewheeling stage I [Fig. 4.3(f)]
As vCr1 reduces to zero at t5, DR1 turns on naturally. iDR1 increases from zero to
iLf1while iSa1 reduces to zero quickly as shown in Fig. 4.2(a) and Fig. 4.3(f)-(i). Therefore,
Sa1 can be turned off with ZCS after a short while since iSa1 becomes zero. The diodes DR1
and DR2 are in freewheeling state. However, unlike that stage with symmetric operation
between two switch pairs in TL converter [43], the current flowing through the transformer
winding isec increases linearly due to a difference of the voltages on C2 and Cb. This
phenomenon is owing to asymmetric operation of the two switch pairs, which will be
investigated in Section 4.5 in detail. As shown in Fig. 4.3(f),
isec (t )
mV (t t 5 )
Llk
(4.15)
Chapter 4-109
This mode ends when t = Ts /2 and S4 is turned off with ZVS due to the presence of
its parasitic capacitance CS4. The duration of this mode is
t 6 t 5 t 5 6
Ts (1 D1 )
t dr1
2
(4.16)
isec (t 6 )
mV Ts
mV
(t 6 t 5 )
(1 D1 ) t dr1
Llk 2
Llk
(i)
(4.17)
Chapter 4-110
(ii)
(iii)
Fig. 4.3(f) Mode 4 (t5-t6).
Chapter 4-111
Mode 5 [t6-t7] - Transition from freewheeling stage to energy transfer stage II [Fig. 4.3(g)]
After S4 is turned off at t6, the equivalent circuit is shown in Fig. 4.3(g). With initial
conditions vCS3(t6) = VC2 and ip(t6) = isec(t6) / m,
1
vCS 3 (t ) VCb 'V cos Z r 3 (t t 6 ) i p (t 6 ) Z r 3 sin Z r 3 (t t 6 )
2
i p (t )
2 'V
sin Z r 3 (t t 6 ) i p (t 6 ) cos Z r 3 (t t 6 )
Z r3
(4.18)
(4.19)
The process described by (4.18)-(4.19) is the resonance occurred among Llk, CS3 and
CS4. CS3 is fully discharged and CS4 is fully charged by the energy stored in the leakage
inductance. DS3 will conduct when the voltage of CS3 reaches zero as shown in Fig. 4.3(g)(ii). This transition takes place in a similar way as the corresponding process in symmetric
FB or TL converters.
provided by Llk is independent of loading condition, which can be observed from (4.17). It
implies that S3 can be turned on with ZVS from very light load to full load without any
additional assisted strategies. S3 is turned on with ZVS in a short while after DS3 conducts.
The current in DR2 reaches zero at t7 while the current of DR1 increases to the load
current. At t7, the primary-side current ip negatively increases to -iLf2/m. Therefore, the
duration of this mode is given by
t7 t6
t 6 7
tdl 2
Llk iLf 2
mVC 2 'V
(4.20)
Chapter 4-112
(i)
(ii)
Chapter 4-113
(iii)
Fig. 4.3(g) Mode 5 (t6-t7).
Chapter 4-114
t 9 t 8 t 89
i Lf 2
isec (t 8 )
(4.21)
Chapter 4-115
isec (t ) i Lf 2
mV (t t 9 )
Llk
(4.22)
Chapter 4-116
Sub-stage II [t10-t11] [Fig. 4.3(k)]- Resonance between Lr and Cr2. Cr2 starts to
resonate with Lr after Sa2 turns on with ZCS at t10 as shown in Fig. 4.2(c). The equivalent
circuit is presented in Fig. 4.3(k) with the initial value of vCr2(t10) = 2 (VC1+V) / m,
implying that
vCr 2 (t )
2(VC1 V )
cos r 4 (t - t10 )
m
(4.23)
i Sa 2 (t )
2(VC1 V )
sin r 4 (t - t10 )
mZ r 4
(4.24)
This mode ends when vCr2 drops to zero at t11, therefore, the duration of this sub-stage is
i Sa 2 (t11 )
Lr C r 2
2
2 (VC1 V )
mZ r 4
(4.25)
(4.26)
According to (4.22), by neglecting the short period of tdr2 and t11-12, one gets
isec (t11 ) i Lf 2
m(1 D2 )VTs
2 Llk
(4.27)
Chapter 4-117
Llk
[iSa 2 (t11 ) isec (t11 ) iLf 2 ][1 cos r 5 (t t11 )]
m Lr Llk
2
m 2 Lr
[iSa 2 (t11 ) isec (t11 ) iLf 2 ][1 cos r 5 (t t11 )]
isec (t ) isec (t11 ) 2
m Lr Llk
It implies that the primary-side current flowing through S2 is given by
(4.28)
(4.29)
(4.30)
Chapter 4-118
iS 2 (t )
isec (t )
i (t )
mL
sec 11 2 r
[iSa 2 (t11 ) isec (t11 ) iLf 2 ][1 cos r 5 (t t11 )]
m
m
m Lr Llk
(4.31)
Within one-half of the resonant cycle, isec increases from negative values to zero,
and then to positive values. iSa2 drops to zero and then goes to below zero as indicated in
Fig. 4.2(c). Therefore, S2 and Sa2 can be turned off with ZCS after their currents become
negative, respectively. It can be noted that during this period, the diode DR2 is blocked and
the energy in Cr2 is transferred to the load, contributing a duty cycle gain. The duration of
this sub-stage is given by
t12 t11 t1112 Leq C r 2
(4.32)
iLf 2
m
1 D2 VTs
2 Llk
2 Llk
m Lr Llk mZ r 4
(i)
(4.33)
Chapter 4-119
(ii)
(iii)
Fig. 4.3(l) Mode 9 (t11-t12).
Chapter 4-120
VCb VC 2
2
2
1
D1VC1 D2VC 2 C sVC 2 CsVC 2 VC1t dl1
2
Ts
i p (t 6 )Ts i p (t8 )Ts
(4.34)
Detailed proof of (4.34) is given in the Appendix A.1. In practical design, the third
term is negligible compared to other ones because of a very small value of Cs and small
difference between ip(t6) and -ip(t8). Therefore, VCb is approximately equal to
VCb VC 2
1
D1VC1 D2VC 2 VC1t dl1
2
Ts
(4.35)
According to (4.35),
V VC 2 VCb
VC1t dl1 1
D1VC1 D2VC 2
2
Ts
(4.36)
VC1 V 2m
(4.37)
Vo
1
D2 D2
VC 2 V 2m
(4.38)
Chapter 4-121
where
C V V
Llk iLf 1
L C
V
D1 2 r1 C1
lk r1
mTs
VC1 mTs VC1 V
2miLf 1Ts
(4.39)
mCsVC 2
4 Leq VC1 V
Llk iLf 2
m 2 Leq 1 D2 V
t
D2 2
dl 2
Llk VC 2 V
Lr Cr 2 VC 2 V Ts Ts m VC 2 V Ts
iLf 2Ts
(4.40)
It should be
noted that the above equations for D1 are for heavy loading condition when the secondary
winding current isec can be assumed to be zero during t01 and t45. Under light load, with the
consideration of isec, the first term (i.e., t45/(2Ts)) of D1 is approximately presented by
Cr1 VC1 V
2m iLf 1 isec Ts
, where isec is the average current of isec during t45. The fourth term of D1
is zero due to that isec itself is sufficient to supply the load current, implying that there is no
duty cycle loss during the turn on transition of S1.
According to (4.37)-(4.38), the conversion ratio is given by
Vo
1 D1 D1 D2 D2
Vin 2m D1 D1 D2 D2
(4.41)
Practically, the net effect values of D1 and D2 are negligible compared to D1 and
D2. Therefore, Eq. (4.41) can be simplified into
M
Vo
1 D1 D2
Vin 2m D1 D2
(4.42)
1 k
D1
2m 1 k
(4.43)
Chapter 4-122
VC1 Vin D2 D2 V D1 D1 D2 D2
VC 2 Vin D1 D1 V D1 D1 D2 D2
(4.44)
VC1 D2
VC 2 D1
(4.45)
Therefore, the voltage across the switches in each switch pair can be adjusted by
varying D1, D2, and thus k, allowing for the choice of the optimal combination of switching
devices.
It should be noted that the input to output voltage ratio is not necessary to be
constant. The duty cycles of D1 and D2 will be updated accordingly with the required
voltage conversion ratio.
During the startup, the voltage distribution can be assured by selecting the ratio
between the capacitance values of C1 and C2. The capacitors C1 and C2 are charged up
instantaneously at the beginning to the initial values defined as VC1 (0) and VC2 (0), which
are assumed to be inversely proportional to their capacitance values. It gives that
VC1 (0) C 2
VC 2 (0) C1
(4.46)
The DSP controller provides a soft-start function that makes the effective duty cycle
increase slowly, and controls the two capacitor voltages (i.e., VC1 and VC2) in the designed
ratio.
Chapter 4-123
the determination of the turns-ratio of the transformer, leakage inductance (or external
inductance if necessary) Llk, the voltages difference V, and the snubber passive
components Cr1, Cr2 and Lr. For selection of other components selection, the design
guidelines are similar with conventional cases (e.g., the converter discussed in Chapter 3)
and will not be presented here.
Table 4.2 Design specifications of the experimental prototype.
Specifications
Value
1500 V
1350 V
1650 V
2 kW
<1 %
48 V
<10 %
Switching frequency ( fs )
50 kHz
Issues on the turns-ratio of the isolation transformer and duty cycle ranges
According to (4.43), (4.45) and the specifications listed in Table 4.2, the duty cycle
ranges with respect to different turns-ratio of the isolation transformer are shown in Table
4.3. To allow the proper operation, the values of D1 and D2 should be within [0, 0.5] and
Chapter 4-124
[0, 1], respectively. m = 4 is selected to retain reasonable margins of the D1 and D2.
Moreover, compared to the cases when m is less than 4 (e.g., m = 2, m = 3), it will reduce
the primary-side currents to achieve lower conduction losses of the switching devices.
Table 4.3 Ranges of duty cycles with respect to m.
m
D1,min
0.175
0.262
0.349
0.436
D1,nom
0.192
0.288
0.384
0.480
D1,max
0.213
0.320
0.427
0.533
D2,min
0.349
0.524
0.698
0.873
D2,nom
0.384
0.576
0.768
0.960
D2,max
0.427
0.640
0.854
1.067*
2)
Llk iLf2 1
C 1, min
(4.47)
Chapter 4-125
Cr 2
Lr 1 D2,min VTs
4 Llk m2 Lr VC1,min V
(4.48)
Lr Llk m 2 (4.49)
VC 2,max 2 Llk Cs
1 D
1,max
2 tdr1
(4.50)
there is a slight difference in the voltages between VC2 and VCb, S3 will be in ZVS.
Practically, the variations of the midpoint voltage between C1 and C2 only affect the
duration of the switching transition of S3.
(e) ZVS condition of S4
It is practically easy for S4 to achieve ZVS as the converter is still operating in
energy transfer stage before S4 is turned on.
Chapter 4-126
The secondary-side active snubber provides ZCS condition for the IGBTs. Without
it, all IGBTs could be switched with ZVS, but not a favorable operation. Moreover, S3
might also be hard-switched at turn on.
3)
the pre-selected maximum current rating of the switching device S1, defined as IS1,max.
According to (4.6), it is given by
iS 1,max
iLf 1
m
VC1,max V
m Llk (Cr1 Cr 2 )
I S 1,max
(4.51)
(b) Current limit of the primary-side winding during the freewheeling stage t5-6
During the freewheeling stage t5-6, the current in the primary-side winding flows
through S2 and S4 and its magnitude should be less than the pre-selected maximum current
ratings of these devices. According to (4.17), the condition is given by
i p (t6 ) max
V Ts
1 D1,min VTs
1
t
min I S 2,max , I S 4,max
dr
1,min
1
Llk 2
2 Llk
(4.52)
where IS2,max and IS4,max are the pre-selected maximum current ratings of S2 and S4,
respectively.
(c) Current limit of Sa2
The maximum current flowing in Sa2 occurs at t11 and from (4.26), one gets
Chapter 4-127
iSa 2,max
2 VC1,max V
m Lr Cr 2
I Sa 2,max
(4.53)
where ISa2,max is the pre-selected maximum current rating of Sa2 and VC1,max is the maximum
voltage stress on C1.
4)
Issues on the conduction time of Sa1 and Sa2 and resonant time of t1-2
The conduction time of Sa1 is t3-5 and that of Sa2 is t10-12. To ensure proper operation
of the switching devices, the minimum conduction durations should be larger than
reasonable values (e.g., larger than five times of the total turn on/off time of Sa1 and Sa2,
respectively). Therefore, according to (4.13)-(4.14), (4.25) and (4.32), the conditions are
given by
Llk Cr1
2m
Cr1 (VC1,min V )
Lr C r 2
2
miL f 1
5 t r1 t f 1
Leq C r 2 5 t r 2 t f 2
(4.54)
(4.55)
where tr1 and tf1 are the turn on and turn off time of Sa1, respectively. tr2 and tf2 are the turn
on and turn off time of Sa2, respectively.
The time duration of t1-2 is given by (4.7), which will affect the conduction loss of
S1. The longer t1-2 is, the larger conduction losses are induced. Therefore, t1-2 is designed
to be less than 25% of the conduction time of S1. It gives that
Llk (C r1 C r 2 )
m
25% D1,min
Ts
2
(4.56)
Chapter 4-128
m 2 I Sa2 2,max Lr
4 VC1,max 'V
(4.57)
(4.58)
By substituting the maximum values of Cr2 and Leq represented by (4.57) and (4.58),
respectively, into (4.55), one gets
Lr !
20 VC1,max 'V tr 2 t f 2
20 tr 2 t f 2 VC1,max
3S mI Sa 2,max
3S mI Sa 2,max
(4.59)
According to (4.47),
Llk i Lf2 1
C 1,min
'V
(4.60)
By substituting the minimum value of Cr1 + Cr2 represented by (4.60) into (4.56),
Llk
mVC1,min D1,minTs
8S iLf 1
(4.61)
Therefore, according to (4.49), (4.59) and (4.61), the boundaries of Lr and Llk are
given by
20m tr 2 t f 2 VC1,max
3S I Sa 2,max
Llk
20 tr 2 t f 2 VC1,max
3S mI Sa 2,max
mVC1,min D1,minTs
8S iLf 1
Lr
Llk
m2
(4.62)
(4.63)
Chapter 4-129
2)
Boundary of V
According to (4.52),
'V d
(4.64)
1 D T
1,min
VC 2,max 2 Llk Cs
1 D T
1,max
3)
2 tdr1
d 'V d
(4.65)
1 D T
1,min
Boundary of Cr2
According to (4.48) and (4.57),
Lr 1 D2,min 'VTs
4)
d Cr 2 d
m 2 I Sa2 2,max Lr
4 VC1,max 'V
(4.66)
Boundary of Cr1
According to (4.51),
Cr 1 d
C1,max 'V
Cr 2
(4.67)
VC1,min 'V
d Cr 1 d
VC1,max 'V
Cr 2
VC1,max 'V
(4.68)
Chapter 4-130
up with the increase of V under specific Llk. Moreover, by referring to (4.53) and (4.66), it
can be observed that small value of V is beneficial to reduce the lower boundary of Cr2,
therefore, allowing reduction of the current stress of Sa2. V is designed with its minimum
value represented by (4.65). Therefore,
V Vmin
VC 2,max 2 Llk Cs
1 D T
1,max
2 tdr1
(4.69)
VC1t dl1
Ts
(4.70)
2)
current stress of S1 with different Llk and Cr1. Each pair of values of Llk and Cr1 within the
boundaries presented by (4.62) and (4.68) are reiterated by (4.54) and (4.56) and only the
ones meet the conditions are shown in Fig. 4.4. It should be noted that the value of Cr2 is
neglected for the sake of simplification during the checking process. Moreover, the values
of the current stress shown in Fig. 4.4(b) are approximated ones with Cr2 = 0. This
approximation will not affect the design of Llk and Cr1 as Cr2 is much smaller than Cr1 and
Chapter 4-131
Chapter 4-132
3)
stress of Sa2 with varying values of Lr and Cr2. Each pair of values of Lr and Cr2 within the
boundaries presented by (4.63) and (4.66) should meet the condition in (4.55). It can be
noted that higher value of Lr is beneficial to increase the value of D2 and reduce the
current stress of Sa2. Large value of Cr2 is also preferable to obtain more duty cycle gain,
however, will induce high current stress on Sa2.
Chapter 4-133
Chapter 4-134
The specifications are as shown in Table 4.2. The design flow chart of V, Llk,
Lr, Cr1 and Cr2 based on the design guideline in Section 4.5 is presented in Fig. 4.6.
According to Table 4.3, the turns ratio of the isolation transformer is selected as m = 4 and
the duty cycle D1, D2 are within [0.349, 0.427] and [0.698, 0.854], respectively.
Fig. 4.4
and Fig. 4.5 are plotted with the pre-selected switching devices which have the following
parameters: IS1,max = 20 A, ISa2,max = 48 A, tr1 = tr2 = 22 ns and tf1 = tf2 = 29 ns. To
compromise D1 and current stress of S1, maximum allowable Llk is chosen and minimum
value of Cr1 is selected. With the design specifications, Llk = 36 H and Cr1 = 34 nF. Lr is
selected with the allowable maximum value and trade-off considerations should be made
for the selection of Cr2.
Therefore, Lr is selected with 1.6 H to maintain a reasonable difference from that of Llk /m2
and to retain margin for tolerance considerations of practical inductors.
be 10 nF.
Cr2 is chosen to
Chapter 4-135
Fig. 4.6 Design flow chart for V, Llk, Lr, Cr1 and Cr2.
Chapter 4-136
Transformer
Inductance Llk
Component Selections
Turns ratio m
4:1
Magnetizing inductance
9.5 mH
11 H
36 H
25 H
dc-link capacitors C1
dc-link capacitors C2
dc-blocking capacitor Cb
Output capacitor Co
120 H
MOSFETs S3 and S4
Snubber diode Da
34 nF (film cap.)
10 nF (film cap.)
Snubber inductor Lr
1.6 H
Chapter 4-137
The
Chapter 4-138
Fig. 4.8 Asymmetric driving signals for the two switch pairs.
Chapter 4-139
Chapter 4-140
(e) ZCS turn on/off of Sa1 and Sa2 under full load.
Fig. 4.9 Switching waveforms of S1-S4 and Sa1-Sa2.
Chapter 4-141
Fig. 4.10 shows the voltage waveforms across the input capacitors C1 and C2 at start
up. The voltage distribution ratio is found to be 1.998, which is in consistent with (4.45)
and (4.46).
Fig. 4.11 shows the relationship of open loop voltage and output current with fixed
duty cycle and input voltage.
current due to increased effective duty cycles. As the practical voltage drops on diodes,
active switches and parasitic resistors have not been considered in the theoretical
calculations, the calculated output voltages are observed to have some discrepancies with
the simulation and experimental ones.
Fig. 4.12 presents the measured efficiencies of the prototype. It reveals that the
proposed converter exhibits high efficiency within wide load ranges. The efficiency under
nominal load is 92.4%. The power losses in main components are analyzed in Fig. 4.13.
The key loss is on the rectifier diodes. With the aid of soft-switching, the power dissipated
on the two switch pairs is only 0.72% of the input power. The efficiency without the ZCS
snubber is also presented in Fig. 4.12, indicating an efficiency reduction of 1.7% under
nominal load mainly due to the turn off losses of IGBTs S1 and S2.
open loop voltage varying from 48 V to 52.1 V (corresponding to Fig. 4.11) under different
loading condition are shown in Fig. 4.12. The power losses are mainly composed of two
parts. The first part is almost constant, such as the core losses of isolation transformer and
output inductors, power supplies for gate drivers and control circuits, and part of the power
losses in the ZCS snubber. The second part is increased with the output power.
The
efficiency drops at light load due to that the first part power losses will become dominant.
Chapter 4-142
54
53
52
51
50
49
48
47
0
10
15
20
25
30
35
40
45
Chapter 4-143
95
93
Efficiency (%)
91
89
87
85
83
81
With ZCS Snubber
Without ZCS Snubber
Open loop with constant duty cycle
79
77
75
100
500
900
1300
Output power (W)
1700
2100
Chapter 4-144
Compared to the prototype in Chapter 3 with same specifications, the proposed one
achieves 16.2% volume reduction and 1.6% and 8.2% efficiency improvement under full
load and 50% load, respectively.
pairs can be soft-switched from very light load to full load with minimum circulating
energy. The control stage is implemented with a single digital controller without additional
hardware circuitry as compared to its counterpart in FB or TL converters. The switches of
the snubber commutate with ZCS. The concept is verified by a 1500/48 V 2 kW prototype.
Experimental results are in good agreement with the theoretical analysis.
A voltage
distribution factor of 2 is achieved and the measured efficiency at nominal load is 92.4%.
Chapter 5-145
CHAPTER 5
A UNIFORM FAST TRANSIENT CONTROLLER FOR DC-DC CONVERTERS
5. 1 Introduction
The output of the high input voltage converters discussed in Chapter 3 and Chapter
4 are usually used to supply energy for various kinds of low-voltage converters. The
performance of the dynamic response of those low-voltage converters is critical as they are
momentary loads in the metro train applications. This chapter presents a uniform fast
transient controller for those low-voltage converters based on the second-order switching
surface control method developed in [117].
Much effort has been made to the switching surface control of buck converter.
However, it remains a fundamental challenge to apply the same concept and associated
control technique to converters with non-minimum-phase characteristics.
A nonlinear
control method for all basic dc-dc converters (i.e. buck converter, boost converter, buckboost converter, uk converter and SEPIC) is proposed by deriving a uniform switching
surface.
It retains the advantages of boundary control for buck converter with second-
general-oriented and can determine the circuit variables needed in the switching function.
The same controller is universally applicable to different converters operating in both
continuous conduction mode (CCM) and discontinuous conduction mode (DCM).
A 190 W 48/48 V (i.e., unregulated input voltage with nominal value of 48 V to a
regulated output voltage of 48 V with different polarity) buck-boost converter prototype has
been built and evaluated to confirm the theoretical predictions.
Chapter 5-146
5.1(a)-(c), are composed of one capacitor and one inductor. The last two, uk converter
and single-ended primary-inductor converter (SEPIC), include two inductors and two
capacitors. Fig. 5.2 plots the theoretical waveforms of their inductor currents and capacitor
voltages. Generally, there are two types of distinctive curves to present the relationship
between inductor currents and capacitor voltages as shown in Fig. 5.2(a) and Fig. 5.2(b). It
can be noted from Fig. 5.2(b) that the capacitor voltages are monotonically decrease with
the corresponding inductor currents for converters with non-minimum phase characteristics,
imposing the challenge to apply switching surface control to those converters.
Chapter 5-147
(d) uk converter.
Chapter 5-148
Fig. 5.2 Theoretical relationships between inductor current and capacitor voltage:
(a) iL-vC in buck converter and iL2-vC2 in uk converter; (b) iL-vC in boost and buckboost converter, iL1-vC1 in uk converter and iL1-vC1, iL2-vC2 in SEPIC.
To handle the above fundamental issue in switching surface control and incorporate
the advantages of the boundary control with second-order switching surface which has been
applied on buck converter [117], a uniform second-order switching surface is proposed. It
extends the control state variables (i.e. inductor currents and capacitor voltages) in
previously proposed switching surface controllers to arbitrary direct or indirect control
variables, namely x and y.
dc converters are exactly the same as that of iL-vC in buck converter shown in Fig. 5.2(a).
Therefore, the switching surfaces of different kind of converters can be easily defined on a
Cartesian x-y plane.
2k s ( x x ref )
(5.1)
where ks is state trajectory parameter related with the slope of x and xref is the reference
value.
Chapter 5-149
Fig. 5.3 Principle of boundary control with uniform second order switching surface:
(a) control variables, (b) control law.
With the aid of Fig. 5.3, according to (5.1), the approximated on-state trajectory
Traj
on
and off-state CCM trajectory Traj off can be expressed respectively as follows
Traj
on
Traj
off
0
2
(5.2)
(5.3)
where t0 and t2 are the turn on/off instants, respectively, ks1 is the trajectory parameter
during on-state period and ks2 is that during off-state CCM period. ks1 > 0 and ks2 < 0. In
DCM, after the x reaches zero, the trajectory moves along the y-axis, x = 0 and the
corresponding trajectory parameter ks3 = 0 during this interval.
Fig. 5.4 presents typical switching surface, load line and ideal on/off statetrajectories of basic dc-dc converters on x-y plane.
Chapter 5-150
solving on- and off-state space equations of specific converter with different initial
conditions and then mapping the state variables iL and vC to x and y, respectively.
It is the
Fig. 5.4 Typical trajectories, load line and switching surface of basic dc-dc converters on
the x-y plane.
As discussed in [117], the ideal second-order switching surface 2 should pass
through the target operating point (yref, xref), and exactly along the approximated on-state
trajectory when x is below the load line, and the off-state trajectory when x is above the
load line.
By transforming the iL-vC state plane to the Cartesian x-y plane, a well-defined
Chapter 5-151
2 ( y yref ) k ( x xref ) 2
(5.4)
where 2 is the uniform second-order switching surface, k is the control parameter and can
be expressed as follows for an ideal second-order switching surface
1 sgn ( x x ref )
1 sgn ( x x ref )
k k s1
k s2
2
2
(5.5)
k can be of other values, which affect the stability and trajectory velocity along the
switching surface as discussed in Section 5.3. In the following analysis, k1 and k2 are
defined as general control parameters for turn-on and turn-off switching actions,
respectively. Practically, in order to avoid chattering phenomenon, a modified switching
surface 2 is derived by adding a hysteresis band 2 y as shown in Fig. 5.4 into (5.4),
resulting in
2 y y ref k1 ( x x ref ) 2 y
2
2
y y ref k 2 ( x x ref ) y
2
( x x ref )
( x x ref )
(5.6)
where 2 and 2 are the uniform second-order switching surface below and above load
line.
Therefore, the uniform control law for the basic dc-dc converters is formulated as
follows. The switch S is turned on if
Chapter 5-152
(5.7a)
(5.7b)
S is turned off if
Table 5.1 Load line and control variables of the proposed uniform control law.
Converter type
Buck
Boost
Buck-boost
uk
SEPIC
Load line
vo
R
iL
vo
vo io
vin
iL
1 2 1 2
LiL Cvo
2
2
vo io
io
vin
iL
1 2 1 2
LiL Cvo Cvin vo
2
2
vo
R
iL2
vo
iL1+iL2
1
L(iL1 iL 2 ) 2 C2 vo2 2C2 vin vo
2
iL
iL
iL
iL 2
iL1 iL 2
vo io
io
vin
kS1 (on-state)
L
2C (vin vo )
Boost
L
2
Buck-boost
L
2
uk
L2
2C2 (vC1 vo )
SEPIC
L
2
kS2 (off-state
CCM)
kS2 (off-state
DCM)
L
2Cvo
Lvin
2(vin vo )
Lvin
2vo
L2
2C2 vo
Lvin
2vo
Chapter 5-153
Table 5.1 and Table 5.2 tabulate the transformed variables x, y and their associated
load line and control parameters ks1 and ks2 for ideal second-order switching surfaces. An
example demonstrating the derivation procedures of x, y, and k for a buck-boost converter
will be given in Section 5.3.
The
results presented in Fig. 5.5 reveal that the single controller (with different control
parameters) can control the four converters operating in both CCM and DCM.
The
converters can revert to steady-state by two switch actions after being exposed to large
disturbances.
It can also be noted from Fig. 5.5(e)-(f) that x and y exhibit similar
properties during steady-state and transient periods as those of iL and vC in buck converter
discussed in [117].
Chapter 5-154
(b) Buck-boost converter with load change from 12 to 200 (CCM to DCM)
(vin = 48 V, vo,ref = 48 V, L = 0.1 mH, C = 150 uF).
Chapter 5-155
(d) SEPIC converter with load change from 200 to 12 (DCM to CCM)
(vin = 48 V, vo,ref = 48 V, L1 = L2 = 0.3 mH, C1 = 4.7 uF, C2 = 220 uF).
Chapter 5-156
Chapter 5-157
0 can be
divided based on the directions of on/off trajectories at the switching surface [106]. There
are three possible modes of the points: rejective mode, reflective mode and refractive mode.
In rejective mode, the trajectories on both sides of the switching surface depart away from
the switching surface, which will lead to unstable operation of the converter. In reflective
mode, the sate trajectories direct toward the switching surface on both side and will move
along the surface to the target operating point. In refractive mode, trajectories reach to the
switching surface on one side and away from the other side. The state will move around
the target operating point. Thus, based on the analysis in [106], the conditions leading to
rejective mode are given by
2
2
V ' off state ! 0 or V '
on state
0, V '2
on state
2
off state ! 0, V '
0
off state ! 0
(5.8)
2
V '
on state
0 or V '2
on state
2
off state ! 0 or V '
0, V '2
2
off state ! 0, V '
on state
!0
off state 0
(5.9)
where on-state and off-state indicate the corresponding value when the initial state is onstate and off-state, respectively.
off state
on state
initial state is off. According to (5.2), (5.3) and (5.6), if the initial state is on,
V '2
on state
2 k s1 k 2 )( x x ref )
(5.10a)
Chapter 5-158
on state
d 2
dt
on state
2 k s1 k1 )( x x ref )
2(k s1 k 2 )( x x ref )
on state
(5.10b)
dx
dt
( x x ref )
(5.10c)
on
2
2
where dx dt
on
off state
0 , dx dt
d 2
dt
off
off state
off state
2 k s 2 k 2 )( x x ref )
2 k s 2 k1 )( x x ref )
2(k s 2 k1 )( x x ref )
off state
(5.11a)
dx
dt
(5.11b)
( x x ref )
(5.11c)
off
By substituting (5.10) and (5.11) into (5.8) and (5.9), the regions of the control
parameters for rejective mode and reflective mode are given by (5.12) and (5.13),
respectively.
k1 k s 2 and k2 k s1
(5.12)
k1 k s1 and k2 k s 2
(5.13)
The conditions for refractive mode are within the ones outside the conditions of
(5.12) and (5.13).
intersection with the switching surface brings the operation closer to the target operating
point as illustrated in Fig. 5.6. A (xn, yn), B (xn+1, yn+1) and C (xn+2, yn+2) are three
subsequent intersections between the state trajectories and the switching surface, called
successor points. The condition for stable operation is given by
Chapter 5-159
S n S n 2
(5.14)
where Sn is the distance between A and the target point O (xref, yref),
S n2
xn xref ) 2 ( yn yref ) 2
and
Sn+2
is
the
distance
between
and
O,
S n2 2 x n 2 xref ) 2 ( y n 2 y ref ) 2 .
yn yref k ( xn xref ) 2
(5.15)
(5.16)
Chapter 5-160
k s1 k1 k s 2 k2
k s1 k2 k s 2 k1
(5.17)
(5.18)
Fig. 5.7 Stability analysis of the proposed uniform second-order switching surface with
different control parameters k1 and k2.
Fig. 5.7 summarizes the aforementioned analysis and presents k1 and k2 regions for
different operation modes. It can be observed that when k1 = ks1 and k2 = ks2, the switching
Chapter 5-161
surface is along the boundary of the reflective and refractive regions. Fig. 5.8 shows five
typical switching surfaces with specific values of k1 and k2. A and B are points on the
right and left sides of switching surfaces of 12 , 22 and 32 , and A and C locate on the two
sides of switching surfaces 42 and 52 . n2 (n = 1, 2, 3, 4, 5) and n2 indicate turn off/on
part of one specific switching surface above and below the load line, respectively. It can
be noted that the curved switching surfaces 12 , 32 , 42 and 52 will make arbitrary point
operate in reflective, stable refractive, unstable refractive and rejective mode, respectively.
When 22 is selected, which approximately follows the on/off state trajectory, the arbitrary
point A or B will reach the target operating point by two switching actions.
Chapter 5-162
vo io
io
vin
(5.19)
where vin is the input voltage, and vo and io are the output voltage and current, respectively.
Step 2 - Determination of x, y and ks1. For buck-boost converter, the control
variable x is firstly selected as the inductor current i L . As shown in Fig. 5.9(a), during on-
Chapter 5-163
state interval,
d vo
Lvo
d iL
RC vin
(5.20)
where L and C are the inductor and output capacitor, respectively, and R is the equivalent
load resistance.
By using (5.1), it can be shown that
y 2k s1 (i L i L , ref ) d i L
2k s1 1 2 1
( L i L C v o2 C v in v o )
L 2
2
(5.21)
1 2 1
L i L C v o2 C v in v o
2
2
(5.22)
L
2
(5.23)
k s1
in (iL iL ,ref )
d iL d t d i L
vo
ks 2
Lvin
2vo
(5.24)
(5.25)
1 vo io
1
io ) 2 C vo2,ref C vin vo ,ref
L(
2
2
vin
(5.26)
Chapter 5-164
(5.27a)
(5.27b)
S is turned off if
Fig. 5.10 Block diagram of the proposed uniform controller for buck-boost converter.
Chapter 5-165
(a) CCM.
(b) DCM.
Fig. 5.11 Switching surface 2 and the steady-state trajectories of buck-boost converter.
Chapter 5-166
The effect of the equivalent series resistance (ESR) of the output capacitor is taken
into account for the analysis as it is critical to the switching frequency variation.
voESR as the measured output and voact as the actual capacitor voltage.
Define
voESR voact iC RC
(5.28)
where iC is the capacitor current, iC = -io during the on-state period and iC = iL-io during the
off-state period.
ESR
yref
including ESR effect are given by
1
1
LiL 2 C (voact iC RC ) 2 C vin (voact iC RC )
2
2
(5.29)
1
1
L iL ,ref 2 C (voact, ref iC RC ) 2 C vin (voact,ref iC RC )
2
2
(5.30)
y ESR
ESR
yref
Fig. 5.11 presents the 2 and the steady-state trajectory of buck-boost converter
operated in CCM and DCM.
(5.31a)
(5.31b)
At steady-state, the ripple currents xmax xref and xref xmin are of the same value.
As points A and B are both on the on and off state trajectories, y1 = y2. Substitute
y1 y1ESR , y2 y2ESR , (5.26), (5.29) and (5.30) into (5.31), resulting in
y1ESR y2ESR
k1 k 2
ESR
y yref
k1 k 2
(5.32)
Chapter 5-167
RC C (vin vo )
xmin xmax
(5.33)
2 y
k1 k2
xmin_ RC 0 xmax_ RC 0
(5.34)
For buck-boost converter, when S is on, iL vin ton L , where ton is the on time.
When S is off, iL vo toff L , where toff is the off time. Therefore, the switching frequency
( k1 k2 )vo vin
L(vin vo )
in
in
vin 2y RC C (vin vo )
(5.35)
By substituting RC = 0 into (5.35) to obtain the switching frequency excluding the
effect of ESR as follows:
f s _ CCM _ RC 0
vo vin
2 y
2 L(vin vo )
k1 k2
(5.36)
When operated in DCM, x reaches to zero during the off-state period as indicated by
the points B (y2, 0) and C (y3, 0) shown in Fig. 5.11(b). In a similar way, it yields
RC C (vin vo )
xmax xref
(5.37)
Chapter 5-168
For buck-boost converter, the average inductor current is equal to xref, given by
0
1 L(vin vo )iL2,max
LiL
1 iL ,max LiL
I L iL
diL
diL
iL , max
Ts 0 vin
vo
2vin vo
Ts
(5.38)
2vo io
v v
L in o io
vin
RC C (vin vo )
2(k1 k2 )
(5.39)
When RC = 0
f s _ DCM _ RC 0
2voio
v v
2 y
L in o io
k1 k2
vin
(5.40)
Fig. 5.12 presents the switching frequency of buck-boost converter with the
proposed control scheme.
and reaches a constant value when the converter enters into the CCM if ideally RC = 0.
The switching frequency in DCM increases slightly with the ESR of the output capacitor,
while in CCM it drops with the increasing value of ESR. Therefore, an output capacitor
with low ESR is beneficial to reduce the variation of the switching frequency in CCM.
Chapter 5-169
38k
DCM CCM
RC increase
30k
Switching frequency (Hz)
34k
26k
22k
18k
14k
35k
34k
33k
RC increase
32k
31k
30k
0,17 0,22 0,27 0,32 0,37
Output current (A)
0.00E+00
RC = 0
1.40E-03
RC = 1.4 m
RC = 6 m
6.00E-03
RC = 10m
1.00E-02
RC = 20 m
2.00E-02
10k
0
0,5
1,5
2
2,5
3
Output current (A)
3,5
4,5
Fig. 5.12 Steady-state switching frequency of buck-boost converter with the controller.
1 2
1
C vo ,min L iL ,ref iL ,max 2 C vin vo ,min
2
2
(5.41a)
y2
1 2
1
C vo ,max L iL ,ref iL ,min 2 C vin vo ,max
2
2
(5.41b)
Chapter 5-170
vo ,max
(5.42)
vo ,min
(5.43)
2 L 2y
2 k1 k 2 L
. Thus, the average output
y and B
C k1 k 2
C k1 k 2
vo, av
d vo , av
d iL , ref
4 A BiL ,ref
vin
1
A BiL , ref
(5.44)
(5.45)
It reveals from (5.45) that the steady-state output voltage will be slightly decreased
with the increase of load.
loading condition when vin = 48 V, vo,ref = 48 V, y = 2.4 mV, k1 = 1.810-4 and k2 = 1.810 -4. It can be noted that the maximum variation of the average output voltage from
no load to rated load is 64 mV.
Chapter 5-171
48,010
Average output voltage (V)
48,000
47,990
47,980
47,970
47,960
47,950
47,940
47,930
0
0,5
1,5 2 2,5 3
Output current (A)
3,5
4,5
Fig. 5.13 Average output voltage versus output current of buck-boost converter with
proposed uniform control law (vin = 48 V, vo,ref = 48 V, y = 2.4 mV, k1 =1.810-4 and k2 = 1.810-4).
control method is implemented according to Fig. 5.10 by a digital method. The prototype
is tested under six kinds of load change conditions: a) output resistance is from 47 to12.3
, and vice versa; b) the value of output resistor reduces from 100 to 12.3 , and vice
versa, and (c) a large load variation with output resistance from 500 to 13.6 , and vice
versa.
Fig. 5.14(a) and Fig. 5.15(a) present waveforms of the output voltage vo, output
current io, inductor current iL and switching signal VGS under a load change from 1.02 A to
Chapter 5-172
3.9 A and vice versus. The converter operates in CCM under both loading condition. It
can be observed from the gate signal VGS that the output voltage approaches to the steadystate after two switching actions.
Chapter 5-173
(a)
(b)
Chapter 5-174
(c)
Fig. 5.14 Waveforms of dynamic response under increased loading condition. (a) RL
from 47 to 12.3 , (b) RL from 100 to 12.3 , (c) RL from 500 to 13.6 . (vo: (ac)
500 mV/div, io: 2 A/div, iL: 5 A/div, vGS: 20 V/div and Timebase: 100 s/div).
Chapter 5-175
(a)
(b)
Chapter 5-176
(c)
Fig. 5.15 Waveforms of dynamic response under reduced loading condition. (a) RL from
12.3 to 47 , (b) RL from 12.3 to 100 , (c) RL from 13.6 to 500 .(vo: (ac) 500
mV/div, io: 2 A/div, iL: 5 A/div, vGS: 20 V/div and Timebase: 200 s/div).
Fig. 5.16 shows the output voltage, output current and driving signal when start-up.
The switch is always off to release the energy stored in the inductor to the load to increase
the output voltage level before reaching steady-state. The start-up time is measured with
2.15 ms.
Fig. 5.17 presents the measured switching frequency at Rc = 1.4 m. With output
capacitor of low ESR, the switching frequency is found to vary 4.2 kHz when the converter
is operated from critical conduction mode to the rated load.
Chapter 5-177
Fig. 5.16 Waveforms of start-up period of buck-boost converter (vo: 50 V/div, io: 1 A/div,
vGS: 20 V/div and Timebase: 2 ms/div).
38k
36k
34k
32k
30k
Experimental
Experimentalresults
results
= 0)
Calculation
(R
Calculation (Rc=0)
C
Calculation(Rc=1.4m)
(RC = 1.4 m)
Calculation
28k
26k
24k
22k
20k
0
0,5
1,5
2
2,5
Output current (A)
3,5
Chapter 5-178
A uniform fast transient controller with second-order switching surface for basic dcdc converters is proposed. State variables such as capacitor voltage and inductor current
are transformed to Cartesian x-y plane to formulate a general form of switching criterion for
different types of dc-dc converters.
considering the component values of the power stage without any sophisticated
calculations. Stability analysis has been carried out by varying the control parameters in
different regions.
demonstrated with a buck-boost converter. A 48/48 V 190 W prototype has been built and
tested under both CCM and DCM conditions. It has been verified that the control method
addresses a complete operation and does not differentiate startup, transient, and steady-state
intervals.
The results of the large-signal response are in good agreement with the
theoretical predictions.
Chapter 6-179
CHAPTER 6
A DC-LINK MODULE FOR REDUCING DC-LINK CAPACITANCE
6.1 Introduction
capacitance in general capacitor-supported power electronic systems, which in turn has the
potential to be applied in the front-end ac-dc stage of high-voltage dc-dc converters.
Accordingly, a dc-link module consists of a dc-link capacitor and a voltage
compensator connected in series with the dc bus line is proposed. The compensator
processes the ripple voltage and reactive power only and thus can be implemented with
switches and capacitors of low voltage rating.
module is significantly reduced from the original one. Therefore, it allows the use of
alternatives (e.g., power film capacitor) with long lifetime and low power loss to replace ECaps with comparable size and cost.
Simulation on several types of power electronic converters and prototype testing on
a power factor corrector (PFC) verify the feasibility of the proposed concept.
Chapter 6-180
Fig. 6.1 Block diagram of a typical capacitor-supported power electronic conversion system.
Chapter 6-181
Fig. 6.2 illustrates the basic concept of the proposed dc-link module with reduced
dc-link capacitance.
power conversion stage. Typically, the previous stage is a bridge rectifier or PFC, which
generates a dc voltage and an ac ripple component.
connected in series with the dc-bus to generate an ac voltage vab that closely follows the
ripple voltage vC. Therefore, an ideal dc voltage VDC will appear at the two terminals of
the bus line. A much higher voltage ripple is allowed on the dc-link capacitor.
The value of dc-link capacitance depends on the designed maximum magnitude of
vab permitting the reduction of the value of the capacitor. The dc-link capacitor together
with the proposed voltage compensator forms a dc-link module that can be applied in
various capacitor-supported power electronic systems.
(6.1)
Id I A
(6.2)
where Vd and VC are the dc components of vd and vC, respectively, and Id and IA are the dc
component of id and iA, respectively.
An ac analysis of the circuit in steady-state operation is taken by assuming that
Chapter 6-182
iA (t ) I A sin 1t 1
(6.3)
id (t ) I d sin 2t 2
(6.4)
where iA and id are the ac components of id and iA, respectively, I A and I d are the
amplitudes of iA and id , respectively, and 1 and 2 are the frequencies of iA and id ,
respectively.
Thus, the ac component of vC, (i.e., vC ) and vab (i.e., vab ) can be expressed as
1
iA (t ) id (t ) dt
C
I
I
A sin 1t 1 90 d sin 2t 2 90
1C
2 C
vab (t ) vC (t )
(6.5)
Based on (6.4)-(6.5), the average power Pab provided by the voltage compensator in
a period T is given by
1 T
vab (t )id (t )dt
T 0
I I A T
d
sin 1 2 t 1 2 dt
21CT 0
Pab
and
(6.6)
for a special case when 1 2 and 1 2 . Therefore, the voltage compensator handles
reactive power only in all of other cases. For the special case mentioned, the dc-link
capacitance can be reduced by synchronization control of the phase 1 and 2 without the
proposed voltage compensator.
The apparent power of the voltage compensator is given by
Chapter 6-183
S ab
1
21C
1
2
I A I d
2 I d2 I d
(6.7)
Qab
1
21C
1
2
2
2
I A I d 2 I d2 I d
2
(1 2 ,or 1 2 and 1 = 2 )
(6.8)
The output terminal voltage (i.e.,vab) of the voltage compensator is only the voltage
ripple of the dc-link. Therefore, Sab presented by (6.7) is considerable small compared to
that of the specific main dc-link power conversion system. Especially, the apparent power
rating is reduced significantly compared to that of the solutions with parallel active circuits
discussed in Section 1.4.3.
6.4.1 Implementation
Fig. 6.3 shows the implementation of vab and its control method. vab is an dc-ac
converter consisting of a full-bridge (FB) and an output filter formed by the inductor Lf and
capacitor Cf.
voltage source. The gate signals for the switches S1-S4 in the FB are generated by a PWM
modulator. It should be noted that the power stage could be implemented by a half-bridge
for loads with unidirectional current flow. The voltage ripple on C is sampled by a scaling
factor of .
Chapter 6-184
extracted by a low-pass filter. The output of the low pass filter passes to a PI control block.
The output of the PI block, vos, is combined with the ripple voltage on C to compose the
modulating signal vm for the PWM modulator.
Power Stage
DS1 S2
S1
Ca
Lf
va
DS3 S4
S3
ia
Cf
DS4
a
iC
Front-end
stage
DS2
id
vab
vC
voltage
sense
vd
Load
PI
vfd
+
VC
vcon =
vC +
DC offset
Control Stage
vos
Ma
driving
vm
PWM
signals
controller
for S1-S4
Chapter 6-185
capacitor voltage vC, modulating signal vm, carrier signal vtri, and the voltage across Ca, va.
It should be noted that the control signal vcon may contain multiple frequency components
as it is obtained by scaling down vC.
ma1
I A
1CVtri
(6.9)
ma 2
I d
2CVtri
(6.10)
where is the scaling factor vcon / vC and Vtri is the amplitude of the tri-angular waveform
used for PWM.
Chapter 6-186
iLf
Lf
id
iLf
Lf
iCf
va
iCf
Cf
Ca
id
va
vab
Cf
Ca
vab
b
(a)
(b)
vC,max
2 vC
t
vC,min
Vtri Vm
t
va,max
2 va
va,min
t0
t1
t2
(c)
Fig. 6. 4 Operation of the voltage compensator: (a) operating mode when S2 and S3 are on,
(b) operating mode when S1 and S4 are on and (c) SPWM and the voltage across Ca.
To study the charging and discharging processes of Ca, t0 and t1 in Fig. 6.4 (c) are
defined as the two time instants when vC is across zero within one period. During t0-t1,
the capacitor Ca is being charged by the load current and its voltage increases from
minimum to maximum.
Chapter 6-187
1
Ca
t0
I d I d sin 2t 2 iCf (t )
ma1 sin 1t 1 90 ma 2 sin 2t 2 90 dt
I t m sin t 90 m sin t 90 dt
a2
1
1
2
2
d t0 a1
t
ma1 I d sin 1t 1 90 sin 2t 2 dt
t0
1
vCa ,min
Ca m I t sin t cos t dt
a2
d t
2
2
2
2
0
(6.11)
where vCa,min is the minimum voltage on Ca. During t0-t1, the net charge of the filter
capacitor Cf by iCf is zero, therefore, when 1 2 , the voltage ripple of Ca , 2 vCa , is
given by
2 vCa
t1
1
I d ma1 sin 1t 1 90 ma 2 sin 2t 2 90 dt
t0
Ca
m I
m I
a1 d sin 1t1 1 sin 1t0 1 a 2 d sin 2t1 2 sin 2t0 2
1Ca
2 Ca
(6.12)
For practical applications when 2 is much larger than 1 , the effect of the second
terms of (6.5) and (6.12) are negligible and sin 1t1 1 1 , sin 1t0 1 1 , therefore,
2 vCa
2ma1 I d
1Ca
(6.13)
The above equation is also applicable for the case when 2 is even multiples of 1 as
sin 2t1 2 sin 2t0 2 . The voltage across Ca is therefore presented by
vCa t VC a
ma1 I d
sin 1t 1
1Ca
(6.14)
Chapter 6-188
m I
vab t VC a a1 d sin 1t 1 ma1 sin 1t 1 90 ma 2 sin 2t 2 90
1Ca
(6.15)
ma21 I d
sin 21t 21
VC a ma1 sin 1t 1 90 ma 2 sin 2t 2 90
21Ca
The first term of (6.15) is used to cancel the dc-link voltage ripple while the second term is
a double frequency ripple that generates voltage variation on vd.
Cnorm meeting the design specification. Practically, the required one may be larger than
Cnorm to sustain ripple current stress. Moreover, the dc-link voltage ripple will increase
from 2 vC , nom to 2 vC due to the aging process with a decay of the capacitance value.
With the proposed voltage compensator, the selection of the dc-link capacitance C
is independent of the required dc-link voltage ripple, but is compromised with the allowable
voltage stress on the capacitor Ca and MOSFETs S1-S4. A smaller value of C requires
higher voltage ratings of Ca and S1-S4. Moreover, a boundary capacitance Cbd can be
determined based on specifications of power electronic systems, availability, cost and
volume of different type of capacitors. It provides guideline on the selection of capacitor
type. For instance, power film capacitors are applied in Selection 1 with a higher level of
the dc component of vCa, VCa, compared to that of Selection 2 in which E-caps are used.
Chapter 6-189
With the aid of the proposed voltage compensator, the required dc-link capacitance can be
reduced, making it possible to achieve long lifetime power electronic systems (i.e., by using
power film capacitors) as well as maintaining high power density and comparable low cost.
Fig. 6.5 VCa-C curve for capacitance selection of the dc-link capacitor ( vC ,nom -half of the
design specification of the dc-link voltage ripple, Cnom-required dc-link capacitance without
- dc-link capacitance after certain degree of aging, Cbd the voltage compensator, Cnom
boundary of the selected type of dc-link capacitor according to specifications, availability,
cost and volume, Vbd- value of VCa corresponding to Cbd.
revealed by (6.15), there is an undesirable voltage ripple with doubled frequency in vab,
Chapter 6-190
leading to variations in the output voltage of the proposed dc-link module. Therefore, the
value of Ca is designed to suppress the voltage ripple across the output terminals of the dclink module within the specification of 2 vC , nom .
As the capacitor Ca withstands a low voltage stress, there are many choices for
practical implementation. One choice is to use low voltage E-caps with high ripple current
and long lifetime. Unlike the ones with high voltage ratings, they are available and costeffective. Another choice is to use ceramic capacitor tank or low voltage film capacitors.
6.6.1 Simulations
Various type of power conversion systems are simulated with and without the
proposed dc-link module.
Table 6.1 tabulates the study cases. It covers both 400 V and
800 V dc-link systems with diode rectifier or PWM converter front-end stage and resistive
load, inductive load or switching load. Fig. 6.6 presents the simulation results accordingly.
It verifies the feasibility and applicability to apply the proposed dc-link module in various
power electronic systems.
Chapter 6-191
Descriptions
Case 1
Case 2
Case 3
Case 4
Case 5
Case 6
vCa (V)
(a) Simulation results with current source front-end and 400 V dc-link (IA = 5 A, Ia = 1 A,
ZL: 80+j0.063 , C: 450 V/ 40 F, Ca: 50 V/1000 F) (Case 1).
Chapter 6-192
vCa (V)
(b) Simulation on three-phase uncontrolled diode bridge rectifier with 800V dc-link voltage
(Po = 2 kW, load RL: 320 , C: 900 V/ 40 F, Ca: 100 V /220 F) (Case 2).
vCa (V)
(c) Simulation on boost PFC with controlled 400 V dc-link voltage (Po = 1 kW, RL: 160 ,
C: 450 V/ 100 F, Ca: 50 V/1000 F) (Case 3).
Chapter 6-193
vCa (V)
(d) Simulation on PWM rectifier with 800 V dc-link voltage and resistive load (Po = 2 kW,
RL: 320 , C: 900 V/ 50 F, Ca: 100 V/470 F) (Case 4).
vCa (V)
(e) Simulation on PWM rectifier with 800 V dc-link voltage and inductive load (Po = 2 kW,
load RL: 320 , load L: 1 H, C: 900 V / 50 F, Ca: 100 V /470 F) (Case 5).
Chapter 6-194
vCa (V)
(f) Simulation on Boost PFC with 400 V dc-link voltage and full-bridge converter load (Po
= 1 kW, Vo = 48 V, RL: 2.3 , C: 450 V/ 100 F, Ca: 50 V/1000 F) (Case 6).
Fig. 6.6 Simulation results of different application cases.
Chapter 6-195
voltage vab. It reveals that vab is in phase with the feedback voltage ripple signal, therefore,
in phase with the dc-link voltage ripple. The 450 V/940 F E-caps used in the PFC board
are replaced by a 450 V/ 110 F power film capacitor with the proposed voltage
compensator. Fig. 6.8(b) gives the captured waveforms tested at 500 W load.
It can be
Chapter 6-196
noted that the voltage ripple appears at the output terminal of the proposed dc-link module
is 3.9 V, while the one with E-cap is 4.8 V. The voltage ripple across the power film
capacitor in the proposed dc-link module is still high, which is cancelled by output voltage
of the compensator, resulting in a very low ripple component in the output terminals.
(b) Voltage ripples on the dc-link capacitor and the output of the dc-link module.
Fig. 6.8 Experimental verifications of a 400 V dc-link PFC front-end conversion
system prototype (C: 450 V/ 110 F, Ca: 63 V/940 F, 500 W load testing).
Chapter 6-197
Chapter 7-198
CHAPTER 7
CONCLUSIONS AND SUGGESTIONS FOR FURTHER RESEARCH
7.1. Summary of the Thesis
This thesis has proposed energy-efficient solutions for both low-to-high voltage and
high-to-low voltage dc-dc power converters. Based on system level considerations, a
uniform fast transient controller and a kind of dc-link capacitance reduction technique have
also been proposed.
By using a switched-capacitor snubber with adaptive energy, the proposed currentfed FB PWM converter achieves ZCS with minimum resonant energy under each loading
condition.
The operation principles of the snubber and the current-fed converter have
been investigated.
tested. It exhibits high efficiency from very light load to nominal load.
By using a symmetric multilevel circuit structure and an asymmetric three-level
circuit structure, two solutions have been proposed for high-to-low voltage power
conversions.
The voltage distributions on switch pairs of the multilevel converter are self-
balanced, thus the voltage stresses on them are the same and equal to a fraction of the input
voltage. While the voltage distributions on the two switch pairs of the TL converter are
different and controlled by duty cycles.
converters are the promising candidates for providing a single-step conversion from high
voltages (e.g., 1.5 kV, 3 kV) to low load voltages for the on-board applications in railway
systems. Two 2 kW prototypes with input voltage of 1500 V are built to verify the
theoretical analysis.
Chapter 7-199
By using axis transformation of the control state variables, a generalized secondorder switching surface, thus a uniform fast transient controller, has been proposed and
applicable for all basic dc-dc converters (i.e. buck converter, boost converter, buck-boost
converter, uk converter and SEPIC).
presented.
applied for various kinds of low voltage dc-dc converters distributed as loads of the highto-low voltage converters.
By connecting a voltage compensator in series with dc bus line, a dc-link module
has been proposed.
power film capacitors) without sacrificing converter performance, power density and costeffectiveness.
voltage stress only. Two prototypes have been built and implemented by analog and digital
methods, respectively.
experimental evaluations on a PFC have verified the theoretical predictions. The research
makes it possible to design high power density long lifetime cost-effective power electronic
systems.
conversion systems.
The major contributions of the research work described in this thesis can be
summarized to the following aspects.
1)
Proposed a new snubbering concept with adaptive snubber energy for achieving
Chapter 7-200
3)
Proposed a uniform second-order switching surface for all of the basic dc-dc
converters (i.e. buck converter, boost converter, buck-boost converter, uk
converter and SEPIC).
4)
5)
The research on the current-fed FB PWM converter has the potential to be applied
for medical X-ray high-voltage generators, which are dominant by series-parallel resonant
type converters up to now. It requires higher output voltage up to 150 kV and much lower
voltage ripple than the prototype designed. It is worthwhile to investigate the feasibility to
apply the proposed ZCS PWM converter for such application and compare the performance
with that of resonant converters.
The application of the proposed dc-link module in other power conversion systems,
such as solar inverters, EV battery chargers and LED road lighting ballasts, should be
investigated and experimentally verified. The lifetime testing of the developed system is
suggested and compared with that of the one with E-caps.
Appendix A-201
APPENDIX A
A.1 Derivation of Eq. (4.34)
The voltage between nodes A and B shown in Fig. 4.1(a) is tabulated in Table
A.1 during the corresponding intervals.
is given by
1- D1 Ts
DT
0
Ts
2 CsVC 2 / i p ( t6 )
VC 2Ts
i p (t6 )
t0
VC 2
2Cs
2 CsVC 2 / i p ( t8 )
(1 D2 )Ts 2CsVC 2
i p (t8 )
t dt VC 2
i p (t8 )
2
2Cs
(A.1)
C V 2
CV2
1
D1VC1 D2VC 2 Ts s C 2 s C 2 VC1tdl1
2
i p (t6 ) i p (t8 )
As the volt-second of the isolation transformer during one steady-state cycle is zero,
the average voltage of VCb is given by
VCb VC 2
2
Ts
i p (t 6 )Ts i p (t 8 )Ts
(A.2)
Appendix A-202
Table A.1 Voltage between nodes A and B and corresponding time intervals.
Time intervals
vAB
t0-tdl1
tdl1
VC2
tdl1-t4
D1T s
t dl1
2
VC1+VC2
t4-t6
t6-tvCs3=0
tvCs3=0-t8
t8- tvCs4=0
tvCs4=0-t12
1 D1 Ts
VC2
2C sVC 2
i p (t 6 )
vCs 3 VC 2
D1Ts 2C sVC 2
2
i p (t 6 )
2C s
2C sVC 2
(ip(t8)<0)
i p (t 8 )
1 D2 Ts
i p (t 6 )
vCs 3
2C sVC 2
i p (t8 )
i p (t 8 )
2C s
VC2
The overall volt-second value of the inductor Lf1 is equal to zero in one steady-state
cycle. According to Table A.2,
4
VC1 V
VC1 V
t
t
V
dt
1
cos
(
)
1 cos r 2 (t t3 ) Vo dt
r1
o
1
t m
t3
1
t2
V V iLf 1
V V
C1
Vo t2-3 Vot5-12 0
t t4 Vo dt Vot0-1 C1
m
Cr 1
m
t4
t5
(A.3)
Appendix A-203
C r 2 VC1 V
Llk i Lf 1
Llk C r1 t dl1
Vo
1
D1 2
2mi Lf 1Ts
VC1 V 2m
mTs
Ts mTs VC1 V
(A.4)
C r 2 VC1 V
Llk i Lf 1
Llk C r1 V
Vo
1
D1 2
2mi Lf 1Ts
VC1 V 2m
mTs
VC1 mTs VC1 V
(A.5)
Table A.2 Voltage across output inductor Lf1 and corresponding time intervals.
Time intervals
t0-t1
t1-t2
t2-t3
t dl1
mVC1 V
Llk (C r1 C r 2 )
m
D1Ts Llk (C r1 C r 2 ) Llk C r1
2
2m
m
Llk i Lf 1
t dl1
mVC1 V
Llk C r1
t3-t4
t4-t5
t5-t12
Llk i Lf 1
-Vo
V C 1 V
1 cos r1 (t t1 ) Vo
m
VC 1 V
Vo
m
2m
VC 1 V
1 cos r 2 (t t 3 ) Vo
m
C r1 (VC1 V )
mi L f 1
VC1 V i Lf 1
(t t 4 ) Vo
m
C r1
2 D1 Ts
2
C r1 (VC1 V )
mi L f 1
-Vo
Appendix A-204
The overall volt-second value of the inductor Lf2 is equal to zero in one steady-state
cycle. According to Table A.3 and (4.26)-(4.27), in a similar fashion as the derivations of
(A.4), one gets
mCsVC 2
4 Leq VC1 V
Vo
1
D2 2
VC 2 -V 2m
Lr Cr 2 VC 2 V Ts
iLf 2Ts
Llk iLf 2
m 2 Leq 1 D2 V
t
dl 2
Ts m VC 2 V Ts
Llk VC 2 V
(A.6)
Table A.3 Voltage across output inductor Lf2 and corresponding time intervals.
Time intervals
t0-t7
Llk i Lf 2
Ts
t dl 2
2 mVC 2 V
-Vo
t7-t8
Llk i Lf 2
D2Ts
t dl 2
2
mVC 2 V
VC 2 V
Vo
m
t8-tvCs4=0
2mC sVC 2
i Lf 2
i Lf 2
VC 2 V
t Vo
m
2m 2 C s
tvCs4=0-t11
t11-t12
1 D 2 Ts
2
2mC s VC 2
Leq C r 2
i Lf 2
Leq C r 2
-Vo
[i Sa 2 (t11 ) - i sec (t11 ) - i Lf 2 ] Z r 5 sin r 5 (t t11 ) V o
Publications -205
[1]
Huai Wang, Henry Chung, and Adrian Ioinovici, A new concept of high voltage
dc-dc conversion with asymmetric voltage distribution on switch pairs and hybrid
ZVS-ZCS scheme, IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2242-2259,
May 2012.
[2]
Huai Wang, Henry Chung, and Adrian Ioinovici, A class of high-input low-output
voltage single-step converters with low voltage stress on the primary-side switches
and high output current capacity, IEEE Trans. Power Electron., vol. 26, no. 6, pp.
1659-1672, Jun. 2011.
[3]
Huai Wang, and Henry Chung, A uniform nonlinear control method for dc-dc
converters with fast transient response, HKIE Trans., vol. 17, no. 4, Dec. 2010.
(Outstanding Paper Award for Young Engineers/Researchers, Hong Kong IE)
[4]
Huai Wang, Qian Sun, Henry Chung, Saad Tapuchi, and Adrian Ioinovici, A ZCS
Ting-ting Song, Huai Wang, Henry Chung, Saad Tapuhi, and Adrian Ioinovici, A
high-voltage ZVZCS dc-dc converter with low voltage stress, IEEE Trans. Power
Electron., vol. 23, no. 6, pp. 2630-2647, Nov. 2008.
[6]
Huai Wang, and Henry Chung, Use of a series voltage compensator for reduction
Publications -206
Conference Papers
[7]
Huai Wang and Henry Chung, A novel concept to reduce the dc-link capacitor in
PFC front-end power conversion systems, in Proc. IEEE Appl. Power Electron.
Conf., 2012, pp. 1192-1197.
[8]
Huai Wang and Henry Chung, Study of a new technique to reduce the dc-link
Huai Wang, Henry Chung and Adrian Ioinovici, Analysis and optimized design of
a new dc-dc converter with asymmetrical voltage distribution for stepping down
1500 V to 48 V, in Proc. IEEE Appl. Power Electron. Conf., 2011, pp. 593-599.
[10]
Huai Wang, Henry Chung and Adrian Ioinovici, A new concept of high input
voltage to low load voltage (1500V-48V) dc-dc conversion with hybrid ZVS-ZCS
and asymmetrical voltage distribution, in Proc. IEEE Energy Convers. Congr.
and Expo., 2010, pp. 3711-3718.
[11]
Huai Wang, Henry Chung and Adrian Ioinovici, Analysis and optimized design of
an efficient high-voltage converter with high output capacity, in Proc. IEEE Appl.
Power Electron. Conf., 2010, pp. 1904-1910.
[12]
Cheung V.S., Henry Chung and Huai Wang, Predictive control of buck converter
using nonlinear output capacitor current programming, in Proc. IEEE Energy
Convers. Congr. and Expo., 2009, pp. 491-498.
[13]
Huai Wang, Henry Chung, S. Tapuchi and Adrian Ioinovici, A class of single-step
high-voltage dc-dc converters with low voltage stress and high output current
Publications -207
capacity, in Proc. IEEE Energy Convers. Congr. and Expo., 2009, pp. 18681875.
[14]
Huai Wang, Henry Chung and Presse J., A unified derivation of second-order
switching surface for boundary control of dc-dc converters, in Proc. IEEE Energy
Convers. Congr. and Expo., 2009, pp. 2889-2896.
[15]
Huai Wang, Henry Chung, S. Tapuchi and Adrian Ioinovici, Modeling and
analysis of a current-fed ZCS full-fridge dc/dc converter with adaptive softswitching energy, in Proc. IEEE Appl. Power Electron. Conf., 2009, pp. 14101416.
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Ioinovici, A ZCS full-bridge PWM converter with self-adaptable soft-switching
snubber energy, in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 3001-3007.
[17]
Huai Wang, and Henry Chung, Hold-up time analysis of dc-link module with a
series voltage compensator, IEEE Energy Convers. Congr. and Expo., 2012.
(Submitted)
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[18]
Henry Chung and Huai Wang, A dc link module for reducing dc link
capacitance, International Patent Filed, PCT/CN2011/076955.
[19]
Henry Chung, and Huai Wang, Reduction of dc-link capacitance using series
voltage compensators, International Patent Application (Submitted for processing
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