Review of PN Junction
MOS Structure
Accumulation, cutoff, Inversion
MOS transistor
Threshold Voltage
CADENCE CONFIDENTIAL
Review of PN Junction
Drift current: electrons and holes move in an electric field
E field
(+)
(-)
holes
electrons
Si
2
Si
Si
Si
CADENCE CONFIDENTIAL
Review (cont)
PN junction built-in potential
E field
N
- V0
EC
EFp
EV
V0
Eip Ein
q
kT N A N D
ln
2
q ni
qV0
EFn
CADENCE CONFIDENTIAL
CADENCE CONFIDENTIAL
2 ( N a N d )
Wd
V0
q Na Nd
Width of depletion region with bias V:
2 ( N a N d )
V0 V
Wd
q Na Nd
5
CADENCE CONFIDENTIAL
Diode Equation
Forward bias: barrier lowered, diffusion current dominates
Reverse bias: barrier raised, only current is small drift
current of minority carriers
Diode only lets current flow in one direction
Diode equation:
I I 0 (e
qV / kT
1)
I0 = generation current
6
CADENCE CONFIDENTIAL
Capacitance:
A 2 q N d N a
Cj
2 V0 V N d N a
CADENCE CONFIDENTIAL
MOS structure
MOS: Metal-oxide-semiconductor
Gate: metal (or polysilicon)
Oxide: silicon dioxide, grown on substrate
CADENCE CONFIDENTIAL
qoxid
e
E0
qS
qS
EFm
EC
oxide
bandgap
8ev
Metal
Oxide
Ei
EFp
EV
p-type Si
CADENCE CONFIDENTIAL
qS
EFm
M
10
qF
Ei
EFp
EV
F = Fermi potential
(difference between EF
and Ei in bulk)
S = surface potential
S (p-type)
CADENCE CONFIDENTIAL
Flat-Band Voltage
Flat-band voltage
11
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P-type Si substrate
VB = 0
12
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Accumulation
Negative voltage on gate: attracts holes in substrate
towards oxide
EC
Ei
EFp
EV
VB = 0
13
CADENCE CONFIDENTIAL
Depletion
Positive voltage on gate: repels holes in substrate
Holes leave negatively charged acceptor ions
P-type Si substrate
Eox
EFm
qVG
EC
Ei
EFp
EV
VB = 0
14
CADENCE CONFIDENTIAL
dQ qN A dx
dQ
dx
Find change in surface potential to displace dQ by distance xd
(Poisson equation):
d x
15
dQ
Si
d xqN A
dx
Si
CADENCE CONFIDENTIAL
xd
qN A x
dS 0 2 Si dx
F
qN A xd2
S F
2 Si
Result:
xd
16
2 Si S F
qN A
CADENCE CONFIDENTIAL
Q qN A xd
Q 2qN A Si S F
17
CADENCE CONFIDENTIAL
Inversion
Increase voltage on gate, bands bend more
Additional minority carriers (electrons) attracted from
substrate to surface
Forms inversion layer of electrons
Surface becomes n-type
VG >> 0
EC
Eox
P-type Si substrate
VB = 0
18
electrons
qVG
EFm
Ei
EFp
EV
CADENCE CONFIDENTIAL
Inversion
Definition of inversion
Point at which density of electrons on surface equals
density of holes in bulk
Surface potential is same as F, but different sign
EC
Remember:
qF
qF = EF - Ei
19
qS = -qF
Ei
EFp
EV
CADENCE CONFIDENTIAL
MOS transistor
Add source and drain terminals to MOS capacitor
Transistor types
NMOS: p-type substrate, n+ source/drain
PMOS: n-type substrate, p+ source/drain
N+
source
20
N+
drain
P+
source
P+
drain
P-substrate
N-substrate
NMOS
PMOS
CADENCE CONFIDENTIAL
MOS Transistor
Important transistor physical characteristics
Channel length L
Channel width W
Thickness of oxide tox
tox
L
21
CADENCE CONFIDENTIAL
Vd=0
source
drain
depletion
region
P-substrate
VB = 0
22
CADENCE CONFIDENTIAL
Vd=0
source
drain
depletion
region
P-substrate
inversion
layer
23
VB = 0
CADENCE CONFIDENTIAL
PMOS Enhancement
24
NMOS with
Bulk Contact
CADENCE CONFIDENTIAL
Threshold voltage
Threshold voltage (VT0): voltage between gate and source
required for inversion
Transistor is off when VGS < VT0
Components:
Work function difference between gate and channel
(Flat-band voltage)
Gate voltage to change surface potential
Gate voltage to offset depletion charge
CADENCE CONFIDENTIAL
VT 0 GC
26
CADENCE CONFIDENTIAL
VT 0 GC 2 F
27
CADENCE CONFIDENTIAL
So:
Q 2qN A Si S F
QB 0 2qN A Si 2 F
QB 2qN A Si 2 F VSB
Due to larger depletion region
28
CADENCE CONFIDENTIAL
VT 0
29
QB
GC 2 F
Cox
CADENCE CONFIDENTIAL
VT 0
30
QB 0 Qox
GC 2 F
Cox Cox
CADENCE CONFIDENTIAL
Threshold voltage
General form (non-zero substrate bias):
QB Qox
VT GC 2 F
Cox Cox
Can also write as:
QB QB 0
VT VT 0
Cox
VT VT 0
Substrate-bias
coefficient
31
2 F VSB 2 F
2qN A Si
Cox
CADENCE CONFIDENTIAL
Cox Cox
If VSB 0 (non-zero substrate bias)
VT VT 0
2 F VSB 2 F
2qN A Si
Cox
Threshold voltage increases as VSB increases!
32
CADENCE CONFIDENTIAL
33
NMOS
PMOS
F < 0
F > 0
QB < 0
QB > 0
>0
<0
VSB > 0
VSB < 0
CADENCE CONFIDENTIAL
Body effect
Body effect: Voltage VSB affects threshold voltage of
transistor
Body normally connected to ground for NMOS, VDD for PMOS
Raising source voltage increases VT of transistor
Implications on circuit design
A
Vx
If Vx > 0,
VSB (A) > 0,
VT(A) > VTO
B
VT0
34
CADENCE CONFIDENTIAL
VT 0
35
qN I
Cox
CADENCE CONFIDENTIAL
5 Minutes Break
36
CADENCE CONFIDENTIAL
CADENCE CONFIDENTIAL
38
CADENCE CONFIDENTIAL
Cutoff Region
VS
VG
source
VD
drain
depletion
region
substrate
VB
CADENCE CONFIDENTIAL
Linear mode
When VGS>VT, an inversion layer forms between drain
and source
Current IDS flows from drain to source (electrons travel
from source to drain)
Depth of channel depends on V between gate and
channel
Drain end narrower due to larger drain voltage
Channel
(inversion layer)
source
Vg > VT0
Vd < VGS-VT0
drain
depletion
region (larger at
drain end)
P-substrate
VB = 0
40
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CADENCE CONFIDENTIAL
QI ( y ) Cox VGS VT V ( y )
dy
dR
W nQI ( y )
Where W is width of channel and n mobility of
electron.
42
CADENCE CONFIDENTIAL
ID
dV I D dR
dy
W n QI ( y )
I
0
43
CADENCE CONFIDENTIAL
W
2
1
VGS VT VDS 2 VDS
I D nCox
L
Device transconductance:
Process transconductance:
W
kn n nCox
L
k n' n Cox
W
2
1
VGS VT VDS 2 VDS
ID k
L
'
n
44
CADENCE CONFIDENTIAL
Saturation mode
When VDS = VGS - VT:
No longer voltage drop of VT from gate to substrate at drain
Channel is pinched off
source
pinch-off point
45
Vg > VT0
Vd > VGS-VT0
drain
depletion
region
VB = 0
CADENCE CONFIDENTIAL
W
2
I D nCox VGS VTN
L
1
2
46
CADENCE CONFIDENTIAL
VGS3
Linear
VGS2
VGS1
Saturation
Drain voltage VDS
47
CADENCE CONFIDENTIAL
Saturation
ID (mA)
VGS = 4V
0.0
VGS = 3V
1.0
2.0
3.0
VDS (V)
VGS = 2V
VGS = 1V
4.0
5.0
(a) ID as a function of VD S
0.020
ID
Triode
Square Dependence
VGS = 5V
0.010
Subthreshold
Current
0.0
2.0
VT1.0
VGS (V)
3.0
48
CADENCE CONFIDENTIAL
MOSFET Capacitances
Oxide Capacitance
Gate to Source overlap
Gate to Drain overlap
Gate to Channel
Junction Capacitance
Source to Bulk junction
Drain to Bulk junction
49
CADENCE CONFIDENTIAL
Oxide capacitances
source
Ldrawn
drain
LD
Overlap capacitances
gate electrode overlaps source and drain regions
LD is overlap length on each side of channel
50
CADENCE CONFIDENTIAL
Oxide capacitances
Channel capacitances
Gate-to-source: Cgs
Gate-to-drain: Cgd
Cgs
source
Cgd
Cgb
drain
Gate-to-bulk: Cgb
Cutoff:
No channel connecting source and drain
Cgs = Cgd = 0
Cgb = CoxWLeff
Total channel capacitance CC = CoxWLeff
51
CADENCE CONFIDENTIAL
Oxide capacitances
Linear mode
Channel spans from source to drain
Capacitance split equally between S and D
1
CGS C oxWLeff
2
1
CGD C oxWLeff
2
CGB 0
2
CGS C oxWLeff
3
CGB 0
52
CADENCE CONFIDENTIAL
Oxide capacitances
Cg,total
(no overlap)
53
CADENCE CONFIDENTIAL
Junction Capacitance
CADENCE CONFIDENTIAL
Junction Capacitance
For a P-N junction:
If V=0, Cap/area =
General form:
A 2 q N d N a
Cj
2 V0 V N d N a
q Si N d N a
C j0
2V0 N d N a
Cj
AC j 0
V
1
V0
CADENCE CONFIDENTIAL
Junction Capacitance
Junction with substrate
Bottom area = W * LS (length of drain/source)
Sidewall facing channel: area = W * Xj
Total cap = Cj
CADENCE CONFIDENTIAL
Characteristics of Inverters
Resistive Load Inverters
VTC, Delay, Power Dissipation
Pseudo-NMOS Inverters
Depletion Load Inverters
CADENCE CONFIDENTIAL
VDD
Vout
VDD
Cload
Vout
time
CADENCE CONFIDENTIAL
VDD
Vout
VDD
Vout
VDD-VT
Cload
time
NMOS remains on until VGS = VT
CADENCE CONFIDENTIAL
Gnd
S
D
Vout
Cload
Gnd
Vout = VDD
Vout
Cload
60
CADENCE CONFIDENTIAL
PMOS summary
Transfers logic 1 completely
Does not transfer logic 0 completely
Result:
NMOS used for pulldown, PMOS for pullup
61
CADENCE CONFIDENTIAL
Inverter Operation
Inverter is simplest digital logic gate
0
1
1
0
In Out
0 1
1 0
Resistive-load
Pseudo-NMOS
CMOS
Important characteristics
Speed (delay through the gate)
Power consumption
Robustness (tolerance to noise)
Area and process cost
62
CADENCE CONFIDENTIAL
Inverter
Vout
Ideal digital inverter:
ideal
VDD
Vout
actual
Vin
63
VDD
CADENCE CONFIDENTIAL
VDD
VOH
Ideally,VOH = VDD,VOL = 0
Difference (VOH-VOL) is the voltage
swing of the gate
Vout
VOL
Vin
64
VDD
CADENCE CONFIDENTIAL
Inverter threshold
VOH
Vout
Vout=Vin
VTH
VOL
Vin
65
VDD
CADENCE CONFIDENTIAL
Noise Margins
VIL and VIH measure effect of
input voltage on inverter
output
VOH
Slope = -1
Vout
VOL
VIL VIH
VDD
Vin
66
CADENCE CONFIDENTIAL
interconnect
1
VOH
VOL
0
NML
VIH
VIL
CADENCE CONFIDENTIAL
Vout
dVout
f Vin
Vnoise
dVin
CADENCE CONFIDENTIAL
Vin
VDD/2
Vss
VDD
Vout
VDD/2
Vss
t0 t1
t2 t3
tplh = t3 - t2,
tp = (tphl+tplh)
CADENCE CONFIDENTIAL
tR
t0 t1
t2 t3
V90%
V10%
t F = t1 - t 0
tR = t3 - t2
70
CADENCE CONFIDENTIAL
Ring oscillator
Ring oscillator circuit: standard method of comparing delay from
one process to another
Odd-number n of inverters connected in chain: oscillates with
period T (usually n >> 5)
VOH
V1
V3
V2
V1
V3
V2
V50%
Cload
71
Cload
1
1
f
,
T 2nt p
1
tp
2nf
CADENCE CONFIDENTIAL
Resistive-load inverter
Requires only NMOS transistor and
resistor
VDD
When Vin = 0:
Vout VDD
Vin
Vout
72
Gnd
Remember: if body terminal
not shown, it is connected to
gnd for NMOS, VDD for
PMOS
CADENCE CONFIDENTIAL
Vout
Vin=0
VOH = VDD
Gnd
73
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VDD
(because ID = Iload)
(VDD VOL )
ID
R
(VDD VOL )
2
k ' WL [(VDD VT )VOL 12 VOL ]
R
Iload
Vout
Vin=VDD
ID
Gnd
1
VOL
' W
Rk L
74
CADENCE CONFIDENTIAL
75
CADENCE CONFIDENTIAL
VDD Vout 1
2
2 kn Vin VT
R
2
Vout VDD 12 Rkn Vin VT
Take derivative of Vout with respect to Vin, set to -1
dVout
Rkn Vin VT 1
dVin
1
Vin VIL
VT
Rkn
76
CADENCE CONFIDENTIAL
VDD Vout
2
kn Vin VT Vout 12 Vout
R
2
VDD Vout kn RVin VT Vout 12 kn RVout
(1)
dVout
dVout
dVout
kn RVin VT
kn RVout kn RVout
dVin
dVin
dVin
8VDD
1
VIH VT
3kn R kn R
77
CADENCE CONFIDENTIAL
I D 12 k ' WL Vin VT
78
CADENCE CONFIDENTIAL
Vin=4V
Vin=3V
Vin=2V
VDD
Vout
VDD
R
Vin=1V
VOL
Vout = VDS
VDD
0
1
Plot IDS of transistor and Iload of resistor vs. Vout
2 Vin 3
79
CADENCE CONFIDENTIAL
Vin=4V
small R
Vin=3V
VDD
Vin=2V
Vout
VDD
R
large
R
small R
large
R
Vin=1V
Vout = VDS
VDD
2 Vin 3
80
CADENCE CONFIDENTIAL
81
CADENCE CONFIDENTIAL
I load
VDD VOL ,
P IV
R
V V V
P1 DD OL DD
R
82
CADENCE CONFIDENTIAL
IR
ID
R
Cload
IR
Cload
83
Need large IR
CADENCE CONFIDENTIAL
I avg
td
dV
C
,
dt
V1
C
0 dt V I avg dV
0
C
V1 V0
td
I avg
84
C
dt
dV
I avg
For rise delay:
V0 = 0, V1 = VDD/2
For fall delay:
V0 = VDD, V1 = VDD/2
CADENCE CONFIDENTIAL
Vin
Vout
Beginning of transition:
Vout VOL ,
End of transition:
VDD VOL
IC
R
Vout VDD ,
1
2
Average current:
I avg
Delay:
VDD
IC
2R
3VDD 2VOL
4R
Cload
4 RCload
V1 V0 , t plh
td
12 VDD VOL
I avg
3VDD 2VOL
85
CADENCE CONFIDENTIAL
IC 0 12 kn VDD VT
2
2
I C1 k n VDD VT 12 VDD 14 VDD
k n 14 VDD
12 VT VDD
Average current:
I avg
1
2
I C 0 I C1
Delay:
Cload
Cload
V1 V0 , t phl
td
I avg
I avg
86
12 VDD
CADENCE CONFIDENTIAL
Large area
Hard to make large resistance values on chip
87
CADENCE CONFIDENTIAL
Pseudo-NMOS inverter
Replace resistor with always-on PMOS
transistor
Easier to implement in standard process
than large resistance value
VDD
G
VGS,P = -VDD
S
D
Vout
Vin
Gnd
Remember:
VT(PMOS) < 0
88
CADENCE CONFIDENTIAL
VDD
Vin = 0
NMOS in cutoff: no drain current
Vout
Gnd
89
CADENCE CONFIDENTIAL
I Dn
k V
n
DD
VTn VOL V
1
2
2
OL
I Dp k p VDD VTp
1
2
(neglecting l)
1
2
90
CADENCE CONFIDENTIAL
Vin=3V
Vin=2V
Vin=4V
VGS=-VDD
Vin=1V
VDS = Vout
VDD
91
CADENCE CONFIDENTIAL
Vin=3V
VDD
Vin=2V
Vout
Vin=4V
Vin=1V
Vout = VDS
VDD
2 Vin 3
92
CADENCE CONFIDENTIAL
Depletion-load inverter
Depletion-load inverter: uses depletion
NMOS transistor as load
VDD
VGS = 0 > VT
VGS = 0
D
S
Vout
Vin
Gnd
93
CADENCE CONFIDENTIAL
Depletion-load inverter
2
knl VTl knd VDD VTd VOL 12 VOL
2
CADENCE CONFIDENTIAL
95
CADENCE CONFIDENTIAL
Regions of Operation
Noise margin
Inverter capacitances
Delay, Rise and Fall time
CADENCE CONFIDENTIAL
CMOS Inverter
Complementary NMOS and PMOS
devices
VDD
Vin
Vout
Gnd
Ratioless logic
97
CADENCE CONFIDENTIAL
NMOS
Vin=3V
VDD
Vin=2V
Vout
Vin=4V
Vin=1V
Vout = VDS
VDD
2 Vin 3
CADENCE CONFIDENTIAL
NMOS transistor:
Cutoff if Vin < VTN
Linear if Vout < Vin VTN
Vin
Vout
PMOS transistor
Cutoff if (Vin-VDD) < VTP Vin < VDD+VTP
Linear if (Vout-VDD)>Vin-VDD-VTP Vout>Vin - VTP
Sat. if (Vout-VDD)<Vin-VDD-VTP Vout < Vin-VTP
99
CADENCE CONFIDENTIAL
P linear
N sat
P cutoff
N linear
P sat
N sat
P sat
N linear
100
CADENCE CONFIDENTIAL
VDD
Increase W of PMOS
kp increases
VTC moves to right
kp=kn
kp=5kn
Vout
kp=0.2kn
VDD
Increase W of NMOS
kn increases
VTC moves to left
For VTH = VDD/2
kn = kp
Wn 2Wp
Vin
101
CADENCE CONFIDENTIAL
102
CADENCE CONFIDENTIAL
kp
kn
2
VGS ,n VT 0,n 2VGS , p VT 0, p VDS , p VDS , p 2
2
2
kn
Vin VT 0,n 2 k p 2Vin VDD VT 0, p Vout VDD Vout VDD 2
2
2
dV
dV
kn Vin VT 0,n k p Vin VDD VT 0, p out Vout VDD Vout VDD out
dVin
dVin
VIL
103
1 kR
Solve simultaneously with KCL to find VIL
kR
kn
kp
CADENCE CONFIDENTIAL
kp
kn
2
2
2VGS ,n VT 0,n VDS ,n VDS ,n VGS , p VT 0, p
2
2
kp
kn
2
2
2Vin VT 0,n Vout Vout Vin VDD VT 0, p
2
2
dV
dV
kn Vin VT 0,n out Vout Vout out k p Vin VDD VT 0, p
dVin
dVin
VIH
kR
kn
kp
CADENCE CONFIDENTIAL
kp
kn
2
VGS ,n VT 0,n VGS , p VT 0, p 2
2
2
kp
kn
2
Vin VT 0,n Vin VDD VT 0, p 2
2
2
VDD VT 0, p
kR
1
105
kR
kn
kp
1
kR
CADENCE CONFIDENTIAL
VDD VT 0, p
kR
1
kR
kn
kp
1
kR
k R ,ideal
k R,ideal 1
VDD 2 VT 0, p
VDD 2 VT 0,n
W
L p n
2. 5
W
p
L n
106
CADENCE CONFIDENTIAL
1
3VDD 2 VT 0
8
VIH
1
5VDD 2 VT 0
8
107
CADENCE CONFIDENTIAL
Csb,p
Cap on node f:
Cgd,p
Cdb,p
Cgd,n
Cdb,n
Cgs,n
Csb,n
Vin
f
Cint
Cg
Junction cap
Cdb,p and Cdb,n
Gate capacitance
Cgd,p and Cgd,n
Interconnect cap
Receiver gate cap
Gnd
108
CADENCE CONFIDENTIAL
C j V
,
C
j0
m
2 N a N d 0
V
1
0
Non-linear, depends on voltage across junction
Use Keq factor to get equivalent capacitance for a voltage
transition
CADENCE CONFIDENTIAL
C gd , p C gd ,n CoxWL D
However, also need to consider Miller effect ...
110
CADENCE CONFIDENTIAL
Vout
Vin
2Cgd1
C gd , p C gd ,n 2CoxWL D
111
CADENCE CONFIDENTIAL
Cint
ox
tox
WL
CADENCE CONFIDENTIAL
CADENCE CONFIDENTIAL
Vout
Cload
114
t PHL
Cload
VDD 12 VDD
I avg
t PLH
Cload
I avg
12 VDD VSS
CADENCE CONFIDENTIAL
Cload
dV
I C
dt
I D ,n Cload
115
dVout
dt
VDD/2
t0 t1 t2
116
CADENCE CONFIDENTIAL
V1=VDD
I1
V2=VDD
t PHL
CloadVDD
2
k n VDD VTn
t PLH
117
CloadVDD
k p VDD VTP
t1
t2
Iavg = I1
CADENCE CONFIDENTIAL
VOH VT 0 , n
dV
out
VOH
2CLVT 0,n
t1 t0
2
kn (VOH VT 0,n )
118
CADENCE CONFIDENTIAL
2
I DS kn (VOH VT 0,n )Vout 12 Vout
t2 t1 CL
(VOH VOL ) / 2
VOH VT 0 , n
kn (VOH
dVout
2
VT 0,n )Vout 12 Vout
kn (VOH VT 0,n )
(VOH VOL ) / 2
119
CADENCE CONFIDENTIAL
(t1-t0) + (t2-t1)
2VT 0,n
4(VOH VT 0,n )
CL
t PHL
ln
1
120
CADENCE CONFIDENTIAL
t PLH
121
k p (VOH
4(VOH VOL VT 0, p )
2 VT 0, p
CL
ln
1
VOH VOL
VOL VT 0, p ) VOH VOL VT 0, p
CADENCE CONFIDENTIAL
122
CADENCE CONFIDENTIAL
fall,rise
123
CV
I avg
CADENCE CONFIDENTIAL
124
CADENCE CONFIDENTIAL
t0 t1 t2
125
CADENCE CONFIDENTIAL
tpHL(ns)
Empirical equations:
tr
2
t phl (actual) t phl ( step)
2
tf
t plh (actual) t ( step)
2
2
plh
trise(ns)
126
CADENCE CONFIDENTIAL
127
CADENCE CONFIDENTIAL
Switch-level model
RP
A
128
VDS
I D Vout 12VDD
R
A
CL
CADENCE CONFIDENTIAL
Switch-level model
Delay estimation using switch-level model (for general
RC circuit):
R
n
CL
dV
C
I C
dt dV
dt
I
V
RC
I
dt
dV
R
V
V1
RC
t1 t0 t p
dV
V
V0
V1
t p RCln(V1 ) ln(V0 ) RC ln
V0
129
CADENCE CONFIDENTIAL
Switch-level model
Delay estimation using switch-level model (for
general RC circuit):
R
n
CL
dV
C
I C
dt dV
dt
I
V
RC
I
dt
dV
R
V
V1
RC
t1 t0 t p
dV
V
V0
V1
t p RCln(V1 ) ln(V0 ) RC ln
V0
130
CADENCE CONFIDENTIAL
Switch-level model
V1
12 VDD
t p RC ln RC ln
VDD
V0
t p RC ln( 0.5)
t phl 0.69RnC L
t plh 0.69R p CL
131
Standard RC-delay
equations
CADENCE CONFIDENTIAL
Static CMOS
Complementary pullup network
(PUN) and pulldown network
(PDN)
Only one network is on at a time
PUN: PMOS devices
VDD
In1
In2
In3
PUN
Why?
PDN: NMOS devices
Why?
PUN and PDN are dual
networks
Output is always connected to
VDD or Gnd
132
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
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Dual Networks
Example: NAND gate
Dual networks:
parallel connection in PDN = series
connection in PUN, vice-versa
If CMOS gate implements logic
function F:
PUN implements function F
PDN implements function G = F
133
parallel
B
series
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NAND gate
NAND function: F = AB
PUN function: F = A B = A + B
Or function (+) parallel connection
Inverted inputs A, B PMOS transistors
PDN function: G = F = A B
And function () series connection
Non-inverted inputs NMOS transistors
134
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NOR gate
PUN: F = A+B = AB
PDN: G = F = A+B
135
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136
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F
F
A
A
B
gnd
137
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A
A
138
B
B
A
B
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1
W
139
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0
Transistors in parallel resistances in parallel
Effective resistance = R
Effective width = 2W
140
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Equivalent Inverter
Equivalent inverter
Represent each gate as an inverter with appropriate device width
Include only transistors which are on or switching
Calculate VTH, delays, etc using inverter equations
141
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For VIL and VIH, only the worst case is interesting since
circuits must be designed for worst-case noise margin
For delays, both the maximum and minimum must be
accounted for in race analysis
142
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143
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WP
WP
WN
WP
WN
WN
144
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145
WP
Transistor equations
WP
Equivalent inverter
WNB
F
WN
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F = A(B+C)
146
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WP
C
WP
F
A
B
WN
WN C
WN
WP
WN
147
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Transistor Sizing
Sizing for switching threshold
All inputs switch together
148
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A
B
FanIn: Quadratic Term due to:
C
D
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
tp = a1 FI + a2 FI 2 + a3 FO
149
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tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
5
fan-in
tpLH
9
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Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
151
In3
M3
C3
In2
M2
C2
In1
M1
C1
Distributed RC-line
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critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
152
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
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153
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CL
154
CL
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Transistor ordering
Critical signal is latest-arriving signal to gate
Put critical signals closest to output
Stack nodes are discharged by early signals
Reduced body effect on top transistor
155
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156
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5 minute break
157
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Transmission gate
MUX
Tristate Inverter
D Latch, MS register
158
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CMOS disadvantages
For N-input CMOS gate, 2N transistors required
Each input connects to an NMOS and PMOS transistor
Large input capacitance: limits fanout
159
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Pseudo-NMOS logic
Pseudo-NMOS: replace PMOS PUN with single always-on PMOS
device
Same problems as pseudo-NMOS inverter:
VOL larger than 0
static power when PDN is on
Advantages
Replace large PMOS stacks with single device
Reduces overall gate size, input capacitance
Especially useful for wide-NOR structures
160
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161
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Equivalent Resistance
0V
Vin
Vout
VDD
162
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Req,n
VDD Vout
1
2
PMOS sat:
Req, p
163
VDD Vout
1
2
k p VDD Vtp
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PMOS lin:
Req,n
Req, p
164
VDD Vout
1
2
2VDD Vout
2
k p 2VDD VTP VDD Vout VDD Vout
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Req ,n
NMOS off:
PMOS lin:
165
Req, p
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Equivalent resistance
Equivalent resistance Req is
parallel combinaton of Req,n
and Req,p
Req is relatively constant
Req,p
Req,n
Req
VTp
Vcc-VTn VDD
Vout
166
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Resistance Approximations
Req,n
k n VDD Vtn
Req, p
k p VDD Vtp
1
Req
kn VDD Vtn k p VDD Vtp
167
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F = A if S
168
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VDD
VDD
M2
F
S
M1
B
GND
S
169
In1
In2
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B
M2
A
F
M1
M3/M4
B
170
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Switch logic
Can implement Boolean formulas as networks of switches.
Can build switches from MOS transistorstransmission gates.
Transmission gates do not amplify but have smaller layouts.
171
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Types of switches
n-type
complementary
172
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VDD
VDD - Vt
VDD
173
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VDD
VDD - Vt
VDD
174
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VDD
VDD - Vt
VDD -2 Vt
VDD
175
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176
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177
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178
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N transistors instead of 2N
Ratioless
179
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180
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181
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182
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Tristate Inverter
Tri-state inverters : 0 1 Z
tri-state
inverter
en
When en=0, F is
floating
en
183
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Memory elements
Stores a value as controlled by clock.
184
capacitance (dynamic);
feedback (static).
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185
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186
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Clock terminology
Clock edge: rising or falling transition.
187
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clock
data
188
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Dynamic latch
189
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Latch characteristics
Uses complementary transmission gate to ensure that storage
node is always strongly driven.
Latch is transparent when transmission gate is closed.
Storage capacitance comes primarily from inverter gate
capacitance.
190
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Latch operation
191
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192
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Non-dynamic latches
Must use feedback to restore value.
193
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Re-circulating latch
Static on one phase:
LD
2
LD
2
194
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Clocked inverter
circuit
symbol
195
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196
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197
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198
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Flip-flops
Not transparentuse multiple storage elements to isolate
output from input.
Major varieties:
199
master-slave;
edge-triggered.
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Master-slave flip-flop
master
slave
200
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Master-slave operation
= 0: master latch is disabled; slave latch is enabled, but
master latch output is stable, so output does not change.
= 1: master latch is enabled, loading value from input; slave
latch is disabled, maintaining old output value.
201
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Signal skew
202
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b
circuit
a
stable
stable
stable
time
5
10
timing diagram
203
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Clock skew
Clock must arrive at all memory elements in time to load data.
204
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205
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206
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static power
Static power consumption:
Static current: in CMOS there is no static current as long as Vin < VTN
or Vin > VDD+VTP
Leakage current: determined by off transistor
Influenced by transistor width, supply voltage, transistor threshold
voltages
VDD
VDD
Ileak,p
Vss
VDD
VDD
Vss
Ileak,n
207
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dVout
VDD C L
dt
dt
0
VDD
C LVDD dVout
0
Evdd C V
2
L DD
2
Pdyn C LVDD
f
208
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Pdyn C V
2
L DD
Observations
Does not (directly) depend on device sizes
Does not depend on switching delay
Applies to general CMOS gate in which:
Switched capacitances are lumped into CL
Output swings from Gnd to VDD
Input signal approximated as step function
Gate switches with frequency f
209
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Imax: depends on
saturation current
of devices
VDD
Imax
Vout
ID
Vin
210
VDD
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Imax
Esc VDD
Psc
211
I m axt f t r t f
I m axt r
VDD
VDD I m ax
2
2
2
tr t f
2
VDD I m ax f
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2
L DD
tr t f
f VDD I m ax
2
Energy-delay product:
f VDD I leak
212
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Power reduction
Reducing dynamic capacitive power:
Lower the voltage!
Quadratic effect on dynamic power
Reduce capacitance
Short interconnect lengths
Drive small gate load (small gates, small fan-out)
Reduce frequency
Lower clock frequency -> use more parallelism
Lower signal activity
213
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Power reduction
Reducing short-circuit current:
Fast rise/fall times on input signal
Reduce input capacitance
Insert small buffers to clean up slow input signals before sending
to large gate
214
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Inverter design
Consider chain of minimum-sized inverters:
Wp, Wn
Wp, Wn
Cload
Wp, Wn
Cload
Wp, Wn
Cload
Cload
Delay of single
inverter is tp0
2Wp, 2Wn
2Cload
215
2Wp, 2Wn
2Cload
2Wp, 2Wn
2Cload
2Cload
What is new
inverter delay?
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delay
Including interconnect
capacitance
size
216
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Inverter as a buffer
Consider minimum-size inverter driving load Cload:
Wp,Wn
Cg
Cload
Delay of inverter:
Gate cap of min-size inverter = Cg
Delay of min-size inverter driving another min-size inverter =
tp0
Cload xC g ,
217
t p xt p 0
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Inverter as buffer
Example:
Assume tp0 = 1ns
Wp,Wn
Wp,Wn
Wp,Wn
20Wp,20Wn
218
uWp,uWn
Cload
CADENCE CONFIDENTIAL
Inverter as buffer
Total delay = delay of first inverter + delay of buffer:
First inverter has u-times larger load:
delay = utp0
Second inverter has x/u-times larger load:
delay = (x/u)tp0
Total delay:
Wp,Wn
x
x
t p ut p 0 t p 0 u t p 0
u
u
219
Cg
uWp,uWn
Cload
CADENCE CONFIDENTIAL
Inverter as buffer
Find factor u which minimizes tp: take derivative of tp wrt u and
set to 0
x
t p ut p 0 t p 0
u
t p
x
t p0 2 t p0 0
u
u
x
1,
uopt x
2
u
t p ,opt 2t p 0 x
220
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Inverter as buffer
unbuffered: t p xt p 0
buffered:
t p 2t p 0 x
2t p 0 x xt p 0
x2 x
x4
221
single-inverter buffer is
faster if load is > 4X larger
CADENCE CONFIDENTIAL
Superbuffer design
Large fixed load capacitance driven by chain of n
inverters
Stage ratio = u
First inverter is minimum size
Each inverter is u times bigger than previous one
1
Cg
222
u2
u3
Cload
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Superbuffer design
tp0 = average delay of one inverter driving another one of same size
Delay of each stage = delay of inverter driving another inverter u
times bigger = utp0
Total delay = n u tp0
Ratio of load cap to gate cap:
Cload u nC g
Cload
x
,
Cg
x un
ln( x) n ln(u ),
223
ln( x)
n
ln(u )
number of buffers
required
CADENCE CONFIDENTIAL
Superbuffer design
Total delay:
u
Total delay ln( x)
t p0
ln(u )
Optimum stage delay u =
e ~ 2.7
Including interconnect, u
ranges from 3-5
224
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Buffer example
20
A minimum-sized inverter (size 1)
needs to drive a fan-out of 4 size 20
inverters
20
1
20
Cg
Find the delay for the (a) nonbuffered, (b) single buffer, and (c)
super-buffer case
20
tp0 = 0.5 ns
225
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226
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Dynamic Logic
VDD
VDD
Mp
Me
Out
CL
In1
In2
In3
PDN
In1
In2
In3
PUN
Out
Me
n network
2 phase operation:
227
Mp
CL
p network
Precharge
Evaluation
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Example
VDD
Mp
N + 1 Transistors
Out
Ratioless
No Static Power Consumption
Requires Clock
228
Me
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Transient Response
6.0
Vout (Volt)
4.0
Vout
EVALUATION
PRECHARGE
2.0
0.0
0.00e+00
229
2.00e-09
t (nsec)
4.00e-09
6.00e-09
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VDD
Out
In1
In2
In3
In4
230
GND
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Charge Sharing
Output is floating after clk = 1 if inputs are 0
231
C2
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232
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Noise Solutions
Charge sharing:
Ensure the output capacitance is large enough such that the
voltage drop is minimal
Precharge internal stack nodes to VCC
Pre-discharging internal stack nodes can increase performance,
but worsens noise
233
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VDD
Mp
Out
(1)
CL
A
Vout
(2)
precharge
evaluate
Me
t
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VDD
Mp
Out
CL
Ma
B=0
235
Mb
Me
X
Ca
Cb
C V
= C V
t + C V
V V
L DD
L out
a DD
Tn X
or
Ca
V out = Vout t V DD = -------- V DD V Tn V X
C
L
a
Vout = V DD ----------------------
C +C
a
L
CADENCE CONFIDENTIAL
VDD
VDD
Mp
Mbl
Mp
Mbl
Out
Out
A
Ma
Ma
Mb
Mb
Me
Me
Clock Feedthrough
VDD
Mp
Out
CL
A
237
Ma
Mb
Me
5V
X
Ca
Cb
overshoot
out
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VDD
Mp
Mp
Out2
Out1
In
Out1
VTn
In
Out2
Me
(a)
Me
t
(b)
238
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Domino Logic
Solves problem of cascading dynamic gates, but is non-inverting
Add an inverter between dynamic gates
Inverter drives the gates fanout increased performance
239
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Domino Logic
240
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Charge-Based Storage
In
Pseudo-static Latch
241
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Master-Slave Flip-Flop
In
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In
t12
243
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In
Input Sampled
Output Enable
244
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VDD
VD D
M2
M6
M4
In
M3
CL1
M8
D
M1
M7
CL2
M5
section
section
C2MOS LATCH
245
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VDD
M2
VD D
VDD
VDD
M6
M2
M6
In
1
M3
M1
D
1
In
M8
D
M7
M5
246
M4
M1
M5
CADENCE CONFIDENTIAL
VDD
In
VDD
VDD
F
C1
Out
C2
C3
NORA CMOS
What are the constraints on F and G?
247
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Example
VDD
VDD
VDD
248
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VD D
In1
In2
In3
VDD
VDD
PUN
PDN
(a) -module
Combinational logic
VDD
VDD
Latch
VDD
VD D
In 4
In 1
In 2
In 3
PDN
249
Out
Out
In4
(b) -module
CADENCE CONFIDENTIAL
VDD
VDD
VDD
VDD
Out
In
In
250
Out
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VD D
VDD
VDD
VDD
PUN
In
Static
Logic
Out
PDN
251
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Master-Slave Flip-flops
VDD
VDD
VDD
VD D
VDD
VDD
VDD
VDD
VDD
252
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Cascading Domino
For gates with all inputs coming from other domino gates, the
bottom NMOS transistor can be eliminated
Why? All inputs will be 0 during precharge and can only
transition from 0 to 1 during evaluate
Results in increased performance due to decreased stack height
253
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Pavg
1
2
2
CloadVDD
CloadVDD
f
T
254
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Velocity saturation
Mobility degradation
Threshold voltage variation
DIBL
Channel length modulation
Scaling
Constant field, constant voltage, Effects of scaling
255
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Secondary effects
Short-channel effects:
Short channel device has channel length comparable to depth of
drain and source junctions and depletion width
Causes threshold voltage and I/V curve variations
Narrow-channel effects:
Narrow channel device has small channel width
256
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Short-channel effects
Short-channel device: channel length is comparable to depth of
drain and source junctions and depletion width
In general, visible when L ~ 1um and below
Short-channel effects:
Carrier velocity saturation
Mobility degradation
Threshold voltage variation
257
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0
N+
source
Vds
N+
drain
P
258
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259
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Mobility degradation
MOS I/V equations depend on surface mobility n (or p)
1 VGS VT
260
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261
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VT rolloff
As channel length L decreases, threshold voltage decreases
Hot-carrier effect
Threshold voltages drift over time
262
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Source
depletion
region
N+
source
N+
drain
Drain
depletion
region
Gate-induced
depletion region
263
CADENCE CONFIDENTIAL
x j
2 xdS
2
x
1
dD
1
VT 0
2q Si N A 2 F
1 1
1
Cox
2 L
xj
xj
264
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VT0
Long-channel VT
Lnom
VT Roll-off:
VT decreases rapidly with channel length
265
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DIBL
Drain-induced barrier lowering (DIBL)
Drain voltage VDS causes change in threshold voltage
As VDS is increased, threshold voltage decreases
266
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267
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268
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269
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Short-channel summary
Long-channel
Short-channel
Both devices have same effective W/L ratio I/V curves should be
similar
Short-channel device has ~ 40% less current at high VDS
Note linear dependence on VGS in short-channel device
270
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Sub-threshold conduction
When VGS < VT, transistor is off
However, small drain current ID still flows
Called subthreshold leakage current
I D ( subthreshold ) I SWe
q
AVGS BVDS
kT
271
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Subthreshold conduction
Exponential relationship to VGS
log IDS(sub)
subthreshold slope
(mV/decade of current)
VT
VGS
Subthreshold slope:
Shift in VGS required to reduce leakage by factor of
10
Typical values: 80-120 mV/decade
272
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Gate leakage
Another source of leakage current is gate leakage (Fowler-Nordheim
Tunneling)
For very thin gate oxide, electrons can tunnel through the gate oxide,
resulting in current from gate to drain or source
Equation for gate leakage current:
I FN C1WLEox2 e
E0
Eox
E0, C1 constants
Eox = electric field across oxide
CADENCE CONFIDENTIAL
Leakage
Effect of leakage current
Wasted power: power consumed even when circuit is inactive
Leakage power raises temperature of chip
Can cause functionality problem in some circuits: memory,
dynamic logic, etc.
274
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Leakage
Leakage vs. performance tradeoff:
For high-speed, need small VT and L
For low leakage, need high VT and large L
Process scaling
VT reduces with each new process (historically)
Leakage increases ~10X!
275
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L L L
'
W
2
I D nCox VGS VTN 1 lVDS
L
1
2
CADENCE CONFIDENTIAL
SPICE Level 2
Variation of mobility with electric field
Variation of channel length in saturation (more accurate)
Carrier velocity saturation
Subthreshold conduction
SPICE Level 3
Mostly empirical
Accurate to 2m
277
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Scaling
Improvement in CMOS process technology. Reduction in device
dimensions, improved circuit performance
Lateral scaling
Only the gate length is scaled (gate shrink)
278
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MOSFET Scaling
Constant Voltage
Traditional, board-level compatible
Constant Field
Ideal, helps reliability
Hybrid
practical
279
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Scaling
Scaling has a threefold objective:
Reduce the gate delay by 30% (43% increase in frequency)
Double the transistor density
Saving 50% of power (at 43% increase in frequency)
280
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Constant Field
Before Scaling
Length
L/s
Width
W/s
Oxide Thickness
tox
tox/s
Diffusion/Junction Depth
Xj
Xj/s
Supply Voltage
VDD
VDD/s
Threshold Voltage
VT
VT/s
Doping Densities
NA,ND
sNA,sND
E dx
281
After Scaling
V Edx
CADENCE CONFIDENTIAL
Constant Voltage
Before Scaling
Length
L/s
Width
W/s
Oxide Thickness
tox
tox/s
Diffusion/Junction Depth
Xj
Xj/s
Supply Voltage
VDD
VDD
Threshold Voltage
VT
VT
Doping Densities
NA,ND
s2NA,s2ND
E dx
282
After Scaling
V Edx
CADENCE CONFIDENTIAL
C g ,scaled
Cg
s
Constant Voltage
Cox,scaled sCox
283
C g ,scaled
Cg
s
CADENCE CONFIDENTIAL
ox W s VGS
2 t ox s L s
VT
2
ID
s
s
Constant Voltage
I D , scaled
ox W s
2 t ox s L s
VGS VT 2 sI D
284
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P
W s L s
Pscaled
Pscaled
Ascaled
Constant Voltage
Pscaled VDS sI D sP
Pscaled
sP
s3 P
Ascaled W s L s
285
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C s V s
I s
Constant Voltage
scaled
286
(C / s )V
2
sI
s
CADENCE CONFIDENTIAL
Technology scaling
W L (1/s)2 = 0.49
Transistor density:
(unit area) /(W L) s2 = 2.04
In practice, memory density has been scaling as expected. (not true for
microprocessors)
287
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Technology scaling
Gate capacitance:
W L / tox 1/s = 0.7
Drain current:
Gate delay:
(C V) / I 1/s = 0.7
Frequency s = 1.43
288
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Technology scaling
Power:
Power density:
C V2 f (1/s)2 = 0.49
1/tox V2 f 1
Active capacitance/unit-area:
Power dissipation is a function of the operation
frequency, the power supply voltage and of the circuit
size (number of devices).
289
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Technology scaling
Interconnects scaling:
Higher densities are only possible if the interconnects also scale.
Reduced width increased resistance
Denser interconnects higher capacitance
290
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Technology scaling
To account for increased parasitics and integration
complexity
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Photolithography
CMOS Fabrication Sequence
Latch up
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Lithography
Lithography: process used to transfer patterns to each layer of the IC
Silicon Foundry:
Masks generation from the layer patterns in the design data base
Printing: transfer the mask pattern to the wafer surface
Process the wafer to physically pattern each layer of the IC
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Lithography
Basic sequence
1. Photoresist coating
Photoresist
SiO2
2. Exposure
Opaque
Mask
Exposed
Unexposed
Substrate
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Substrate
3. Development
Substrate
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Lithography
4. Etching
Substrate
Ion Implantation:
5. Ion implant
Substrate
6. After doping
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Substrate
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Lithography
The lithographic sequence is repeated for each physical layer
used to construct the IC. The sequence is always the same:
Photoresist application
Printing (exposure)
Development
Etching
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Lithography
Patterning a layer above the silicon surface
1. Polysilicon deposition
4. Photoresist developmen t
Polysilicon
SiO2
Substrate
2. Photoresist coating
Substrate
5. Polysilicon etching
photoresist
Substrate
3. Exposure
Substrate
UV light
6. Final polysilicon pattern
Substrate
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Substrate
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Lithography
Etching:
layer 1
layer 2
isotropic etch
undercut
Etching techniques:
Wet etching: uses chemicals to
remove the unprotected materials
Dry or plasma etching: uses ionized
gases rendered chemically active by
an rf-generated plasma
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resist
resist
layer 1
layer 2
preferential etch
undercut
resist
layer 1
layer 2
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Diameter = 75 to 230mm
P+ -type wafer
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< 1mm
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Lateral
diffusion
n-well
p-type epitaxial layer
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Silicon Nitride
Active mask
n-well
p-type
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n+
n+
n+
n+
p-substrate (bulk)
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Implant (Boron)
resit
n-well
p-type
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p+ channel-stop implant
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n-well
active area after LOCOS
p-type
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Field oxide
XFOX
0.54 XFOX
Silicon surface
0.46 XFOX
Silicon wafer
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Gate oxide
tox
n-well
p-type
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n-well
p-type
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p+ implant (boron)
p+ mask
n-well
Photoresist
p-type
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n-well
Photoresist
p-type
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n-well
n+
p+
p-type
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n-well
n+
p+
p-type
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metal 1 mask
metal 1
n-well
n+
p+
p-type
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Via
metal 2
metal 1
n-well
n+
p+
p-type
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Yield
Y
80
60
the layout
40
Yield tendency
100
Yield (%)
20
1.0 defects/cm2
Y e
AD
2.5 defects/cm2
5.0 defects/cm2
10
0
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Other processes
P-well process
NMOS devices are build on a implanted p-well
p-well
n+
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p+
n-type
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Other processes
Twin-well process
n+ or p+ substrate plus a lightly doped epi-layer (latchup
prevention)
wells for the n- and p-transistors
Advantages, simultaneous optimization of p- and n-transistors:
threshold voltages
body effect
gain
p-well
n-well
n+
epitaxial layer
p+
n+ substrate
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Other processes
Silicon On Insulator (SOI)
Islands of silicon on an insulator form the transistors
Advantages:
No wells denser transistor structures
Lower substrate capacitances
phosphorus glass or SiO2
S
n+
p-
n+
SiO2
S
p+
n-
polysilicon
D
p+
thinoxide
sapphire (insulator)
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Other processes
Very low leakage currents
No FOX FET exists between unrelated devices
No latchup
No body-effect:
Radiation tolerance
Disadvantages:
Absence of substrate diodes (hard to implement protection
circuits)
Higher number of substrate defects lower gain devices
More expensive processing
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Silicide
p+ poly
Oxide spacer
n+
p-doping
n+
p+
n-doping
p+
n-well
Shallow-trench isolation
p-type substrate
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Source-drain
extension
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Process enhancements
Up to six metal levels in modern processes
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Latchup
CMOS process contains parasitic bipolar transistors
Under certain conditions, these parasitic transistors can turn on,
shorting power and ground rails and usually destroying the chip
latchup
Avoiding latchup requires certain layout design rules, and careful
control of process
Latchup was a major problem in early CMOS processes
Now, latchup is mainly issue for I/O circuits, with high current
demands and possibly noisy voltages
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Latchup
substrate tap
NMOS
PMOS
n-well tap
Positive feedback between transistors: when one turns on, Vdd and Gnd are
connected
Solution: reduce Rnwell and Rpsubs: use many substrate taps in layout
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Eular graph
Stick diagrams
Design rules
Layout example
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Manufacturing problems
Photoresist shrinkage, tearing.
Impurities.
Variations between lots.
Variations across a wafer.
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Transistor problems
Variations in threshold voltage:
oxide thickness;
ion implantation;
poly variations.
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Wiring problems
Diffusion: changes in doping
- variations
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Oxide problems
Variations in height.
metal 2
metal 2
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metal 1
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Via problems
Via may not be cut all the way through.
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Constraints on Layout
Resolution constraints
What is the smallest width feature than can be printed
What is the smallest spacing that will guarantee no shorts
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Constraints on Layout
Alignment/overlap constraints
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Design Rules
Interface between designer and process engineer
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Minimum width
smallest dimension
permitted for any object in
the layout drawing (minimum
feature size)
Minimum spacing:
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Minimum spacing
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Contact
metal 1
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n+
p
Contact size
d
metal 1
d
n+ diffusion
Registration tolerance
x2
metal 1
x1
n+ diffusion
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active
n+
p-substrate
x
nselect
Incorrect mask sizing
overlap
x
active
n+
x nselect
p-substrate
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gate overhang
no overhang
no overhang
and misalignment
Short circuit
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Layer
Color
Well (p,n)
Yellow
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Representation
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Wires
341
metal 2
metal 1
pdiff/ndiff
poly
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Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
Metal1
2
2
Metal2
3
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Transistor Layout
2
3
2
3
1
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2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
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Select Layer
2
3
Select
2
1
3
Substrate
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Well
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In
GND
VD D
Out
(a) Layout
A
n
p-substrate
+
Field
Oxide
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Stick diagrams
A stick diagram is a cartoon of a layout.
Does show all components/vias (except possibly tub ties),
relative placement.
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Stick Diagrams
But
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Stick layers
metal 2
metal 1
poly
ndiff
pdiff
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VDD
in
out
VSS
phi
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phi
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SCMOS design rules are simplified, there are still a number of rules to
remember.
Use a subset of the rules to estimate what the layout will look like,
Warning:
Layout is often (sometimes) fun to do- can be an infinite time sink
Can find a way to shrink the cell a few more microns.
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Layout Issues
In CMOS there are two types of diffusion
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Keep NMOS devices near NMOS devices and PMOS devices near PMOS
devices.
So NMOS usually are placed near Gnd, and PMOS near Vdd You need
to route power and ground. (in metal)
No one will auto connect it for you.
Run poly vertically and diffusion horizontally, with metal1 horizontal (or the
reverse, just keep them orthogonal)
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Odd Out
A
A_b
CMOS Inverter/Buffer
Vdd
Gnd
A
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A_b
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If you not happy with the answer, goto step 1 and try again.
Else you are done, and you can try to layout the cell.
Will get better at seeing the critical path as you do more layout.
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Approach:
Use Euler path method to find ordering of transistors in layout
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F
C
Vdd
D
B
D
B
gnd
NMOS network
Euler path: BACED
PMOS network
Euler path: BACED
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D
VDD
D
A
F
F
C
D
Gnd
E
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1.
2.
3.
Example: x = (ab+cd)
x
x
c
VDD
x
a
VD D
x
a
d
GND
d
GND
x
GND
a
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Standard cell
Design broken into gates, either by logic designer or automated
synthesis tool
Library of standard cells created
Correct cells chosen from library, connected by layout designer or
place and route tool
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Standard cells
Example standard cell gates:
inverters, buffers, XOR gates
Detailed specifications
Delays for each input combination
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