r

Credits Terms of

A Project Report On

TIMING SIGNAL GENERATION OF CONTROL

CARD
Submitted in the partial fulfillment of the requirements of the Degree of Bachelor
of Technology
By
SHUBHAM PANDEY (43187)
ECE
June-July 2015

JCOLLEGE OF TECHNOLOGY
G.B.PANT UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
PANTNAGAR
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ARYABHATTA RESEARCH INSTITUTE OF OBSERVATIONAL

SCIENCES

MANORA PEAK, NANITAL

CERTIFICATE
This is to certify that the project entitled TIMING SIGNAL GENERATION OF CONTROL
CARD submitted by SHUBHAM PANDEY (43187) , COLLEGE OF TECHNOLOGY,
G.B.PANT UNIVERSITY OF AGRICULTURE AND TECHNOLOGY, PANTNAGAR in
partial fulfillment of the requirement of the Degree of Bachelor Of Technology embodies the
work done by him under my guidance , for the purpose of summer industrial training.

Name:

Mr. Samaresh Bhattacharjee

Designation: Engineer D (Electronics)

ARIES, Manora Peak, Nanital
Date:
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15/07/2015

ACKNOWLEDGEMENT

I express my deepest sense of gratitude towards my guide Mr. Samaresh Bhattacharjee,

for his patience, inspiration, guidance, constant encouragement, moral support, keen interest, and
valuable suggestions during preparation of this project report.
My heartfelt gratitude goes to the computer center, library and academic staff, ARIES for
their kind co-operation to our project work.
I owe a debt of gratitude to my father and mother for their consistent support, sacrifice,
candid views and meaningful suggestion given to me at different stages of this work.
Last but not the least I am thankful to the Almighty who gave me the strength and health
for completing our report.

SHUBHAM PANDEY (ECE)

43187
FINAL YEAR
COLLEGE OF TECHNOLOGY

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INDEX
List of Tables
List of Figures
Content

Page no.

Chapter 1 : About ARIES

8-16

1.1 Historical Background

1.2 Facilities at ARIES
1.2.1 130 cm Telescope
1.2.2 104 cm Telescope
1.2.3 LIDAR
1.2.4 Aethalometer
1.2.5 Automatic Weather Station (AWS)
1.2.6 ST RADAR at ARIES
Chapter 2 : PIC MICROCONTROLLER
2.1 Introduction
2.2 History of PIC Microcontroller
2.3 Core Architecture
a) Data Space(RAM)
b) Code Space
c) Word Size
d) Stacks
e) Instruction Set
2.4 Performance
2.5 Advantage
2.6 Limitations
2.7 Hardware Features
2.8 Variants
2.9 Device families
a) PIC10 and PIC12
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17-30

b)
c)
d)
e)
f)

PIC16
PIC17
PIC18
PIC24 & dsPIC
PIC32MX

Chapter 3 : Development Software

31-34

3.1 Device Programmers

a) Boot Loading
b) Third party
3.2 Debugging
a) In-circuit Debugging
b) In-circuit Emulators
3.3 Development Tools
3.4 Introduction to mikroC PRO for PIC
a) Features
Chapter 4 : Pulse Width Modulation(PWM)

35-44

4.1
4.2
4.3
4.4
4.5

Introduction
Analog Circuits
Digital Control
CCP Modules
CCP1 Modules
a) CCP1 in PWM Mode
b) PWM Period
c) PWM Resolution
4.6 Code for Generating the Timing Signals
CONCLUSION

45

REFERENCES

46

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LIST OF TABLES

TABLE 1

Modes of operation of ST RADAR

LIST OF FIGURES

Figure No.

Caption

1.1

SAMPURNANAND SANSKRIT UNIVERSITY

1.2

DEVI LODGE NANITAL

1.3

MANORA PEAK

1.4

130 cm Telescope

1.5

104 cm Telescope

1.6

LIDAR Block Diagram

1.7

Rayleigh & Mie scattering

1.8

Automatic weather station

2.1

PIC microcontrollers in DIP and QFN packages

2.2

Various older (EPROM) PIC Microcontrollers

2.3

Pin Diagram of PIC16F877A

4.1

PWM signals of varing duty cycles

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4.2

CCP1 Module

4.3

CCP1 in PWM Mode

4.4

CCP1 in PWM mode with filtration

4.5

PWM Mode

4.6

PWM Module

4.7

Single PWM wave having PWM period as 1S

4.8

Two PWM waves having PWM period as 1S and 16S respectively

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Chapter 1

ABOUT ARIES

ARIES (an acronym of Aryabhatta Research Institute of observational sciencES) is situated

adjacent to the picturesque hill town of Nainital, ARIES is one of the leading research Institutes
which specializes in observational Astronomy & Astrophysics and Atmospheric Sciences. The
main research interests of Astronomy & Astrophysics division are in solar, planetary, stellar,
galactic and extra-galactic astronomy including stellar variabilitys, X-ray binaries, star clusters,
nearby galaxies, quasars, and inherently transient events like supernovae and highly energetic
gamma ray bursts. Research focus in Atmospheric Sciences division is mainly in the lower part
of the atmosphere and covers the studies on aerosols and trace gases. Moreover, to strengthen the
scientific contribution
The Institute has extended its horizon to theoretical and numerical studies in Relativistic
Astrophysics. The unique position of ARIES (79 East), places it at almost in the middle of 180
wide longitude band, between Canary Island (20 West) and Eastern Australia (157 East), and
therefore complements observations which might not be possible from either of these two places.
ARIES has made unique contribution from time to time. To quote examples from the past the
first successful Indian optical observations of the afterglow of gamma-ray burst was carried out
from ARIES on January 23, 1999, a few micro- lensing events and quasar variability, new ring
systems around Saturn, Uranus, and Neptune were also discovered.

The Institute hosts five telescopes of different apertures ranging from 15cm to 104cm.
There are two 15-cm telescopes dedicated for solar observations. The 104-cm optical telescope is
being used as a main observing facility by the ARIES scientists since 1972. It is equipped with 2k
x 2k, and 1k x 1k liquid N cooled CCD cameras, fast photometer, spectrophotometer, and
standard astronomical 2 filters. The telescope uses a SBIG ST-4 camera for auto-guiding through
an auxiliary 20-cm telescope.

In order to carry out observations in the frontier areas of astronomy, the Institute has
telescopes at a site called 'Devasthal' at a distance of ~ 60-Km from ARIES, which has the
advantages of having dark skies and excellent observing conditions.
The Scientists from the Solar group of ARIES are also participating in the national
projects like space coronagraph and National Large Solar Telescope (NLST). There are different
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instruments for observation of physical and optical properties of aerosols and trace gas. An 84cm micro-pulse LIDAR system for high altitude studies of aerosols and a ST Radar (Stratosphere
Troposphere Radar) to measure winds speed up to an altitude of around 20 km is also being
setup.
For different research activities in the field of atmospheric sciences, different instrument
have been at ARIES, which provide many interesting data. In order to fulfill the objective of
ARIES, it has also started initiative to set up a modern technique in the field of atmospheric
sciences.

1.1 Historical background

By the initiative of the Govt. of India, immediately after the independence, there was a
flurry in scientific activities signaled by the establishme nt of a chain of national laboratories in
the period 1947-1955. It was happy a coincidence that in the state of Uttar Pradesh a scholarly
statesman was interested in nurturing the science of Astronomy - the mother of a number of other
branches in fundamental sciences. Mainly, It was due to the initiative of the late Dr.
Sampurnanand, cabinet Minister of Education, Uttar Pradesh and later the Chief Minister of the
state, the Uttar Pradesh State Observatory (UPSO) came into existence.
In November 1955, the UPSO was shifted over from Varanasi to a small cottage at Debi
Lodge, half way up to Snow View from the Lake Bridge at Nainital. UPSO moved to Manora
Peak (longitude 790 27' E, latitude 290 22' N, altitude 1951 meters), south west of Nainital and
situated at a distance of 9 km from the Nainital town. The boundaries of UPSO are defined by the
road to Nainital which was a gravel one at that time. On 7 th January 2004, after the institute has
come under the department of science and technology, Govt. of India it has been initiated as
ARIES (Aryabhatta Research Institute of observational sciences ). The primary objective of
ARIES is to develop research facilities in the field of modern astrophysical research and
atmospheric sciences.

Figure 1.1: S AMPURN ANAND S ANS KRIT UN IVERS ITY

The observatory moved from Varanasi to the Hills of Nanital (1955)

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Figure 2.2: DEVI LODGE N ANITAL

Aryabhatta Research Institute of observational sciencES (ARIES) was the new name
when SO came under the Department of Science & Technology (DST), Govt. of India as an
autonomous body. The ARIES came into existence on 22nd March 2004, following the decision
of the cabinet of Ministers of the Govt. of India on 07th January, 2004.

Figure 3.3: MANORA PEAK

The observatory moved to Manora Peak in 1961

The main objective of ARIES is to provide national optical observing facilities to carry
out research in front- line areas of astronomy, astrophysics and atmospheric sciences. The main
research interests are in solar astronomy, stellar astronomy, star clusters, stellar variabilitys and
pulsation, photometric studies of nearby galaxies, Quasars, transient event like supernovae and
highly energetic gamma-ray Burst, study of Aerosols, airglow emission, mesosphere lower
thermosphere regions , and various coupling processes between different atmospheric regions of
the earth.
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1.2 Facilities at ARIES

1.2.1 130 cm Telescope:
130-cm diameter optical telescope has been installed in December 2010 at Devasthal,
Nainital in the central Himalayan region. The main objective for setting up of a 130 cm optical
telescope at Devasthal was to meet the observational requirements for the institute's scientific
programs, which were so far being carried out using nearly 40 year old 104-cm Sampurnanand
telescope. The institute's main scientific programs such as monitoring of transients (Gamma Ray
Bursts; GRB, Supernovae explosions), variability of stars in the Milky-way and of active nucleus
in external galaxies require an automated telescope for efficient observations. Other programs
such as imaging of star clusters require wide field imaging capabilities. The installed 130-cm
telescope at Devasthal is able to fulfill most of the requirement.

Figure 4.4: 130 cm Telescope

The telescope has been fabricated by DFM Engineering Inc. USA. The telescope uses a
modified Ritchey-Chretien Cassegrain design and the focal length to diameter ratio (focal-ratio)
of the overall optics was kept at 4 making it a very fast system providing 40 arcsec view of the
sky in 1 mm scale at the focal plane. A single element corrector provides a nearly flat field view
of the sky up to 66 arcmin in diameter.
The tube of the 130-cm telescope is of open truss allowing the telescope to cool faster in
the ambient. The telescope mount is of fork-equatorial type. The telescope can be pointed to a
celestial object with an accuracy of 10 arcsec rms. The mechanical system provides a tracking
accuracy at nearly 0.5 arcsec rms over 10- min without any external guider. The images obtained
with the telescope show best FWHM at nearly 1 arcsec. The atmospheric extinction at Devasthal
is measured as 0.24 mag in B (Blue), 0.14 mag in V (Visual), and 0.08 mag in R (Red) band on
the first week of December, 2010. The sky brightness is measured as 21.2 mag/arcsec2 in the V
band in moonless night.

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1.2.2 104 cm Telescope:

The 104-cm Sampurnanand Optical Telescope, located at Manora Peak, Nainital, is the
main optical observing facility of Aryabhatta Research Institute of Observational Sciences. This
facility is popularly known as 40- inch telescope amongst ARIES staff. It was installed in 1972 by
Carl Zeiss, Germany. The telescope is an RC reflector with a Cassegrain and a Coude focus with
equatorial 2-pier english mounting.
Three finder telescopes are also provided with clear aperture of around 10-inch (264 mm,
f/14, reflector), 8- inch (200 mm, f/15, refractor) and 4- inch (110 mm, f/7, refractor type). The 8
and 4- inch finder telescopes are equipped with eyepieces which covers around 20 and
90 arcmin field of view respectively. The 8-inch refractor is also used for guiding the main (104cm) telescope.

Figure 5.5: 104 cm Telescope

A field of around 45 arcmin with corrector is available at the cassegrain end of the
telescope. The tracking accuracy is around 7 arcsec/hr (0.1 arcsec/min) without guider and is
around 0.7 arcsec/hr with guider. The off-axis guiding of the telescope is done through 8- inch
finder telescope using ST4.Fundamental Parameters for the 104-cm Sampurnanand Telescope
Parameter Value Unit Primary Diameter 104 cm Primary focal length 416 (f/4) cm Effective
focal length 1330 (f/13) cm Separation 292 cm .
1.2.3 LIDAR:
LIDAR, stands for Light Detection And Ranging. The LIDAR has designed and
developed at National Atmospheric Research laboratory (NARL), Gadanki, Tirupati. Since,
Manora Peak is located geographically in free tropospheric zone, the site is conducive for
evaluating the aerosol loading effects on the atmosphere due to the aerosol transportation from
nearby polluted valley regions and also the long range aerosol transportation from far off regions
to this height, apparently discernible during the major dust storms. In this perspective the LIDAR
observations of tropospheric aerosols are being carried out for the first time, in the central
Himalayan region at an altitude of ~2.0 km above mean sea level with a range resolution of 0.03
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km. During the observations the LIDAR system collects the backscattered laser returns from the
atmospheric aerosol and high altitude clouds.

Figure 6.6: LIDAR Block Diagram

Rayleigh & Mie LIDAR:

When scatters are very small compared to the wavelength of incident radiation(r<
wavelength/10), the scattered intensity on both forward and backward directions are equal. This
type of scattering is called Rayleigh scatte ring.

Figure 7.7: Rayleigh & Mie scattering

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For larger particles(r> wavelength), the angular distribution of scattered intensity

becomes more complex with more energy scattered in the forward direction. This type of
scattering is called Mie scattering.

Mie scattering LIDAR Winds, Aerosols & clouds

Rayleigh scattering LIDAR Atmospheric temperature, Winds

1.2.4 Aethalometer:
An Aethalometer is an instrument for measuring the concentration of optically absorbing
(black) suspended particulates in a gas colloid stream; commonly visualized as smoke or haze,
often seen in ambient air under polluted conditions. The word aethalometer is derived from the
Classical Greek verb aethaloun, meaning to blacken with soot.
The main uses of aethalometers relate to air quality measurements, with the data being
used for studies of the impact of air pollution on health; climate; and visibility. Other uses
include measurements of the emission of black carbon from combustion sources such as vehicles;
industrial processes; and biomass burning, both in wild fires and in domestic and industrial
settings. The Aethalometer currently in use at ARIES is spectrum AE4 series of Aethalometer,
which performs simultaneous measurements of BC at 7 Wavelengths from 370nm (UV) to
950nm (Near IR).

1.2.5 Automatic Weathe r Station (AWS):

An automatic weather station (AWS) is an automated version of the traditional weather

station, either to save human labour or to enable measurements from remote areas. An AWS will
typically consist of a weather-proof enclosure containing the data logger, rechargeable
battery, telemetry (optional) and the meteorological sensors with an attached solar panel or wind
turbine and mounted upon a mast. The specific configuration may vary due to the purpose of the
system. The system may report in near real time via the Argos System and the Global
Telecommunications System, or save the data for later recovery. In the past, automatic weather
stations were often placed where electricity and communication lines were available. Nowadays,
the solar panel, wind turbine and mobile phone technology have made it possible to have wireless
stations that are not connected to the electrical grid or hard- line telecommunications network.

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Figure 8.8: Automatic weather station

Data collections are being carried out on regular basis by using both manual and
automatic weather stations. Automatic weather station (Campbell scientific, USA) installed at
ARIES is used for standard meteorological measurements like wind speed, wind directions, solar
radiation, soil/air temperature, relative humidity, barometric pressure and precipitation at ground
level. The system is fully programmed for hourly and daily measurements of above parameters.

1.2.6 ST Radar at ARIES:

Upcoming stratosphere troposphere (ST) RADAR at ARIES Nainital will operate at 206.5
MHz center frequency covering a bandwidth of 5MHz.
Salient features includes :

Active Phased Array, Circular Aperture, Triangular grid of 588 individual 3-elements Yagi's
Provides both DBS & SAD mode of operation

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MODE

Height Coverage

Resolution

DBS-1/SAD mode

0.5-5 km

75m to 150m

DBS-2 mode

5km - 20km

300m

TABLE 9: Modes of operation of S T RADAR

Coherent 588 solid state T/R modules with peak power of - 400 Watt
Direct RF signal Digitization with baseband sampling
Advanced 4-channel digital Rx - having 16 bit ADC and Vertex-5 FPGA
Control Area Network(CAN) based beam steering and control
NAS Box storage in NetCDF format.

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Chapter 2

PIC MICROCONTROLLER

2.1 Introduction:
PIC is a family of modified Harvard architecture microcontrollers made by Microchip
Technology, derived from the PIC1650 originally developed by General Instrument's
Microelectronics Division. The name PIC initially referred to Peripheral Interface
Controller. The first parts of the family were available in 1976; by 2013 the company
had shipped more than twelve billion individual parts, used in a wide variety
of embedded systems.
Early models of PIC had read-only memory (ROM) or field-programmable EPROM
for program storage, some with provision for erasing memory. All current models
use Flash memory for program storage, and newer models allow the PIC to reprogram
itself. Program memory and data memory are separated. Data memory is 8-bit, 16-bit
and in latest models, 32-bit wide. Program instructions vary in bit-count by family of
PIC, and may be 12, 14, 16, or 24 bits long. The instruction set also varies by model,
with more powerful chips adding instructions for digital signal processing functions.
The hardware capabilities of PIC devices range from 8-pin DIP chips up to 100pin SMD chips, with discrete I/O pins, ADC and DAC modules, and communications
ports such as UART, I2C, CAN, and even USB. Low-power and high-speed variations
exist for many types.

Fig2.1 PIC microcontrollers in DIP and QFN packages

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The manufacturer supplies computer software for development known as MPLAB,

assemblers and C/C++ compilers, and programmer/debugger hardware under
the MPLAB and PICKit series. Third party and some open-source tools are also
available. Some parts have in-circuit programming capability; low-cost development
programmers are available as well has high-production programmers.
PIC devices are popular with both industrial developers and hobbyists due to their low
cost, wide availability, large user base, extensive collection of application notes, and
availability of low cost or free development tools, serial programming, and reprogrammable Flash-memory capability.

2.2 History of PIC Microcontroller:

The original PIC was built to be used with General Instrument's new CP1600 16bit Central processing unit (CPU). While generally a good CPU, the CP1600 had
poor I/O performance, and the 8-bit PIC was developed in 1975 to improve
performance of the overall system by offloading I/O tasks from the CPU. The PIC
used simple microcode stored in ROM to perform its tasks, and although the term was
not used at the time, it shares some common features with RISC designs.
In 1985, General Instrument spun off their microelectronics division and the new
ownership cancelled almost everything which by this time was mostly out-of-date.
The PIC, however, was upgraded with an internal EPROM to produce a
programmable channel controller. Today, a huge variety of PICs are available with
various on-board peripherals (serial communication modules, UARTs, motor control
kernels, etc.) and program memory from 256 words to 64k words and more (a "word"
is one assembly language instruction, varying in length from 8 to 16 bits, depending
on the specific PIC micro family).
PIC and PICmicro are registered trademarks of Microchip Technology. It is generally
thought that PIC stands for Peripheral Interface Controller, although General
Instruments' original acronym for the initial PIC1640 and PIC1650 devices was
"Programmable Interface Controller". The acronym was quickly replaced with
"Programmable Intelligent Computer".
The Microchip 16C84 (PIC16x84), introduced in 1993, was the first Microchip CPU
with on-chip EEPROM memory. This electrically erasable memory made it cost less
than CPUs that required a quartz "erase window" for erasing EPROM.
By 2013, Microchip was shipping over one billion PIC microcontrollers every year.
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2.3 CORE ARCHITECTURE:

The PIC architecture is characterized by its multiple attributes:
Separate code and data spaces (Harvard architecture).
A small number of fixed-length instructions
Most instructions are single-cycle (2 clock cycles, or 4 clock cycles in 8-bit
models), with one delay cycle on branches and skips
One accumulator (W0), the use of which (as source operand) is implied (i.e. is
not encoded in the opcode)
All RAM locations function as registers as both source and/or destination of
math and other functions.
A hardware stack for storing return addresses
A small amount of addressable data space (32, 128, or 256 bytes, depending on
the family), extended through banking
Data-space mapped CPU, port, and peripheral registers
ALU status flags are mapped into the data space
The program counter is also mapped into the data space and writable (this is
used to implement indirect jumps).
There is no distinction between memory space and register space because the RAM
serves the job of both memory and registers, and the RAM is usually just referred to as
the register file or simply as the registers.

Fig 2.2 Various older (EPROM) PIC microcontrollers

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a) Data space (RAM)

PICs have a set of registers that function as general-purpose RAM. Special-purpose control
registers for on-chip hardware resources are also mapped into the data space. The
addressability of memory varies depending on device series, and all PIC devices have
some banking mechanism to extend addressing to additional memory. Later series of devices
feature move instructions, which can cover the whole addressable space, independent of the
selected bank. In earlier devices, any register move had to be achieved through the
accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF)
are used. A register number is written to the FSR, after which reads from or writes to INDF
will actually be to or from the register pointed to by FSR. Later devices extended this concept
with post- and pre- increment/decrement for greater efficiency in accessing sequentially
stored data. This also allows FSR to be treated almost like a stack pointer (SP).
External data memory is not directly addressable except in some PIC18 devices with high pin
count.

b) Code space
The code space is generally implemented as ROM, EPROM or flash ROM. In general,
external code memory is not directly addressable due to the lack of an external memory
interface. The exceptions are PIC17 and select high pin count PIC18 devices.

c) Word size
All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the
code space is not generally the same as the data space. For example, PICs in the baseline
(PIC12) and mid-range (PIC16) families have program memory addressable in the same
wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18
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series, the program memory is addressed in 8-bit increments (bytes), which differs from the
instruction width of 16 bits.
In order to be clear, the program memory capacity is usually stated in number of (singleword) instructions, rather than in bytes.

d) Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware stack
is not software-accessible on earlier devices, but this changed with the 18 series devices.
Hardware support for a general-purpose parameter stack was lacking in early series, but this
greatly improved in the 18 series, making the 18 series architecture more friendly to highlevel language compilers.

e) Instruction set
PIC's instructions vary from about 35 instructions for the low-end PICs to over 80
instructions for the high-end PICs. The instruction set includes instructions to perform a
variety of operations on registers directly, the accumulator and a literal constant or the
accumulator and a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register,
but bi-operand arithmetic operations always involve W (the accumulator), writing the result
back to either W or the other operand register. To load a constant, it is necessary to load it
into W before it can be moved into another register. On the older cores, all register moves
needed to pass through W, but this changed on the "high-end" cores.
PIC cores have skip instructions, which are used for conditional execution and branching.
The skip instructions are "skip if bit set" and "skip if bit not set". Because cores before PIC18
had only unconditional branch instructions, conditional jumps are implemented by a
conditional skip (with the opposite condition) followed by an unconditional branch. Skips are
also of utility for conditional execution of any immediate single following instruction. It is
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possible to skip skip instructions. For example, the instruction sequence "skip if A; skip if B;
C" will execute C if A is true or if B is false.
The 18 series implemented shadow, registers which save several important registers during
an interrupt, providing hardware support for automatically saving processor state when
servicing interrupts.
In general, PIC instructions fall into 5 classes:
Operation on working register (WREG) with 8-bit immediate ("literal") operand.
E.g. movlw (move literal to WREG), andlw (AND literal with WREG). One instruction
peculiar to the PIC is retlw, load immediate into WREG and return, which is used with
computed branches to produce lookup tables.
Operation with WREG and indexed register. The result can be written to either the Working
register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f ).
Bit operations. These take a register number and a bit number, and perform one of 4 actions:
set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional
branches. The usual ALU status flags are available in a numbered register so operations such
as "branch on carry clear" are possible.
Control transfers. Other than the skip instructions previously mentioned, there are only
two: goto and call .
A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to
enter low-power mode.

2.4) Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC
architecture was among the first scalar CPU designs and is still among the simplest and
cheapest. The Harvard architecture, in which instructions and data come from separate
sources, simplifies timing and microcircuit design greatly, and this benefits clock speed,
price, and power consumption.
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The PIC instruction set is suited to implementation of fast lookup tables in the program space.
Such lookups take one instruction and two instruction cycles. Many functions can be modeled
in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g.
4096 14-bit words on the 16F690) and by the design of the instruction set, which allows
embedded constants. For example, a branch instruction's target may be indexed by W, and
execute a "RETLW", which does as it is named return with literal in W.
Interrupt latency is constant at three instruction cycles. External interrupts have to be
synchronized with the four-clock instruction cycle, otherwise there can be a one instruction
cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows
PICs to achieve interrupt-driven low-jitter timing sequences. An example of this is a video
sync pulse generator. This is no longer true in the newest PIC models, because they have a
synchronous interrupt latency of three or four cycles.

2.5) Advantages

Small instruction set to learn

RISC architecture

Built-in oscillator with selectable speeds

Easy entry level, in-circuit programming plus in-circuit debugging PICkit units available
for less than $50

Inexpensive microcontrollers

Wide range of interfaces including IC, SPI, USB, USART, A/D, programmable
comparators, PWM, LIN, CAN, PSP, and Ethernet .

Availability of processors in DIL package make them easy to handle for hobby use.

2.6) Limitations

One accumulator

Register-bank switching is required to access the entire RAM of many devices

Operations and registers are not orthogonal; some instructions can address RAM
and/or immediate constants, while others can use the accumulator only.
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The following stack limitations have been addressed in the PIC18 series, but still apply to
earlier cores:

The hardware call stack is not addressable, so preemptive task switching cannot be
implemented

Software-implemented stacks are not efficient, so it is difficult to generate reentrant code

and support local variables

With paged program memory, there are two page sizes to worry about: one for CALL and
GOTO and another for computed GOTO (typically used for table lookups). For example, on
PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction
words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words.
In both cases, the upper address bits are provided by the PCLATH register. This register must
be changed every time control transfers between pages. PCLATH must also be preserved by
any interrupt handler.

2.7) Hardware features

PIC devices generally feature:

Flash memory (program memory, programmed using MPLAB devices)

SRAM (data memory)

EEPROM memory (programmable at run-time)

Sleep mode (power savings)

Watchdog timer

Various crystal or RC oscillator configurations, or an external clock

2.8) Variants
Within a series, there are still many device variants depending on what hardware resources
the chip features:

General purpose I/O pins

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Internal clock oscillators

8/16/32 bit timers

Synchronous/Asynchronous Serial Interface USART

MSSP Peripheral for IC and SPI communications

Capture/Compare and PWM modules

Analog-to-digital converters (up to ~1.0 MHz)

USB, Ethernet, CAN interfacing support

External memory interface

Integrated analog RF front ends (PIC16F639, and rfPIC).

KEELOQ Rolling code encryption peripheral (encode/decode)

And many more

2.9) DEVICE FAMILIES

PICmicro chips are designed with a Harvard architecture, and are offered in various device
families. The baseline and mid-range families use 8-bit wide data memory, and the high-end
families use 16-bit data memory. The latest series, PIC32MX is a 32-bit MIPS-based
microcontroller. Instruction words are in sizes of 12-bit (PIC10 and PIC12), 14-bit (PIC16)
and 24-bit (PIC24 and dsPIC). The binary representations of the machine instructions vary by
family and are shown in PIC instruction listings.

a) PIC10 and PIC12

These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level
deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and
PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.
Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the
remaining bytes are general purpose RAM. Pointers are implemented using a register pair:
after writing an address to the FSR (file select register), the INDF (indirect f) register
becomes an alias for the addressed register. If banked RAM is implemented, the bank number
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is selected by the high 3 bits of the FSR. This affects register numbers 1631; registers 015
are global and not affected by the bank select bits.
Because of the very limited register space (5 bits), 4 rarely read registers were not assigned
addresses, but written by special instructions ( OPTION and TRIS).
The ROM address space is 512 words (12 bits each), which may be extended to 2048 words
by banking. CALL and GOTO instructions specify the low 9 bits of the new code location;
additional high-order bits are taken from the status register. Note that a CALL instruction
only includes 8 bits of address, and may only specify addresses in the first half of each 512word page.
Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a
table of RETLW instructions. Baseline core devices (12 bit).

b) PIC16:
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack.
The instruction set differs very little from the baseline devices, but the 2 additional opcode
bits allow 128 registers and 2048 words of code to be directly addressed. There are a few
additional miscellaneous instructions, and two additional 8-bit literal instructions, add and
subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.
The first 32 bytes of the register space are allocated to special-purpose registers; the
remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16
registers (0x700x7F) are global, as are a few of the most important special-purpose
registers, including the STATUS register which holds the RAM bank select bits. (The other
global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high
preload register PCLATH, and the master interrupt control register INTCON.)
The PCLATH register supplies high-order instruction address bits when the 8 bits supplied
by a write to the PCL register, or the 11 bits supplied by a GOTO or CALL instruction, is
not sufficient to address the available ROM space.

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FIG2.3 PIN DIAGRAM OF PIC16F877A

c) PIC17
The 17 series never became popular and has been superseded by the PIC18 architecture. It is
not recommended for new designs, and availability may be limited.
Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions),
and a 16 level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins.
The 17 series introduced a number of important new features:

a memory mapped accumulator

read access to code memory (table reads)

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direct register to register moves (prior cores needed to move registers through the
accumulator)

an external program memory interface to expand the code space

an 8-bit 8-bit hardware multiplier

a second indirect register pair

auto-increment/decrement addressing controlled by control bits in a status register

(ALUSTA)

d) PIC18
In 2000, Microchip introduced the PIC18 architecture. Unlike the 17 series, it has proven to
be very popular, with a large number of device variants presently in manufacture. In contrast
to earlier devices, which were more often than not programmed in assembly, C has become
the predominant development language.
The 18 series inherits most of the features and instructions of the 17 series, while adding a
number of important new features:

call stack is 21 bits wide and much deeper (31 levels deep)

the call stack may be read and written (TOSU:TOSH:TOSL registers)

conditional branch instructions

indexed addressing mode (PLUSW)

extending the FSR registers to 12 bits, allowing them to linearly address the entire data
address space

the addition of another FSR register (bringing the number up to 3)

The RAM space is 12 bits, addressed using a 4-bit bank select register and an 8-bit offset in
each instruction. An additional "access" bit in each instruction selects between bank 0 (a=0)
and the bank selected by the BSR (a=1).
A 1-level stack is also available for the STATUS, WREG and BSR registers. They are saved
on every interrupt, and may be restored on return. If interrupts are disabled, they may also be
used on subroutine call/return by setting the s bit (appending ", FAST" to the instruction).
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The auto increment/decrement feature was improved by removing the control bits and adding
four new indirect registers per FSR. Depending on which indirect file register is being
accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the
effective address by adding W to FSR.
In more advanced PIC18 devices, an "extended mode" is available which makes the
addressing even more favorable to compiled code:

a new offset addressing mode; some addresses which were relative to the access bank are
now interpreted relative to the FSR2 register

the addition of several new instructions, notable for manipulating the FSR registers.

These changes were primarily aimed at improving the efficiency of a data stack
implementation. If FSR2 is used either as the stack pointer or frame pointer, stack items may
be easily indexedallowing more efficient re-entrant code. Microchip's MPLAB C18 C
compiler chooses to use FSR2 as a frame pointer.

e) PIC24 and dsPIC

In 2001, Microchip introduced the dsPIC series of chips, which entered mass production in
late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are
designed as general purpose microcontrollers. dsPIC devices include digital signal
processing capabilities in addition.
Although still similar to earlier PIC architectures, there are significant enhancements.

All registers are 16 bits wide

Data address space expanded to 64 KB

First 2 KB is reserved for peripheral control registers

Data bank switching is not required unless RAM exceeds 62 KB

"f operand" direct addressing extended to 13 bits (8 KB)

16 W registers available for register-register operations.

(But operations on f operands always reference W0.)

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Program counter is 22 bits (Bits 22:1; bit 0 is always 0)

Instructions are 24 bits wide

Instructions come in byte (B=1) and (16-bit) word (B=0) forms

Stack is in RAM (with W15 as stack pointer); there is no hardware stack

W14 is the frame pointer

Data stored in ROM may be accessed directly ("Program Space Visibility")

Interrupt vectors for different interrupt sources are supported.

Some features are:

hardware MAC (multiplyaccumulate)

barrel shifting

bit reversal

(1616)-bit single-cycle multiplication and other DSP operations

hardware divide assist (19 cycles for 16/32-bit divide)

hardware support for loop indexing

Direct memory access

dsPICs can be programmed in C using Microchip's XC16 compiler (formerly called C30)
which is a variant of GCC.
Instruction ROM is 24 bits wide. Software can access ROM in 16-bit words, where even
words hold the least significant 16 bits of each instruction, and odd words hold the most
significant 8 bits. The high half of odd words reads as zero. The program counter is 23 bits
wide, but the least significant bit is always 0, so there are 22 modifiable bits.
Instructions come in 2 main varieties. One is like the classic PIC instructions, with an
operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a
destination select bit selecting which is updated with the result. The W registers are memorymapped. so the f operand may be any W register,

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f) PIC32MX
In November 2007, Microchip introduced the new PIC32MX family of 32-bit
microcontrollers. The initial device line-up is based on the industry standard MIPS32 M4K
Core. The device can be programmed using the Microchip MPLAB C Compiler for PIC32
MCUs, a variant of the GCC compiler. The first 18 models currently in production
(PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the same peripherals
set with the PIC24FxxGA0xx family of (16-bit) devices allowing the use of common
libraries, software and hardware tools. Today starting at 28 pin in small QFN packages up to
high performance devices with Ethernet, CAN and USB OTG, full family range of mid-range
32-bit microcontrollers are available.
The PIC32 architecture brings a number of new features to Microchip portfolio, including:

The highest execution speed 80 MIPS (120+ Dhrystone MIPS @ 80 MHz)

The largest flash memory: 512 kB

One instruction per clock cycle execution

The first cached processor

Allows execution from RAM

Full Speed Host/Dual Role and OTG USB capabilities

Full JTAG and 2 wire programming and debugging

Real-time trace

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Chapter 3

Development Software

3.1) Device Programmers:

Devices called "programmers" are traditionally used to get program code into the
target PIC. Most PICs that Microchip currently sell feature ICSP (In Circuit Serial
Programming) and/or LVP (Low Voltage Programming) capabilities, allowing the
PIC to be programmed while it is sitting in the target circuit.
Microchip offers programmers/debuggers under the MPLAB and PICKit series.
MPLAB ICD and MPLAB REAL ICE are the current programmers and debuggers
for professional engineering, while PICKit is a low-cost programmer-only line for
hobbyists and students.

a) Boot loading:
Many of the higher end flash based PICs can also self-program (write to their own
program memory), a process known as bootloading. Demo boards are available
with a small bootloader factory programmed that can be used to load user programs
over an interface such as RS-232 or USB, thus obviating the need for a programmer
device.
Alternatively there is bootloader firmware available that the user can load onto the
PIC using ICSP. After programming the bootloader onto the PIC, the user can then
reprogram the device using RS232 or USB, in conjunction with specialized
computer software.
The advantages of a bootloader over ICSP is faster programming speeds,
immediate program execution following programming, and the ability to both
debug and program using the same cable.
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b) Third party:
There are many programmers for PIC microcontrollers, ranging from the extremely
simple designs which rely on ICSP to allow direct download of code from a host
computer, to intelligent programmers that can verify the device at several supply
voltages. Many of these complex programmers use a pre-programmed PIC
themselves to send the programming commands to the PIC that is to be
programmed. The intelligent type of programmer is needed to program earlier PIC
models (mostly EPROM type) which do not support in-circuit programming.
Third party programmers range from plans to build your own, to self-assembly kits
and fully tested ready-to-go units. Some are simple designs which require a PC to
do the low-level programming signalling (these typically connect to
the serial or parallel port and consist of a few simple components), while others
have the programming logic built into them (these typically use a serial or USB
connection, are usually faster, and are often built using PICs themselves for
control).

3.2) Debugging:
a) In-circuit debugging:
All newer PIC devices feature an ICD (in-circuit debugging) interface, built into
the CPU core, that allows for interactive debugging of the program in conjunction
with MPLAB IDE.MPLAB ICD and MPLAB REAL ICE debuggers can
communicate with this interface using the ICSP interface.
This debugging system comes at a price however, namely limited breakpoint count
(1 on older devices, 3 on newer devices), loss of some I/O (with the exception of
some surface mount 44-pin PICs which have dedicated lines for debugging) and
loss of some on-chip features.

b) In-circuit emulators:
Microchip offers three full in-circuit emulators: the MPLAB ICE2000 (parallel
interface, a USB converter is available); the newer MPLAB ICE4000 (USB 2.0
connection); and most recently, the REAL ICE (USB 2.0 connection). All such
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tools are typically used in conjunction with MPLAB IDE for source-level
interactive debugging of code running on the target.

3.3) Development tools:

Microchip provides a freeware IDE package called MPLAB, which includes an
assembler, linker, software simulator, and debugger. They also sell C compilers for
the PIC18, PIC24, PIC32 and dsPIC, which integrate cleanly with MPLAB. Free
student versions of the C compilers are also available with all features. But for the
free versions, optimizations will be disabled after 60 days. The cheapest compiler
for the most common PIC18 series and commercial use starts at around $500.
Several third parties develop C language compilers for PICs, many of which
integrate to MPLAB and/or feature their own IDE. A fully featured compiler for
the PICBASIC language to program PIC microcontrollers is available from meLabs
Inc. Mikroelektronika offers PIC compilers in C, Basic and Pascal
programming languages.
A graphical programming language, Flowcode, exists capable of programming 8and 16-bit PIC devices and generating PIC-compatible C code. It exists in
numerous versions from a free demonstration to a more complete professional
edition

3.4) Introduction to mikroC PRO for PIC:

The mikroC PRO for PIC is a powerful, feature-rich development tool for PIC
microcontrollers. It is designed to provide the programmer with the easiest possible
solution to developing applications for embedded systems, without compromising
performance or control.
PIC and C fit together well: PIC is the most popular 8-bit chip in the world, used in
a wide variety of applications, and C, prized for its efficiency, is the natural choice
for developing embedded systems. mikroC PRO for PIC provides a successful
match featuring highly advanced IDE, ANSI compliant compiler, broad set of
hardware libraries, comprehensive documentation, and plenty of ready-to-run
examples.

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a) Features:
mikroC PRO for PIC allows you to quickly develop and deploy complex
applications:
Write your C source code using the built-in Code Editor (Code and
Parameter Assistants, Code Folding, Syntax Highlighting, Auto Correct,
Code Templates, and more.)
Use included mikroC PRO for PIC libraries to dramatically speed up the
development: data acquisition, memory, displays, conversions,
communication etc.
Monitor your program structure, variables, and functions in the Code
Explorer.
Generate commented, human-readable assembly, and standard HEX
compatible with all programmers.
Use the integrated mikroICD (In-Circuit Debugger) Real-Time debugging
tool to monitor program execution on the hardware level.
Inspect
program flow and debug executable logic with the
integrated Software Simulator.
Generate COFF (Common Object File Format) file for software and
hardware debugging under Microchip's MPLAB software.
Active Comments enable you to make your comments alive and interactive.
Get detailed reports and graphs: RAM and ROM map, code statistics,
assembly listing, calling tree, and more.
mikroC PRO for PIC provides plenty of examples to expand, develop, and
use as building bricks in your projects. Copy them entirely if you deem fit
thats why we included them with the compiler.

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Chapter 4
Pulse Width Modulation (PWM)
4.1 Introduction:
Pulse-width modulation (PWM), or pulse-duration modulation (PDM), is a
technique used to encode a message into a pulsing signal. It is a type of modulation.
Although this modulation technique can be used to encode information for
transmission, its main use is to allow the control of the power supplied to electrical
devices, especially to inertial loads such as motors. In addition, PWM is one of the
two principal algorithms used in photovoltaic solar battery chargers, the other
being MPPT.
The average value of voltage (and current) fed to the load is controlled by turning
the switch between supply and load on and off at a fast rate. The longer the switch
is on compared to the off periods, the higher the total power supplied to the load.
The PWM switching frequency has to be much higher than what would affect the
load (the device that uses the power), which is to say that the resultant waveform
perceived by the load must be as smooth as possible. Typically switching has to be
done several times a minute in an electric stove, 120 Hz in a lamp dimmer, from
few kilohertz (kHz) to tens of kHz for a motor drive and well into the tens or
hundreds of kHz in audio amplifiers and computer power supplies.
The term duty cycle describes the proportion of 'on' time to the regular interval or
'period' of time; a low duty cycle corresponds to low power, because the power is
off for most of the time. Duty cycle is expressed in percent, 100% being fully on.
The main advantage of PWM is that power loss in the switching devices is very
low. When a switch is off there is practically no current, and when it is on and
power is being transferred to the load, there is almost no voltage drop across the
switch. Power loss, being the product of voltage and current, is thus in both cases
close to zero. PWM also works well with digital controls, which, because of their
on/off nature, can easily set the needed duty cycle.

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4.2) Analog circuits:

An analog signal has a continuously varying value, with infinite resolution in both
time and magnitude. A nine-volt battery is an example of an analog device, in that
its output voltage is not precisely 9V, changes over time, and can take any realnumbered value. Similarly, the amount of current drawn from a battery is not
limited to a finite set of possible values. Analog signals are distinguishable from
digital signals because the latter always take values only from a finite set of
predetermined possibilities, such as the set {0V, 5V}.
Analog voltages and currents can be used to control things directly, like the volume
of a car radio. In a simple analog radio, a knob is connected to a variable resistor.
As you turn the knob, the resistance goes up or down. As that happens, the current
flowing through the resistor increases or decreases. This changes the amount of
current driving the speakers, thus increasing or decreasing the volume. An analog
circuit is one, like the radio, whose output is linearly proportional to its input.
As intuitive and simple as analog control may seem, it is not always economically
attractive or otherwise practical. For one thing, analog circuits tend to drift over
time and can, therefore, be very difficult to tune. Precision analog circuits, which
solve that problem, can be very large, heavy (just think of older home stereo
equipment), and expensive. Analog circuits can also get very hot; the power
dissipated is proportional to the voltage across the active elements multiplied by the
current through them. Analog circuitry can also be sensitive to noise. Because of its
infinite resolution, any perturbation or noise on an analog signal necessarily
changes the current value.

4.3) Digital control;

By controlling analog circuits digitally, system costs and power consumption can
be drastically reduced. What's more, many microcontrollers and DSPs already
include on-chip PWM controllers, making implementation easy.
In a nutshell, PWM is a way of digitally encoding analog signal levels. Through the
use of high-resolution counters, the duty cycle of a square wave is modulated to
encode a specific analog signal level. The PWM signal is still digital because, at
any given instant of time, the full DC supply is either fully on or fully off. The
voltage or current source is supplied to the analog load by means of a repeating
series of on and off pulses. The on-time is the time during which the DC supply is
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applied to the load, and the off-time is the period during which that supply is
switched off. Given a sufficient bandwidth, any analog value can be encoded with
PWM.
Figure 4.1 shows three different PWM signals. Figure 4a shows a PWM output at a
10% duty cycle. That is, the signal is on for 10% of the period and off the other
90%. Figures 4b and 4c show PWM outputs at 50% and 90% duty cycles,
respectively. These three PWM outputs encode three different analog signal values,
at 10%, 50%, and 90% of the full strength. If, for example, the supply is 9V and the
duty cycle is 10%, a 0.9V analog signal results.

Figure 4.1: PWM signals of varying duty cycles

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4.4) CCP Modules:

The abbreviation CCP stands for Capture/Compare/PWM.
The CCP module is a peripheral which allows the user to time and control different
events.
a) Capture Mode, allows timing for the duration of an event. This circuit gives
insight into the current state of a register which constantly changes its value. In this
case, it is the timer TMR1 register.
b) Compare Mode compares values contained in two registers at some point. One
of them is the timer TMR1 register. This circuit also allows the user to trigger an
external event when a predetermined amount of time has expired.
c) PWM - Pulse Width Modulation can generate signals of varying frequency and
duty cycle.
The PIC16F887A microcontroller has two such modules - CCP1 and CCP2.

4.5) CCP1 Module

A central part of this circuit is a 16-bit register CCPR1, which consists of the
CCPR1L and CCPR1H registers. It is used for capturing or comparing with binary
number stored in the timer register TMR1 (TMR1H and TMR1L).

Fig. 4-2: CCP1 Module

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In Compare mode, if enabled by software, the timer TMR1 reset may occur on
match. Besides, the CCP1 module can generate PWM signals of varying frequency
and duty cycle.
Bits of the CCP1CON register controls the CCP1 module.

a) CCP1 in PWM mode:

Signals of varying frequency and duty cycle have a wide application in automation.
A typical example is a power control circuit whose simple operation is shown in
figure below. If a logic zero (0) represents switch-off and logic one (1) represents
switchon, the power that the load consumes will be directly proportional to the
pulse duration. This ratio is often called Duty Cycle.

Fig. 4-3: CCP1 in PWM mode

Another example, common in practice, is the usage of PWM signals in the circuit
for generating signals of arbitrary waveforms, for example, sinusoidal waveform.
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Fig. 4-4: CCP1 in PWM mode with filtration

Devices which operate in this way are often used in practice as switching regulators
which control the operation of motors (speed, acceleration, deceleration etc.).

Fig.4-5: PWM Mode

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The figure below shows the block diagram of the CCP1 module setup in PWM
mode. In order to generate a pulse of arbitrary form on its output pin, it is necessary
to determine only two values- pulse frequency and duration.

Fig. 4-6 PWM module

b) PWM Period:
The output pulse period (T) is specified by the PR2 register of the timer TMR2.
The PWM period can be calculated using the following equation:
PWM Period(T) = (PR2 +1) * 4Tosc * TMR2 Prescale Value
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If the PWM Period (T) is known then, it is easy to determine the signal frequency F
because these two values are related by equation F=1/T.

c) PWM Duty Cycle

The PWM duty cycle is specified by using in total of 10 bits: eight MSbs found in
the CCPR1L register and two additional LSbs found in the CCP1CON register
(DC1B1 and DC1B0). The result is 10-bit number contained in the formula:
Pulse Width = (CCPR1L,DC1B1,DC1B0) * Tosc * TMR2 Prescale Value

d) PWM Resolution
PWM signal is nothing more than the pulse sequence with varying duty cycle. For
one specified frequency (number of pulses per second), there is a limited number of
duty cycle combinations. This number is called resolution measured by bits. For
example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8bit resolution will result in 256 discrete duty cycles etc. In relation to this
microcontroller, the resolution is specified by the PR2 register. The maximal value
is obtained by writing number FFh.

4.6) Code for Generating the Timing Signals:

The code for generating a single PWM wave is as follows:

The output of this code obtained through digital oscilloscope is as follows:

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Fig 4.7: Single PWM wave having PWM period as 1S.

The code for generating two PWM waves is as follows:

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The output of the above code is as follows:

Fig 4.7: Two PWM waves having PWM period as 1S and 16S respectively.

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Conclusion
This project is compiled under the guidance of Mr. Samaresh Bhattacharjee, Engineer
D ARIES. While compiling I learned about TIMING SIGNAL GENERATION OF
CONTROL CARD.
While compiling I learned about "PIC Microcontroller and its programming
using mikroC Pro for PIC. I also learned about various PWM techniques and its use in producing
signals having different pulse width.
I also learned how to stimulate different circuits by using PROTEUS and also to
debug the code into a microcontroller using MPLAB ICD.

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References
1. http://www.mikroe.com/download/eng/documents/compilers/mikroc/pro/pic/help/introdu
ction_to_mikroc_pro_for_pic.htm
2. http://www.embedded.com/electronics-blogs/beginner-s-corner/4023833/Introduction-toPulse-Width-Modulation
3. http://www.mikroe.com/chapters/view/6/chapter-5-ccp-modules/
4. https://www.google.com
5. https:// www.wikipedia.com
6. https://electrosome.com/category/tutorials/pic- microcontroller/

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