5 Registers

0113611 COMPUTER HARDWARE
Registers, Register Transfers and

Counters
Dr. Fethullah Karabiber
Overview
2
Registers, Microoperations and Implementations

Registers and load enable
Register transfer operations
Microoperations - arithmetic, logic, and shift
Microoperations on a single register
Multiplexer-based transfers
n Shift registers
n
Register Cells, Buses, & Serial Operations

Control of Register Transfers
Counters
Registers
Register a collection of binary storage elements
In theory, a register is sequential logic which can be
defined by a state table
More often, think of a register as storing a vector of
binary values
Frequently used to perform simple data storage
and data movement and processing operations
Example: 2-bit Register
How many states are there?

How many input combinations?
Output combinations?
What is the output function?
What is the next state function?
Current
Moore or Mealy?
State
State Table:
A1 A0
0 0
0 1
1 0
1 1
In1
D Q
C
In0
D Q
CP
A1
A0
Y1
Y0
Next State
A1(t+1) A0(t+1)
For In1 In0 =
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
What are the quantities above for an n-bit register?
Output
(=A1 A0)
Y1
0
0
1
1
Y0
0
1
0
1
7-9
Simple Register
5
Serial
input SI
D
C
Clock
(a) Logic diagram
SRG 4
Clock
Sl
SO
(b) Symbol
2008 Pearson Education, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
Serial
output SO
Register Design Models

Due to the large numbers of states and input
combinations as n becomes large, the state diagram/
state table model is not feasible!
What are methods we can use to design registers?
Add
n
predefined combinational circuits to registers
Example: To count up, connect the register flip-flops to an incrementer
Design
individual cells using the state diagram/state table

model and combine them into a register
A 1-bit cell has just two states
n Output is usually the state variable
n
Register Storage
Expectations:
Reality:
A D flip-flop register loads information on every clock cycle
Realizing expectations:
A register can store information for multiple clock cycles

To store or load information should be controlled by a signal
Use a signal to block the clock to the register,

Use a signal to control feedback of the output of the register back to its
inputs, or
Use other SR or JK flip-flops, that for (0,0) applied, store their state
Load is a frequent name for the signal that controls register

storage and loading
Load = 1: Load the values on the data inputs

Load = 0: Store the values in the register
Registers with Clock Gating
The Load signal enables the clock signal to pass through if 1 and
prevents the clock signal from passing through if 0.
Example: For Positive Edge-Triggered or Negative Pulse
Master-Slave Flip-flop:
Clock
Load
Gated Clock to FF
What logic is needed for gating?

Gated Clock = Clock + Load
What is the problem?
Clock Skew of gated clocks with
respect to clock or each other
7-1
D0
7-1
Q0
Registers with Clock Gating

C
Clock
D0
Clock
D0
DClear
Clock
C
D1
Clear
D2
Clear
Q1
D
Q2
C
D3
D2
D
D3
Q2
R
D3
D
C
Q3
Q02
D
Q0
REG
C
D1
Q1
D2
Q2
Clear R
D0
Q0
D1 D
Q1
(b) Symbol
(a) Logic diagram
R
Load
Clock
Clock
R Clock
(c) Load control input
Load
C inputs
(d) Timing diagram
Q0
D1
Q1
D2
Q2
D3
Q3
(b) Symbol
C inputs (clock inputs
of flip-flops)

of flip-flops)

of flip-flops)
(a) Logic
diagram
2008
PearsonLoad
Education, Inc.
LOGIC ANDCCOMPUTER
DESIGN FUNDAMENTALS, 4e
inputs
Clock

M. Morris Mano & Charles
Load R. Kime
Q3
Load
Clock
Q3 Symbol
(b)
D0
D3
D2
CQ2
Load
D3
Q3
ClockR
Q3
(a) Logic diagram
REG
C
D2
Clear
D1
Q1
Q1
C
R
Clear
REG
Q0
D
D1
Q0
(d) Timing diagram
Registers with Load-Controlled Feedback
A more reliable way to selectively load a register:
Run the clock continuously, and
Selectively use a load control to change the register contents.
Example: 2-bit register

with Load Control:
2-to-1 Multiplexers
For Load = 0,
loads register contents
(hold current values)
For Load = 1,
loads input values
(load new values)
D Q
Load
In1
A1
Y1
Hardware more complex

than clock gating, but
free of timing problems
D Q
C
In0
Clock
A0
Y0
EN
D
C
C
D Flip-flop with
enable
Registers with Load-Controlled
Feedback
(a)
11
EN
D
C
D
D Flip-flop with enable
(a)
D0
D
th enable
D1
D
EN
C
Q0
D1
D
EN
C
Q1
D2
D
EN
C
Q2
D3
Load
Clock
D
EN
C
Q3
D
EN
C
Q0
D1
Q1
D
(b)
2008 Pearson Education,
EN Inc.
C DESIGN FUNDAMENTALS, 4e
LOGIC AND COMPUTER
(a)
D0
D
EN
C
D
EN
C
D
EN
C
Q0
Q1
D2
D
EN
C
(b)
D0
(b)
Q2
D
EN
C
(c)
Registers
T 7-6
7-10
12
Shift
Function Table
TABLE 7-6
Function Table for the Register of Figure 7-10
Shift
0
0
D
C 1
Q0
Load
Serial
input
D0
Load
Operation
0
1
X
No change
Load parallel data
Shift down from Q0 to Q3
Q0
D
C
D1
Q1
D
C

Q1
Q2
D
C
SHR 4
Shift
Load
Sl
D0
D1
D2
D3
D2
Q0
Q1
Q2
Q3
D3
Q3
D
C
Clock
Q3
Shift
Load
Sl
D0
D1
D2
D3
(b) S
(b) Symbol
Q2
SH

Registers
T 7-7
TABLE 7-7
Function Table for the Register of Figure 7-7
Function Table
13Mode control
Qi
S1
S0
Register
Operation
0
0
1
1
0
1
0
1
No change
Shift down
Shift up
Parallel load

Mode S1
S1
Mode S0
S0
Qi
Right serial input
MUX
S1
S1
S0
S0
Left se
D
0
1
Qi
C
LSI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
RSI
(b) Symbol
Qi
Qi
SHR 4
Clock
Left serial input
7-11
Di
Right se
Qi
D
C
Clock
(a) Logic diagram of one typical stage
Register Transfer Operations
Register Transfer Operations The movement and

processing of data stored in registers
Three basic components:
set of registers
operations
control of operations
Elementary Operations -- load, count, shift, add,

bitwise "OR", etc.
Elementary operations called microoperations
Register Transfer Operations

15
The system is partitioned into 2 types of modules:

Datapath:
performs data processing operations.

Control unit: determines the sequence of those
operations.
7-3
Datapaths are defined by their registers and the

operations performed on binary data stored in the
registers
Control signals
Control
inputs
Control
unit
Status signals
Datapath
Data
outputs
Control Data
outputs inputs
Register Notation
R
7 6 5 4 3 2 1 0
(a) Register R
(b) Individual bits of 8-bit register
T 7-115
15
R2
(c) Numbering of 16-bit register
8
PC (H)
0
PC (L)
(d) Two-part 16-bit register
TABLE 7-1
Basic Symbols for Register Transfers
Symbol
Description

Letters
(and numerals)
Parentheses
Arrow
Comma
Square brackets
Examples
Denotes a register
AR, R2, DR, IR
Denotes a part of a register

Denotes transfer of data
Separates simultaneous transfers
Specifies an address for memory
R2(1), R2(7:0), AR(L)

R1 m R2
R1 m R2, R2 m R1
DR m M[ AR]
7-5
Conditional Transfer
7-5
K1
If (K1 =1) then (R2 R1) is K1

shortened to
K1: (R2 R1)
where K1 is a control
variable specifying a
conditional execution
Clock
of the microoperation.
R1
Clock
R2
R2
t 1
Clock
K1
Clock
K1
t
R1
Transfer occurs here
Load
Trans
Load

Microoperations
Logical Groupings:
Transfer - move data from one register to another

Arithmetic - perform arithmetic on data in registers
Logic - manipulate data or use bitwise logical operations
Shift - shift data in registers
Arithmetic operations
+ Addition
Subtraction
* Multiplication
/ Division
Logical operations
Logical OR
Logical AND
Logical Exclusive OR
! Not
T 7-2
19
Register Trasfers
TABLE 7-2
Textbook RTL, VHDL, and Verilog Symbols for Register Transfers
Operation
Text RTL
VHDL
Verilog
Combinational assignment
Register transfer
Addition
Subtraction
Bitwise AND
Bitwise OR
Bitwise XOR
Bitwise NOT
Shift left (logical)
Shift right (logical)
Vectors/registers
Concatenation
=
m
+
(overline)
sl
sr
A(3:0)
||
<= (concurrent)
<= (concurrent)
+
and
or
xor
not
sll
srl
A(3 down to 0)
&
assign = (nonblocking)
<= (nonblocking)
+
&
|
^
~
<<
>>
A[3:0]
{,}

Example Microoperations
Add the content of R1 to the content of R2 and place the result

in R1.
R1 R1 + R2
Multiply the content of R1 by the content of R6 and place the
result in PC.
PC R1 * R6
Exclusive OR the content of R1 with the content of R2 and
place the result in R1.
R1 R1 R2
Example Microoperations (Continued)
Take the 1's Complement of the contents of R2 and place it

in the PC.
PC R2
On condition K1 OR K2, the content of R1 is Logic bitwise
Ored with the content of R3 and the result placed in R1.
(K1 + K2): R1 R1 R3
NOTE: "+" (as in K1 + K2) and means OR.
In R1 R1 + R3, + means plus.
Control Expressions
The control expression for an

operation appears to the left
of the operation and is
separated from it by a colon
Control expressions specify
the logical condition for the
operation to occur
Control expression values of:
Logic "1" -- the operation

occurs.
Logic "0" -- the operation is
does not occur.
Example:
X K1 : R1 R1 + R2
X K1 : R1 R1 + R2 + 1
Variable K1 enables the add
or subtract operation.
If X =0, then X =1 so
X K1 = 1, activating the
addition of R1 and R2.
If X = 1, then X K1 = 1,
activating the addition of
R1 and the two's
complement of R2
(subtract).
Arithmetic Microoperations
TABLE 7-3
Arithmetic Microoperations
Symbolic
designation
Description
R0 m R1 + R2
Contents of R1 plus R2 transferred to R0
R2 m R2
Complement of the contents of R2 (1s complement)
R2 m R2 + 1
2s complement of the contents of R2
R0 m R1 + R2 + 1
R1 plus 2s complement of R2 transferred to R0 (subtraction)
R1 m R1 + 1
Increment the contents of R1 (count up)
R1 m R1 1
Decrement the contents of R1 (count down)
Note that any register may be specified for source 1,

source 2, or destination.
These simple microoperations operate on the whole
word

Adder/ Subtracter Unit

24 XK1 : R1 R1+R2
XK1 : R1 R1+R2+1
Overflow
output
Logical Microoperations
TABLE 7-4
Logic Microoperations
Symbolic
designation
Description
R0 m R1
R0 m R1 R2
R0 m R1 R2
R0 m R1 R2
Logical bitwise NOT (1s complement)

Logical bitwise AND (clears bits)
Logical bitwise OR (sets bits)
Logical bitwise XOR (complements bits)
Let R1 = 10101010, and R2 = 11110000

Then after the operation, R0 becomes:

R0
01010101
LOGIC AND COMPUTER DESIGN FUNDAMENTALS,
4e
Operation
11111010
10100000
R0 ! R1
R0 ! R1 " R2
R0 ! R1 # R2
01011010
R0 ! R1 $ R2
Shift Microoperations
TABLE 7-5
Examples of Shifts
Eight-bit examples
Type
shift left
shift right
Symbolic
designation
Source R2
After shift:
Destination R1
R1m sl R2
R1m sr R2
10011110
11100101
00111100
01110010
Note: These shifts "zero fill". Sometimes a separate flipflop is used to provide the data shifted in, or to catch
2008 Pearson Education,
Inc.
the data
shifted out.

Other shifts are possible (rotates, arithmetic).
Register Cell Design
Assume that a register consists of identical cells

Then register design can be approached as
follows:
Design representative cell for the register
Connect copies of the cell together to form the register
Applying appropriate boundary conditions to cells
that need to be different and contract if appropriate
Register cell design is the first step of the above

process
Register Cell Specifications
A register
Data inputs to the register
Control input combinations to the register
Example 1: Not encoded

Control inputs: Load, Shift, Add
n At most, one of Load, Shift, Add is 1 for any clock cycle
(0,0,0), (1,0,0), (0,1,0), (0,0,1)
n
Example 2: Encoded
Control inputs: S1, S0
n All possible binary combinations on S1, S0
(0,0), (0,1), (1,0), (1,1)
n
Register Cell Specifications
A set of register functions (typically specified as

register transfers)
Example:
Load: A B
Shift: A sr B
Add: A A + B
A hold state specification
Example:
Control inputs: Load, Shift, Add
n If all control inputs are 0, hold the current register state
n
Example 1: Register Cell Design
Register A (m-bits) Specification:

Data
input: B
Control inputs (CX, CY)
Control input combinations (0,0), (0,1) (1,0)
Register transfers:
CX : A B v A
CY : A B + A
Hold state: (0,0)
Example 1: Register Cell Design (continued)
Load Control
Load = CX + CY
Since all control combinations appear as if

encoded (0,0), (0,1), (1,0) can use multiplexer
without encoder:
S1 = CX
S0 = CY
D0 = Ai
D1 = Ai Bi + Ai
D2 = Ai Bi v Ai
Hold A
CY = 1
CX = 1
Note that the decoder part of the 3-input

multiplexer can be shared between bits if desired
Sequential Circuit Design Approach
Find a state diagram or state table

Note
that there are only two states with the state

assignment equal to the register cell output value
Use the design procedure in Chapter 5 to complete

the cell design
For optimization:
Use
K-maps for up to 4 to 6 variables

Otherwise, use computer-aided or manual optimization
Example 1 Again
State Table:
Hold
Ai
CX = 0
CY = 0
Ai v Bi
Ai + Bi
CX = 1 CX = 1 CY = 1
Bi = 0 Bi = 1 Bi = 0
CY = 1
Bi = 1
0
0
0
1
0
1
1
1
1
1
1
0
Four variables give a total of 16 state table entries
By using:
Combinations of variable names and values
n Don t care conditions (for CX = CY = 1)
n
only 8 entries are required to represent the 16 entries
Example 1 Again (continued)
K-map - Use variable ordering CX, CY, Ai Bi and assume a

D flip-flop
Di
CX
Ai
X X
Bi
CY
Example 1 Again (continued)

The resulting SOP equation:
Di = CX Bi + CY Ai Bi + Ai Bi + CY Ai
Using factoring and DeMorgan s law:
Di = CX Bi + Ai (CY Bi) + Ai(CY Bi )
Di = CX Bi + Ai + (CY Bi)
The gate input cost per cell = 2 + 8 + 2 + 2 = 14
The gate input cost per cell for the previous version
is:
Per cell: 19
Shared decoder logic: 8
Cost gain by sequential design > 5 per cell

Also, no Enable on the flip-flop makes it cost less
Register Transfer Structures
Multiplexer-Based Transfers - Multiple inputs are selected by a

multiplexer dedicated to the register
Bus-Based Transfers - Multiple inputs are selected by a shared
multiplexer driving a bus that feeds inputs to multiple registers
Three-State Bus - Multiple inputs are selected by
3-state drivers with outputs connected to a bus that feeds
multiple registers
Other Transfer Structures - Use multiple multiplexers, multiple
buses, and combinations of all the above
Multiplexer-Based Transfers
Multiplexers connected to register inputs produce flexible

transfer structures (Note: Clocks are omitted for clarity)
The transfers are:
R0 R1
K1:
K2 K1: R0 R2
K2
4
R2
K1
0
S
MUX
Load
4
1
4
R1
(a) Block diagram

K2
K1
R2
R0
Multiplexer Approach
7-8
Uses an n-input multiplexer with a variety of transfer sources

and functions
K0
Kn
Dedicated
logic 0
...
Dedicated
logic k 1
.
.
.
4
4
...
Encoder
.
.
.
.
.
.
.
.
.
Registers or
shared logic
.
.
.
0 Sm S0
.
.
. MUX
k 1
k
.
.
.
n 1
Load
4
R0
Multiplexer Approach
Load enable by OR of control signals K0, K1, Kn-1

- assumes no load for 000
7-8
Use
Encoder + Multiplexer (shown) or n x 2 AND-OR to select sources
and/or transfer functions
K0
Kn
Dedicated
logic 0
...
Dedicated
logic k 1
.
.
.
4
4

...
Encoder
.
.
.
.
.
.
.
.
.
Registers or
shared logic
.
.
.
0 Sm S0
.
.
. MUX
k 1
k
.
.
.
n 1
Load
4
R0
Multiplexer and Bus-Based Transfers for Multiple Registers
Multiplexer dedicated to each register

Shared transfer paths for registers
shared transfer object is a called a bus (Plural: buses)
Bus implementation using:

multiplexers
three-state
nodes and drivers
In most cases, the number of bits is the length of the

receiving register
Dedicated MUX-Based Transfers

7-19
Multiplexer connected to
each register input
produces a very flexible
transfer structure =>
Characterize the
simultaneous transfers
possible with this
structure.
Select
S0 S1 S2
Load
L0 L1 L2
S
2-to-1
1 MUX
0
n
R0
Select
S
2-to-1
1 MUX
0
0
R1
SS11 S0
1 3-to-1
MUX
02
n
S
2-to-1
1 MUX
0
n
R2
(a) Dedicated multiplexers

(b
Multiplexer Bus
7-19
Select
S0 S1 S2
A single bus driven by a

multiplexer lowers
cost,
but
S
0
n
2-to-1
limits the available
transfers
1 MUX
R0
=>
n
Characterize the
possible with this0 structure.
S
n
2-to-1
MUX savings
Characterize the
1 cost
R1
TABLE 7-13
n
compared to
Examples of Register Transfers Using the Single Bus
dedicated
multiplexers
in Figure
7-19(b)
T 7-13
Load
L0 L1 L2
Select
S
0
S1
S0
2-to-1
R0 j R2
R0 j R1, R2 j R1
R0 j R1, R1 j R0
1
0
0n
1
n L2
L1
R2
0
0
1
0
Impossible
(a) Dedicated multiplexers

LOGIC
AND
LOGIC AND COMPUTER DESIGN FUNDAMENTALS,
4e COMPUTER DESIGN
n
n
R0
Select
SS11 S0
1 3-to-1
MUX
2
0
n
n
Bus
R1
Load
Register Transfer
1 MUX
Load
L0 L1 L2
FUNDAMENTALS, 4e
L0
1
1
R2
(b) Single bus
7-20
Three-State Bus
Load
L0 L1 L2
7-20
Load
L0 L1 L2
The 3-input MUX can be

Load
replaced by a 3-state node
n
Load
LOAD
n
(bus) and 3-state buffers.
R0
n
R
LOAD
n
n n
Cost is further reduced,
butSelect
R
2
n
transfers are limited
EN
n
Characterize the
n
EN
3to1
R1
Bus
Load
MUX
possible with Load
this structure. n
n
R
CharacterizeR then cost
n
savings and compare
EN
n
EN
(a) Register with bidirectional
inputoutput lines and symbol
Load
L2 L1 L0
Enable
E2 E1 E0
R0
n
n
R2
(a) Register with bidirectional

inputoutput
lines and
(b) Multiplexer
bus symbol
n Bus
R0
Select
2
EN
3to1
MUX
R1
Bus
n
R1
n
EN
n
n
R2
R2
(b) Multiplexer
bus
EN
(c) Three-state bus using
registers with bidirectional
lines


Serial Transfers and Microoperations
Serial Transfers
Used
for narrow transfer paths

Example 1: Telephone or cable line
Parallel-to-Serial conversion at source
n Serial-to-Parallel conversion at destination
n
Example
2: Initialization and Capture of the contents of

many flip-flops for test purposes
Add shift function to all flip-flops and form large shift register
n Use shifting for simultaneous Initialization and Capture operations
n
Serial microoperations
Example
1: Addition
Example 2: Error-Correction for CDs
7-21
Serial Transfer
45
Shift
Clock
C
0
Register A
SRG 4
C
SO
SI
Register B
SRG 4
SO
SI
(a) Block diagram

Clock
Shift
C inputs
T 7-14
T1
T3
T2
T4
TABLE
7-14diagram
(b) Timing
Example of Serial Transfer
Timing
pulse
Shift Register A
Initial value
After T1
After T2
After T3
After T4
1
0
0
0
0

Example of
Serial Transfer
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
Shift Register B
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
Serial Microoperations
By using two shift registers for operands, a full adder, and a flip
flop (for the carry), we can add two numbers serially, starting at
the least significant bit.
Serial addition is a low cost way to add large numbers of
operands, since a tree of full adder cells can be made to any
depth, and each new level doubles the number of operands.
Other operations can be performed serially as well, such as
parity generation/checking or more complex error-check codes.
Shifting a binary number left is equivalent to multiplying by 2.
Shifting a binary number right is equivalent to dividing by 2.
Serial Adder
The circuit shown uses two shift

registers for operands A(3:0)
and B(3:0).
A full adder, and one more
flip flop (for the carry) is used
to compute the sum.
The result is stored in the
A register and the final
carry in the flip-flop
Load/Right Shift Registers

Serial
In
FA
A3 A2 A1 A0
Parallel Load
Cin
Serial
In
Sum
Cout
B3
B2 B1 B0
Parallel Load
(Clock and Load/Shift
Control not shown)
With the operands and the

result in shift registers, a tree of full adders can be
used to add a large number of operands. Used as a common
digital signal processing technique.
CP
Serial Adder
48
Counters
Counters are sequential circuits which "count" through a

specific state sequence. They can count up, count down, or
count through other fixed sequences. Two distinct types are
in common usage:
Ripple Counters
Clock connected to the flip-flop clock input on the LSB bit flip-flop
For all other bits, a flip-flop output is connected to the clock input,
thus circuit is not truly synchronous!
Output change is delayed more for each bit toward the MSB.
Resurgent because of low power consumption
Synchronous Counters
Clock is directly connected to the flip-flop clock inputs

Logic is used to implement the desired state sequencing
Ripple Counter
C
ha
pt
er
7Pa
rt
2
50
How does it work?

When
there is a positive
edge on the clock input
of A, A complements
The clock input for flipflop B is the complemented
output of flip-flop A
When flip A changes
from 1 to 0, there is a CP
positive edge on the
A
clock input of B
causing B to
B
complement
0
D
Clock
CR
D
CR
Reset
Ripple Counter (continued)

The arrows show the
cause-effect relation- CP
ship from the prior
A
slide =>
B
The corresponding
0 1
2
3
sequence of states => 0 1
(B,A) = (0,0), (0,1), (1,0), (1,1), (0,0), (0,1),
Each additional bit, C, D, behaves like bit B,
changing half as frequently as the bit before it.
For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1),
(1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0),

7-12
These circuits are called ripple

counters because each edge
sensitive transition (positive in the
example) causes a change in the
next flip-flop s state.
The changes ripple upward
through the chain of flip-flops, i.
e., each transition occurs after a
clock-to-output delay from the
stage before.
To see this effect in detail look at
the waveforms on the next slide.
D
C
R
Clock pulse

Reset
D
C
R
D
C
R
D
C
R
Starting with C = B = A = 1, equivalent to (C,B,A)

= 7 base 10, the next clock increments the count to
(C,B,A) = 0 base 10. In fine timing detail:
The
clock to output delay

tPHL causes an increasing
delay from clock edge for
each stage transition.
Thus, the count ripples
from least to most
significant bit.
For n bits, total worst case
delay is n tPHL.
CP
A
tPHL
tPHL
tpHL
B
C
Synchronous Counters
C
ha
pt
er
7Pa
rt
2
54
To eliminate the "ripple" effects, use a common clock for

each flip-flop and a combinational circuit to generate the
next state.
For an up-counter,
use an incrementer =>
Incre-
T 7-8
TABLE 7-8
Counting Sequence of Binary Counter
Upward Counting Sequence
Downward Counting Sequence
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

menterS3
D3 Q3
A2
S2
D2 Q2
A1
S1
D1 Q1
A0
S0
D0 Q0
A3
Clock
Synchronous Counters (continued)
Internal details =>

Internal Logic
Count enable EN
XOR complements each bit

AND chain causes complement
of a bit if all bits toward LSB
from it equal 1
Q1
Q2
Forces all outputs of AND

chain to 0 to hold the state
Added as part of incrementer
Connect to Count Enable of
additional 4-bit counters to
form larger counters
EN
Carry Out
Q0
Count Enable
7-13
Q3
C
Carry
output CO
Clock
(a) Logic diagram-serial gating
(b) Logic dia
CTR 4
EN
Q0
Q1
Q2
Q3
7-13
Q0
Synchronous Counters (continued)

Count enable EN
EN
Q0
Q1
7-13
Count enable EN
Carry chain
D
C
series of AND gates through which the

carry ripples
D
D
C
Yields long path delays
C
Called serial gating
Q0
Q1
Q1
C1 C2
Q2
C2
Carry
output CO
Reduces path delays

Clock
D
Q3
Called parallel gating
(a) Logic diagram-serial gating
C
Like carry lookahead
CTR 4
Carry
Lookahead can be used on COs
Q0
EN output
CO
Clock
Q
and ENs to prevent long paths in
1
Q
2
large counters (a) Logic diagram-serial gating
Q3
2008 Pearson
Inc.
Symbol
forEducation,
Synchronous
Counter
EN
Q2
CTR 4
C1
Q1 Q2
D
Q
Replace AND carry chain with ANDs
=>
D
Q
C
C
in parallel
Q0
CO
Q0
EN(c) Symbol
Q1
Q2
Q3
CO
Q3
C3
Q3
C3 CO
(b) Logic diagram-parallel gating
CO
(b) Logic diagram-parallel gating
Other Counters
See text for:

Down
Counter - counts downward instead of upward

Up-Down Counter - counts up or down depending on value a control
input such as Up/Down
Parallel
Load Counter - Has parallel load of values available
depending on control input such as Load
Divide-by-n (Modulo n) Counter

Count
is remainder of division by n; n may not be a power

of 2 or
Count is arbitrary sequence of n states specifically designed
state-by-state
Includes modulo 10 which is the BCD counter
Counter with Parallel Load

7-14
Count
enabled for Load = 1
D0
Add logic to:
Load
Add path for input data
Q0
disable count logic for Load = 1

disable feedback from outputs
for Load = 1
enable count logic for Load = 0
and Count = 1
D1
D2
Hold Stored Value
Count Up Stored Value
Load D
Q2
Action
Q1
The resulting function table:

Load Count
D3
Q3
Clock

Carry
Output CO
Counter w/ Unused States

59
n flip-flops 2n binary states

Unused states: states that are not used in
specifying the sequential ckt
maybetreatedasdont-careconditionsor
may be assigned specific next states Selfcorrecting counter:
Ensure
that when a ckt enter one of its unused states, it

eventually goes into one of the valid states after one or
more clock pulses so it can resume normal operation.
n Analyze
the ckt to determine the next state from an unused

state after it is designed.

60
Example:
Example:
Example:
The
Thesimplified
simplifiedf-f
f-finput
inputeqs:
eqs:
DDA AABB
A
DDB CC
B
DDC BBCC
C
Two unused states: 011 & 111

Two unused states: 011 & 111
J.J. Shann 7-44

J.J. Shann 7-44

7-16
7-16
61
ABC
ABC
Reset
Reset
000
000
110
110 011
011001
101
111
010
D
C
101
111
100
(b)
100
(b)
Clock
Reset
Clock
Reset

(a)
(a)
001
010
Design Example: Synchronous BCD

Use the sequential logic model to design a synchronous BCD
counter with D flip-flops
Input combinations 1010 through 1111 are don t cares
T 7-9
TABLE 7-9
State T able and Flip-Flop Inputs for BCD Counter
Present State
Next State
Q8
Q4
Q2
Q1
D8 = D 4 =
D2 =
Q8(t+1) Q4(t+1) Q2(t+1)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
0

0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
Output
D1 =
Q1(t+1)
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
Synchronous BCD (continued)

Use K-Maps to two-level optimize the next state equations and
manipulate into forms containing XOR gates:
D1 = Q1
D2 = Q2 + Q1Q8
D4 = Q4 + Q1Q2
D8 = Q8 + (Q1Q8 + Q1Q2Q4)
The logic diagram can be draw from these equations

An asynchronous or synchronous reset should be added
What happens if the counter is perturbed by a power

disturbance or other interference and it enters a state other
than 0000 through 1001?

C Find the actual values of the six next states for the don t
ha
care combinations from the equations
pt Find the overall state diagram to assess behavior for the
er
don t care states (states in decimal)
70
Present State
Next State
9
1
Pa
14
rt Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1
1 0 1 0
1 0 1 1
2
2
8
15
64 1 0 1 1 0 1 1 0
12
1
13
11
10
6
5
3
4
For the BCD counter design, if an invalid state is entered,

return to a valid state occurs within two clock cycles
Is this adequate? If not:
The action to be taken depends on:
Is a signal needed that indicates that an invalid state has been

entered? What is the equation for such a signal?
Does the design need to be modified to return from an invalid state
to a valid state in one clock cycle?
Does the design need to be modified to return from a invalid state
to a specific state (such as 0)?
the application of the circuit
design group policy
See pages 244 of the text.
Three Decade Decimal Counter
Three-decade BCD counter:
66
J.J. Shann 7-42
Counting Modulo N
The following techniques use an n-bit binary counter with

asynchronous or synchronous clear and/or parallel load:
Detect a terminal count of N in a Modulo-N count sequence to

asynchronously Clear the count to 0 or asynchronously Load in value 0
(These lead to counts which are present for only a very short time and can
fail to work for some timing conditions!)
Detect a terminal count of N - 1 in a Modulo-N count sequence to Clear the
count synchronously to 0
Detect a terminal count of N - 1 in a Modulo-N count sequence to
synchronously Load in value 0
Detect a terminal count and use Load to preset a count of the terminal
count value minus (N - 1)
Alternatively, custom design a modulo N counter as done for BCD
A BCD Counter
687-15
Generate any count sequence:
E.g.: design a BCD counter by using a counter w/ parallel load &

async clear
CTR 4
Clock
Load
1
(Logic 0)
Count
D0
Q0
Q0
D1
Q1
Q1
D2
Q2
Q2
D3
Q3
Q3
CO
Counting Modulo 6: Synchronously Preset 9 on Reset

and Load 9 on Terminal Count 14
A synchronous, 4-bit binary

1
counter with a synchronous
0
Load is to be used to make a
Modulo 6 counter.
0
1
Use the Load feature to
preset the count to 9 on
Clock
Reset and detection of Reset
count 14.
1
D3
Q3
D2
Q2
D1
Q1
D0
Q0
CP
LOAD
CLEAR
This gives a count of 9, 10, 11, 12, 13, 14, 9, 10, 11, 12,
13, 14, 9,
If the terminal count is 15 detection is usually built in as
Carry Out (CO)
Counting Modulo 7: Detect 7 and Asynchronously Clear

C
ha
pt
er
7Pa
rt
2
70
A synchronous 4-bit binary counter

with an asynchronous Clear is
used to make a Modulo
7 counter.
Use the Clear feature to
detect the count 7 and
clear the count to 0. This
gives a count of 0, 1, 2, 3, 4, Clock
0
5, 6, 7(short)0, 1, 2, 3, 4, 5,
6, 7(short)0, etc.
D3
Q3
D2
Q2
D1
Q1
D0
Q0
CP
LOAD
CLEAR
DON T DO THIS! Existence of state 7 may not be long enough

to reliably reset all flip-flops to 0. Referred to as a suicide
counter! (Count 7 is killed, but the designer s job may be
dead as well!)
Counting Modulo 7: Synchronously Load on Terminal Count of 6
A synchronous 4-bit binary

0
counter with a synchronous
0
load and an asynchronous
0
clear is used to make a
0
Modulo 7 counter
Clock
Use the Load feature to
detect the count "6" and
Reset
load in "zero". This gives
a count of 0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 0, ...
Using don t cares for states
above 0110, detection of 6 can be done
with Load = Q4 Q2
D3
Q3
D2
Q2
D1
Q1
D0
Q0
CP
LOAD
CLEAR
4-bit Shift Register with Reset

72
library ieee;
use ieee.std_logic_1164.all;
entity srg_4_r is
port(CLK, RESET, SI : in std_logic;
Q : out std_logic_vector(3 downto 0);
SO : out std_logic);
end srg_4_r;
4-bit Shift Register with Reset

73
architecture behavioral of srg_4_r is

signal shift : std_logic_vector (3 downto 0);
begin
process (RESET, CLK)
begin
if (RESET = '1') then
shift <= "0000;
elsif (CLK'event and (CLK = '1')) then
shift <= shift(2 downto 0) & SI;
end if;
end process;
Q <= shift;
SO <= shift(3);
end behavioral;
4-bit Binary Counter with Reset

74
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_4_r is
port(CLK, RESET, EN : in std_logic;
Q
: out std_logic_vector(3 downto 0);
CO
: out std_logic);
end count_4_r;
4-bit Binary Counter with Reset

75 architecture behavioral of count_4_r is
signal count : std_logic_vector(3 downto 0);
begin
process (RESET, CLK)
begin
if (RESET = '1') then
count <= "0000;
elsif (CLK'event and (CLK = '1') and (EN = '1')) then
count <= count + "0001;
end if;
end process;
CO <= '1' when count = "1111" and EN = '1' else '0;
Q <= count;
end behavioral;

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0113611 COMPUTER HARDWARE

Registers, Register Transfers and

Dr. Fethullah Karabiber

Registers, Microoperations and Implementations

Register Cells, Buses, & Serial Operations

Example: 2-bit Register

How many states are there?

What are the quantities above for an n-bit register?

2008 Pearson Education, Inc.

Register Design Models

predefined combinational circuits to registers

Example: To count up, connect the register flip-flops to an incrementer

individual cells using the state diagram/state table

A D flip-flop register loads information on every clock cycle

A register can store information for multiple clock cycles

Use a signal to block the clock to the register,

Load is a frequent name for the signal that controls register

Load = 1: Load the values on the data inputs

Registers with Clock Gating

What logic is needed for gating?

Registers with Clock Gating

(c) Load control input

(c) Load control input

(d) Timing diagram

C inputs (clock inputs

C inputs (clock inputs

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(d) Timing diagram

Registers with Load-Controlled Feedback

A more reliable way to selectively load a register:

Run the clock continuously, and

Selectively use a load control to change the register contents.

Example: 2-bit register

Hardware more complex

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Right serial input

Left serial input

Register Transfer Operations

Register Transfer Operations The movement and

Elementary Operations -- load, count, shift, add,

Elementary operations called microoperations

Register Transfer Operations

The system is partitioned into 2 types of modules:

performs data processing operations.

Datapaths are defined by their registers and the

(b) Individual bits of 8-bit register

(d) Two-part 16-bit register

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AR, R2, DR, IR

Denotes a part of a register

R2(1), R2(7:0), AR(L)

If (K1 =1) then (R2 R1) is K1

Transfer occurs here

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Transfer - move data from one register to another

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Add the content of R1 to the content of R2 and place the result

Example Microoperations (Continued)

Take the 1's Complement of the contents of R2 and place it

The control expression for an

Logic "1" -- the operation

Contents of R1 plus R2 transferred to R0