HDL Models
Dataflow modeling
Uses continuous assignment statements with keyword assign
Behavioral modeling
Uses procedural assignment statements with keyword always
Verilog II
Gate-level Modeling
Predefined primitives
12 basic gates
and, nand, or, nor, xor, xnor, not,
buf others
Most are n-input, 1-output
buf and not are single-input n-output primitives
A single input can be connected to multiple lines
not( in, out1, out2, out2)
Verilog II
I. Gate-level Modeling
Verilog II
Logic Values
x (for unknown)
Table 4.9
Vectors
Multi-bit widths are called vectors.
output [0:3] D;
Output vector D, 4 bits wide, numbered 0 thru 3.
D[2] specifies bit 2 of D .
The first number (on the left) is the index of the most significant bit (MSB).
Bit numbering can go either way (MSB to LSB or LSB to MSB).
wire
[7:0] SUM
Example 4.1
// HDL example 4.1
// Gate-level description of 2-to-4 decoder
module decoder( D, A, B, enable );
output [0:3] D;
// vector of 4 bits
input A, B;
input enable;
wire
Anot, Bnot, enableNot;
not
G1 (Anot, A),
G2 (Bnot, B),
G3 (enableNot, enable);
nand
G4 (D[0],
G5 (D[1],
G6 (D[2],
G7 (D[3],
endmodule
Anot,
Anot,
A,
A,
Bnot,
B,
Bnot,
B,
enableNot
enableNot
enableNot
enableNot
Verilog II
),
),
),
);
FIGURE 4.19
10
(continued)
Verilog II
11
FIGURE 4.5
FIGURE 4.8
FIGURE 4.9
Four-bit adder
15
Test
Verilog II
16
Three-state Gates
Three-state gates have output values 0, 1, or z.
z is high impedance
Verilog gates:
bufif1
Output
Output
bufif0
Output
Output
notif1
Output
Output
notif0
Output
Output
is z when control is 0
is same as input when control is 1
is z when control is 1
is same as input when control is 0
is z when control is 0
is inverted input when control is 1
is z when control is 1
is same as input when control is 0
Verilog II
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FIGURE 4.32
Three-state gates
Verilog II
19
FIGURE 4.33
Notetri
connection
Verilog II
21
Dataflow Modeling
Dataflow modeling uses operands that act on binary operands and
produce binary results.
Be careful to distinguish binary addition + from AND operation &
assign gives a value to a net data type.
Net data types represent a physical connection between circuit
elements, e.g. wire, or a port
assign Y = Boolean Expression using variables and operators.
continuous assignment : expression is always true as simulation runs
(compare with procedural assignment : happens once, when the
statement gets control.)
Verilog II
22
Operators
Concatenation operator is { operand , operand }
braces enclosing operands separated by comma
Equality test is == (two equal signs)
Bitwise AND is &
operates on a vector of bits, does AND between
bits in same position to produce a vector of bits
Logical AND is &&
operates on a single true/false value to produce
a single true/false value. Non-0 is regarded as
true (as in programming language C).
Verilog II
23
Table 4.10
slide 8
=
=
=
=
!
!
!
!
( !A && !B &&
( !A && B &&
( A && !B &&
( A && B &&
!enable
!enable
!enable
!enable
),
),
),
);
endmodule
Verilog II
25
Verilog II
26
Conditional Operator
Condition ? trueExpression : falseExpression
The Condition is evaluated.
If true, the value of the entire expression is trueExpression.
If false, the value of the entire expression is falseExpression.
// Dataflow description of a 2-to-1 mux
//
module mux ( m_out, A, B, select);
output m_out;
input
A, B, select;
assign
endmodule
m_out = select ? A: B ;
Verilog II
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Verilog II
28
Behavioral Modeling
Represents digital circuits at an algorithmic level.
keyword initial indicates a process that starts running when the
simulation starts, but runs just once.
keyword always indicates a process that starts waiting for a
trigger when the simulation starts.
keyword always is followed by an event control expression,
and then a list of procedural assignment statements.
29
always
always @(a or b)
begin
if (a)
c = b;
else
d = ~b;
end
// End of block
30
loop
always
begin
// Always begins executing at time 0 and NEVER stops
clk = 0;
// Set clk to 0
#1;
// Wait for 1 time unit
clk = 1;
// Set clk to 1
#1;
// Wait 1 time unit
end
// Keeps executing - so continue back at the top of the begin
Verilog II
31
Mux Example
// Behavioral description of 2-to-1-line multiplexer
// HDL Example 4.7
module mux2x1(OUT, A, B, select);
input A,B,select;
output OUT;
reg OUT;
// OUT must be reg type since it is assigned to
always @ (A or B or select)
if (select == 1) OUT = A;
else OUT = B;
endmodule
Verilog II
32
case Example
//Behavioral description of 4-to-1-line multiplexer
//Describes the function table of Fig. 4-25(b).
module mux4x1_bh (i0, i1, i2, i3, select, y);
input i0,i1,i2,i3;
input [1:0] select;
output y;
reg y;
always @ (i0 or i1 or i2 or i3 or select)
case (select)
2'b00: y = i0;
2'b01: y = i1;
2'b10: y = i2;
2'b11: y = i3;
endcase
endmodule
Verilog II
33
FIGURE 4.25
Four-to-one-line multiplexer
Test Benches
Verilog II
35
Test Bench
behavioral statements.
The test bench contains the output statements, like
$display or $monitor.
Analogy to actual electronics lab:
The circuit is a breadboard containing the electronic components.
The circuit is tested with signal generators, probes, and scopes.
Verilog II
36
Time Delays
initial
begin
A = 0; B = 0;
#10 A = 1;
#20 A = 0; B = 1;
end
Verilog II
37
repeat
repeat(n) specifies that a block will be repeated n times.
initial
begin
D = 3b000;
repeat(7)
#10 D = D + 3b001;
end
Verilog II
38
Usual Form
module testBenchName;
// declare local reg and wire identifiers
// instantiate the circuit module, binding local
//
identifiers to modules identifiers
// generate a sequence of stimulus values
//
using always and initial
// display the output of the module
endmodule
Test modules usually have no inputs nor outputs, but create inputs for
the circuit under test and display that circuits outputs.
When the circuit model is instantiated, the identifiers in the test
bench are bound to the formal identifiers in the circuit model.
-- like variables of main bound to parameters of a function.
Verilog II
39
FIGURE 4.34
System Tasks
Verilog II
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