Microelectronics Reliability 43 (2003) 20772086

www.elsevier.com/locate/microrel

Eect of voids on the reliability of BGA/CSP solder joints

Mohammad Yunus
b

a,*

, K. Srihari b, J.M. Pitarresi c, Anthony Primavera

a
Semiconductor Packaging Development, Texas Instruments Inc., Dallas, TX 75265, USA
Department of Systems Science and Industrial Engineering, Watson School of Engineering and Applied Sciences,
State University of New York at Binghamton, Binghamton, NY 13902, USA
c
Department of Mechanical Engineering, Watson School of Engineering and Applied Sciences,
State University of New York at Binghamton, Binghamton, NY 13902, USA
d
Area Array Consortium, Universal Instruments Corporation, Binghamton, NY 13907, USA

Received 3 February 2003; received in revised form 20 April 2003

Abstract
Voids in solder joints have been considered as a defect in electronics assembly. The factors that aect void formation
are complex and involve the interaction of many factors. There are no established standards for void size and void area
in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The eect of voids on the
reliability of solder joint may depend not only on the size, but also on frequency and location. This study is focussed on
investigating the eect of voids on the reliability of solder joints. The size, location and frequency eects on the reliability were studied. Testing was done by mechanical deection testing (torsion) system and air to air thermal cycling
()40
C/125
C). Failures were analyzed for the failure modes by cross sectional analysis. The results indicate that voids
reduce the life of the solder joint. Voids which are greater than 50% of the solder joint area, decrease the mechanical
robustness of the solder joints. Small voids also have an eect on the reliability, but it is dependent on the void frequency and location.
 2003 Published by Elsevier Ltd.

1. Introduction
With the continual miniaturization of electronic
components and their increasing functionality, the
electronics industry is rapidly switching towards ne
pitch devices. Area array components have evolved as a
viable solution to the requirement of the industry. With
area array devices, the solder joint reliability becomes
one of the most critical factors as, with ner pitches a
smaller amount of solder paste is deposited and the
solder ball size is also reduced. Void formation in solder
joint is one of the many critical factors governing the
solder joint reliability. Voids may degrade the mechanical robustness of the board level interconnection and
consequently aect the reliability and the conducting
performance of the solder joint.

Corresponding author.
E-mail address: m-yunus2@ti.com (M. Yunus).

0026-2714/$ - see front matter  2003 Published by Elsevier Ltd.

doi:10.1016/S0026-2714(03)00124-0

Voids are dened as cavities formed in the solder

joint. Voids are caused by the amount of outgassing ux
that gets entrapped in the solder joint during reow [1].
The outgassing substance is generally produced by the
evaporation of the solvent in the solder paste and the
rheological additives in the solder paste that may evaporate in the heating process during reow [2]. The
outgassing substance may also be generated by the metallization of the substrate, component or the solder
powder surface during the uxing reaction in the reow
process. Previous studies have indicated that the reow
process and the solder material are the most signicant
factors that aect void formation [3].
The location and the size of solder joints are perhaps
the key factors that inuence the eect of voids on the
performance and reliability of solder joints. It has been a
common observation that voids in solder joints tend to
accumulate towards the top of the solder joint (the interface between the package and the solder joint). Voids
which are essentially gas bubbles have a lower density

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M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

than molten solder. The buoyancy of these regions cause

the bubbles to rise to the top of the solder joints [4].
A solder joint in an electronic assembly serves electrical, mechanical, and thermal functions, the most important being the conduction of electrical signals.
Consequently, the resistance of the solder joint should
be as low as possible and there should not be much
deviation in resistance between adjacent solder joints in
order to achieve uniform conductivity. Empirically, it
has been observed that the resistance of the solder joint
will increase with the occurrence of large (or many)
voids as the cross sectional area of the solder joint is
considerably reduced.
The mechanical function of the solder joint is to
provide the connection and support to the component.
The electronic component is continuously aected by the
stress and strain as a result of the mismatch in the coecient of thermal expansion, and the solder joint
should be able to withstand all the stress and strain
imposed on the component. Yet another function of the
solder joint is to dissipate the heat generated on the
electronic component. An active component in use can
produce a signicant amount of heat during its operation and this heat needs to be dissipated to prevent
overheating or the breakdown of the component. The
conductive heat transfer through the solder joint can be
modeled based on Fouriers law as follows:
Q KAT 1  T 2=L
where Q is the heat transferred, K is the thermal conductivity, A is the cross sectional area of the solder joint,
L is the length of the solid element and T 1 and T 2 are the
temperature of the source and sink.
It can be inferred from the above equation that the
heat transferred is directly proportional to the cross
sectional area. A solder joint with voids may have a
greater diameter or an increased stando to maintain the
same volume in the solder joint. However, the area of
cross section may or may not be the same. A solder joint
with voids may have a smaller area, which may interrupt
the ow of heat.
Solder joint reliability is an interaction of many factors which include design and process parameters.
Voids, which arise as a result of process parameter has
been observed as a critical factor that aects solder joint
reliability. It has been dicult to study the eect of voids
on the reliability of solder joint, as it has been an uncontrolled factor in the assembly process and it has been
dicult to isolate the eect of voids on the reliability of
solder joint. Numerous studies have been conducted in
the past to study the eect of voids, but most of the
results have been contradictory, with some showing a
positive eect, while others showing a negative eect on
the reliability of the solder joint. This study was aimed at
isolating the eect of voids on the reliability of solder
joints.

2. Assembly
The assembly was focussed to study the issues related
to the assembly of chip scale packages (CSP). The factors involved in the assembly were solder paste type
(three levels), pad metallurgy (two levels), paste type
(two levels), and reow atmosphere (two levels). The test
board used in the experiment was a CSP test board
designed to study the assembly and reliability issues as a
part of the CSP consortium at Universal Instruments
Corporation. The test board was a 9.5  9.35 in., two up
panel, four layered board with tetrafunctional epoxy as
the base material. The pad nishes investigated were
organic solder protect (OSP) [Entek 106 A (Enthone
OMI)] and immersion gold over electroless nickel. A
total of seven dierent types of components were assembled. The component type included:

ex carrier devices with wirebond,

ex carrier with elastomeric interposers,
laminate carrier BGAs,
laminate carrier CSPs.

Three solder pastes were used in the assembly. Paste

A was a type III no clean paste, while paste B was a type
IV no clean paste and paste C was a type IV water
soluble paste. Paste A and paste B were commercially
available paste while paste C was an experimental paste.
The solder pastes are classied into the type depending
on the solder particle distribution in the solder paste.
Type III paste has larger diameter solder particles, while
type IV has ner diameter particle size, which is typically
used for solder paste printing in ne pitch application.
The solder paste are called water soluble or no clean
depending on the ux type used in the solder paste.
The assembly process involved stencil printing solder
paste followed by print inspection to measure the deposit volume. The components were placed with a pick
and place machine and the assemblies were reowed in a
forced convection reow oven. The boards assembled
with the water soluble solder paste were cleaned after
reow while the boards assembled with no clean solder
paste were inspected immediately after assembly.
The assembled boards were inspected for electrical
continuity and for the solder joint quality. On electrical
inspection, three opens were found and all these were
attributed to the same components on dierent boards.
On further analysis they were identied as component
related defect associated with the rst level interconnection. All the assemblies were inspected by X-ray inspection to check for any visible solder joint defects. The
most signicant observation from the inspection results
were the excessive amount of voiding observed in all
assemblies. Voids were observed in assemblies reowed
in air and nitrogen and for all the three pastes. However
the type of voids with each was dierent based on the

M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

size and the frequency. With paste A, small and medium

sized voids were observed with air and nitrogen atmosphere. Paste B also gave small to medium sized voids
(115% of the cross sectional area of the solder joint)
while with paste C, excessively large voids (1550% of
the cross sectional area of the solder joints) were observed with both air and nitrogen atmosphere. From
X-ray inspection as shown in Fig. 1, solder joints with
multiple small voids, medium sized voids and large voids
were observed. Fig. 2 shows a few cross sectional image
of solder joints with voids.
The solder joints were characterized based on the
voids in them to study the eect of voids on the reliability
of the solder joints. X-ray images of assemblies show the
presence of voids and all the assemblies were documented. These X-ray images were used as an input into
an image recognition software Optimas 5.1 which characterizes the lighter areas in the solder joints. The software uses the gray scale image and delineates the voided
area and measures the void diameter and the void area
percentage in the solder joint. These values were noted
for all the solder joints and were documented. The percentage of solder joints with voids and the void area
percentage data was analyzed to study the eect of different factors on the amount of voiding observed in the
assemblies. The analysis revealed that the solder paste
was the most signicant factor that inuenced the void
formation in this experiment, with paste C (experimental,

2079

water soluble), showing signicantly higher percentage

of solder joints with voids and the void area percentage in
a solder joint, which could be attributed to the fact that
water soluble pastes are more active paste and produce
more volatile by products during the soldering process.
The other factors (pad metallurgy and reow atmosphere) did not show a signicant eect on void formation. However, Cu OSP pad metallurgy showed a slightly
higher amount of void formation. This could be attributed to the higher oxidation tendency of Cu and thereby
reducing the solderability of the pads, which could produce more oxide-reduction by products during the soldering process.

3. Reliability evaluation
The main objective of this study was to study the effect of voids on the reliability of BGA/CSP solder joints.
Also the eect of void location, frequency, and the size of
the void on the reliability of solder joints was investigated. Reliability evaluation of voided solder joints was
conducted by torsion testing and air to air thermal cycling (AATC). The reasoning to perform two dierent
types of testing is because the performance of the solder
joint may depend upon the type of loading imposed depending on the application space of the device.

Fig. 1. X-ray images showing solder joints with no voids, small voids, multiple small voids and big voids.

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M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

Fig. 2. Time zero cross sections of solder joints with voids.

3.1. Torsion testing

Torsion testing is a test where cyclic out of plane
deformation (torsion) is imposed on assemblies with a
temperature usually slightly above the ambient temperature. As a result of this deformation on the assembly, a
portion of the applied deformation is transferred to the
assembled solder joints and repeated loading and unloading results in eventual failure [5]. This test can be
performed at ambient temperature and also at elevated
temperatures. The torsion test applies predominantly
tensile and compressive deformation to solder joints
helping to evaluate the mechanical robustness of the
solder joints. The resistance of these assemblies to failure
when subjected to handling defects like dropping,
twisting etc., can be evaluated by torsion testing. This
testing was performed at room temperature. The loading
parameters for the MDS testing of the components were
determined using the calculations in [6,7]. The angle of
twist applied would depend on the size of the coupon
and the size of the package on the coupon. The coupon
size and the package size for package G were 1.909 in.
and 17 mm square respectively and the dimensions for
package I were 1.4 in. and 8.15  6.25 mm respectively.
The components to be tested were clamped with a set
of clamping devices and inserted into the torsion xture.
The deection and the cycle frequency was controlled by

an air cylinder. Data acquisition and storage was done

using an event detector. An event was detected if the
resistance of the component surpasses 300 X for a
minimum duration of 200 nS. If one or more events are
recorded during a cycle, then the cycle is considered
open. A component is dened to have failed at cycle N if
it is open for 10 cycles within 10% of cycle N, beginning
at cycle N [8]. Torsion testing was performed for two
component types from the set of assembled components.
The components that were evaluated by this method
were a 48 I/O, 0.8 mm, ex CSP and 256 I/O, 1 mm
pitch, PBGA. Only these components were tested by this
method as these were assembled on a single panel of a
two up panel format. The rest of the assembled components were tested by a )40
C/125
C, 60 min AATC.
The failed assemblies were removed from the chamber
and cross sections were performed to study the failure
mode in the solder joints. The failure cycles were plotted
using a Weibull distribution and the N63 were determined for each case. The failures were separated based
on the void percentage in the solder joint. The packages
were characterized for the void size and frequency before
they were subjected to testing. Fig. 3 shows the Weibull
plot of failures with 48 I/O component during torsion
testing. The N63 (characteristic life dened as the time
for 63% of the packages under test to fail) for failure
with no voids, small voids, and big voids (void area
>50% of the solder joint area) are 1457, 1443 and 1278

M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

2081

Fig. 3. Weibull plot of failures on 48 I/O, 0.8 mm, ex CSP.

cycles respectively. This shows that there is no signicant

dierence in reliability between the solder joints with no
voids and small voids. However, the solder joints with
big voids fail considerably earlier than the solder joints
with small voids or no voids showing a 13% decline in
the expected life as compared to solder joints with no
voids. These observations point towards the trend that

as the void size increases, the probability of failure increases.

Similar Weibull plots were made for the failures with
the 256 I/O package and the failures were separated
based on the void size in the solder joints. Fig. 4 shows
the Weibull plot for the same. The characteristic life for
the failures with no voids and big voids are 1349 and 757

Fig. 4. Weibull plot of failures on 256 I/O, 1 mm, PBGA.

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M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

cycles respectively. This shows a signicant eect of big

voids on the reliability of solder joints, showing a 44%
decline in the life of solder joints. The failures were
analyzed to study the failure modes and the factors affecting the crack initiation and propagation. A detailed
analysis of the failure modes revealed the eect of void
size, location and frequency. It was observed that big
voids (voids area percentage >50%) signicantly reduced
the characteristic life of the solder joint and caused early
failures. Fig. 5 shows a few cross sectional images of
solder joint failures with big voids. The failures were
accelerated in a few cases when other issues such as
solder mask misregistration was also observed, which
typically causes an area of high stress concentration
associated with a sharp change in geometry. Another
observation with solder joint failures with big voids was
that a few failures were observed on the board side when
the voids were oriented towards the board side. This is
not a typical failure mode observed in BGA solder
joints, thereby hinting that big voids do aect the failure
mode in the solder joint. A key observation from the
failure analysis of solder joints with big voids was the
importance of the shell thickness which can be dened as
the distance from the soldervoid interface to the corner
of the solder joint. From numerous cross sections, it has
been observed that the shell thickness has an eect on
the probability of crack propagation and early failure.
This shell thickness is smaller, when there is a big void.

It has been observed that the probability of solder joint

failure is high when the shell thickness is smaller than
67 mil in a 2024 mil diameter solder joint.
Failure analysis also revealed the eect of location
and size of the solder joint. The Weibull plot comparison
of solder joints with small voids and no voids did not
show any signicant dierence in the characteristic life
time. However, with small voids, the frequency and the
location played a critical role. In the few cases where
small voids were observed on the board side, the voids
did not aect the failure mode, while the small voids
observed on the component side did show cracks
through the voids resulting in failure (Fig. 6). Solder
joint failure was also accelerated when multiple small
voids were present on the component side showing the
eect of frequency of voids on the reliability of solder
joint. Fig. 7 shows a few cross sectional images of solder
joint failure illustrating the eect of frequency of voids.
3.2. Thermal cycling
A total of 120 of the remaining assembled components were subjected to thermal cycle testing to study the
eect of voids on the thermalmechanical reliability of
solder joints. The testing cycle used was a 60 min cycle
()40
C/125
C) with a 15 min ramp and 15 min dwell.
The test procedure and the failure criteria was dened as
explained earlier. The failure cycles were noted and the

Fig. 5. Cross section of solder joint failures with big voids.

M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

2083

with voids showed a characteristic life of 2037 cycles,

thereby resulting in a 30% reduction in characteristic life
of the component. Fig. 10 shows a few cross sectional
images of solder joint failure as a result of the void during
thermal cycling. The early failure in these solder joints
has resulted due to the reduced cross sectional area of the
solder joint due to the presence of void in the crack
propagation pathway.
3.3. Finite element modeling

Fig. 6. Cross section of a solder joint failure with a small void

on the component side.

characteristic life was determined by Weibull plots and

the failure mode was analyzed by cross sectional analysis.
Two of the component types were elastomer CSPs
with ribbon bond as the rst level interconnection. These
components failed very early during cycling and upon
failure analysis, these were identied as ribbon bond
failure (rst level) in the component. This data could not
be used for studying the eect of voids on solder joint
reliability as the failure mode was predominantly rst
level. The laminate based 36 I/O, 0.8 mm pitch component showed the eect of voids on reliability from failure
analysis. Fig. 8 shows the Weibull plot comparison of
the failures. The components with voids showed a
characteristic life of 2300 cycles as compared to components with no voids which lasted for 2923 cycles. The
solder joints with voids showed a 21% reduction in
characteristic life.
The other component type analyzed was a 48 I/O, 0.5
mm pitch CABGA (chip array BGA). The failures were
separated based on the void percentage in the solder
joint. Fig. 9 shows the Weibull comparison of the characteristic life. The components with no voids showed a
characteristic life of 2938 cycles, while the components

To study the eect of voids and to correlate with

experimental data, a nite element model of a CSP with
a single big void was modeled and analyzed. A 48 I/O
ex based CSP was used for the analysis. As the corner
joints are usually the highly stressed joints, a void was
created in those joints. The voids were located at the top
of the joint. Quarter symmetry of the package was used,
and as a result, a void was present in all the four corner
joints. Three dierent void sizes were analyzed.
A 20-min 0100
C thermal cycle was used as loading
for the analysis. Due to some limitations of Darveauxs
model, the eect of the voids at dierent positions within
the joint was not analyzed.
The modeling assumptions and techniques adopted
are described as follows. Three-dimensional models of
the CSP were used. The models used twofold (i.e.,
quarter) symmetry. The solder was modeled with temperature and time dependent elasticplastic stressstrain
response (using rate-dependent visco-plasticity). The
fatigue life of each solder joint was computed using the
crack growth rate approach [6], and the package reliability was estimated using a two-parameter Weibull
failure distribution and an assumed Weibull slope of 4.0.
Three dierent void sizes used had a 5, 8 and 10 mil
diameter in a 18 mil diameter solder joint.
Fig. 11 shows the quarter symmetry model of the
package. The modeling results are shown in Table 1. The
results show that in a package with a 5 mil void, approximately 8% of the joint volume was ascribed to the

Fig. 7. Cross sectional images of failed solder joints showing the eect of frequency of voids.

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M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

Fig. 8. Weibull plot of failures of 36 I/O, 0.8 mm pitch laminate CSP.

Fig. 9. Weibull plot of failures for 48 I/O, 0.5 mm pitch, CABGA.

void. The life was computed to be 1503 cycles, a 3%

decline in the characteristic life as compared to a package
without voids. The package with a 8 mil diameter void

showed a 14% decrease in characteristic life (1341 cycles).

The package with the biggest void size (10 mil) showed a
16% decrease in characteristic life (1301 cycles).

M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

Fig. 10. Cross section of a solder joint failure in 36 I/O package

with the crack going through the void.

Fig. 11. Quarter symmetry model of the package.

Table 1
Summary of FEM results
Void size
(mil)

Ratio of void
volume to joint
volume (%)

Package life
N (50%)

Decrease in life
N (50%) as
compared to
package with
no void

0
5
8
10

0
8
20
31

1553
1503
1341
1301

0
3
14
16

4. Conclusion
The eect of voids on the mechanical robustness and
thermalmechanical reliability of solder joint was determined. Some of the prominent inferences from the
study are:
Voids which are greater than 50% of the solder joint
area cause potential reliability problem causing a 25
50% reduction in solder joint life in mechanical testing.
The distance from the voidsolder interface to the
corner of the solder joint (shell thickness) is of critical

2085

importance. From the numerous cross sections and

analysis performed, it is understood that if the distance is lesser than 67 mil, there is a higher probability of crack propagation and subsequent failure when
subjected to handling stresses.
Other factors, such as solder mask misregistration
and other stress concentration points, coupled with
the occurrence of voids may accelerate the failure
of solder joints.
Although there was no statistical signicance of the effect of small voids on the mechanical robustness of solder joint, in reality they aect the solder joint life, when
multiple small voids line up on the component side.
The frequency and location of the voids in the solder
joint have an eect on the reliability. For example,
multiple small voids lined up on the component side
dramatically reduce the life of the solder joint as the
crack links up through the void causing a failure.
Other small voids on the board side have not shown
to aect the mechanical robustness of a solder joint.
Voids have also shown a reduction in solder joint life
in thermal cycle testing.
The location of voids with respect to the area of
crack propagation is signicant. If the voids are on
the component side of the solder joint, which is typical location of crack in a BGA/CSP solder joint, the
voids may accelerate the failure as a result of reduced
distance that the crack has to propagate. At the same
time there is also a possibility of the void arresting
the crack and extending the life of the solder joint
as it may take longer time for another crack to initiate and propagate. But typically, cracks propagate
inwards from all directions simultaneously.
The eect of voids on the reliability of solder joint in
thermal cycling may be dierent from handling and
torsion testing. However in both forms of test, presence of voids have shown a decrease in the characteristic life of solder joint. There was a 30% reduction in
characteristic life of solder joints with big voids in thermal cycling and a 44% decline in the characteristic life
of solder joints with big voids in mechanical testing.
The eect of voids on mechanical robustness of solder joint was more pronounced as compared to thermal cycle testing. This may translate to strict void
inspection criteria for handheld and portable electronic products, which are subjected to severe handling stresses during normal eld life. However, it
should be mentioned that these are two dierent
loading mechanisms and the actual loading in products may depend on the application.
Another important concern is the impact of small
voids on the reliability of the solder joint. These small
voids may not be visible under X-ray inspection.
FEM performed to correlate experimental data also
showed voids reduce the fatigue life of solder joints.
The reduction in fatigue life was proportional to the

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M. Yunus et al. / Microelectronics Reliability 43 (2003) 20772086

void dimensions. In reality, there may not be a direct

correlation, but the modeling data shows that voids
are concerns due to local stress concentration regions.
From the testing conducted, voids have shown to
have an impact on the reliability of solder joint. The
exact nature of eect of voids on the failure mode depends on the location, size and the frequency. Further
designed studies have been planned to study in determine the critical void size and location that accelerates
the solder joint failure. This will be achieved by creating
voids in solder joints by having varying areas of the pad
being exposed laminate. This has shown to produce
voids of varying sizes in the solder joint.

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