ALU DESIGN

Bit-slice technique was used to design a 16-bit ALU with three selection inputs S2, S1, S0 that implement eight
functions of the two data inputs A and B (and carry-in C0). We choose our ALUs functions from the following:
F = XOR
F = OR
F = AND
F = NOR
F = Increment A
F = Increment B
F = A minus B minus 1
F = A plus B

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

A
A
A
A
A
A
0
A
A

B
B
B
B
B
0
B
B
B

F
XOR
OR
AND
NOR
Increment A
Increment B
A minus B minus 1
A plus B

Cin
X
X
X
X
1
1
0
0

Simulation from Quartus II Altera

1-bit slice body diagram
XOR

inst9
INPUT
VCC
INPUT
VCC

S1
S0

OR2

MUX41
INH
D0

inst8

D1
D2

AND2

D3
INPUT
VCC

S2

S1
S0

inst7

21mux

inst3

A
B
S

NOR2

inst10

inst4

OUTPUT

MULTIPLEXER

MUX41

INPUT
VCC

INH
D0
D1
D2

D3
XOR

S1

XOR

S0

inst

inst1

inst13

MUX41

INPUT
VCC

AND2

INH
D0
NOT

OUTPUT

D1
D2

inst6

OUTPUT

inst14
Q

D3
S1

Cin

S0

INPUT
VCC

inst2

GND

At 2 to 1 MUX for above design, when selector S2 = 0, it will select B and the function will choose logic gate function.

1-bit slice in symbol

baru
S1
S0
S2
A
B
Cin
inst

F
G
P

Carry Lookahead (CLA)

Carry Lookahead Logic Derivation

Carry Generate Gi = Ai Bi
Carry Propagate Pi = Ai XOR Bi
Sum and Carry can be reexpressed in terms of generate/propagate:

Si = Ai XOR Bi XOR Ci = Pi XOR Ci

Ci+1 = Ai Bi + Ai Ci + Bi Ci
= Ai Bi + (Ai + Bi) Ci
= Ai Bi + (Ai XOR Bi) Ci
= Gi + Pi Ci
Reexpress

C1 = G0 + P0 C0
C2 = G1 + P1 C1
= G1+ P1G0+ P1 P0 C0
C3 = G2 + P2 C2
= G2+ P2 G1+ P2 P1 G0 + P2 P1P0 C0
C4 = G3 + P3 C3
= G3 + P3 G2+ P3 P2 G1+ P3 P2 P1G0 + P3 P2 P1P0 C0

Simulation from Quartus II Altera

Carry Lookahead in Symbol
CLA
G0
C0
P0
G1
P1
G2
P2
G3
P3
inst

C1
C2
C3
G
P

G0

P0

G1

P1

G2

P2

G3

P3

C0

VCC
INPUT

VCC
INPUT

VCC
INPUT

VCC
INPUT

VCC
INPUT

VCC
INPUT

VCC
INPUT

VCC
INPUT

VCC
INPUT

Carry Lookahead body diagram

OR2
OUTPUT

C1

OUTPUT

C2

OUTPUT

C3

AND2

inst20
inst19

AND2

OR3

inst21

inst23

AND3

inst24

AND2
OR4

inst22

AND3

inst27

inst26

AND4

inst25

AND2

inst

AND3
OR4

inst1
OUTPUT
AND4

inst3

inst2

AND4

OUTPUT

inst4

4-bit slice was produced from connection between 1 bit slice and carry lookahead (CLA)
4-bit slice body diagram
Cin

INPUT
VCC

OUTPUT

F0

OUTPUT

F1

baru

A0
B0

INPUT
VCC
INPUT
VCC

S1
S0
S2
A
B
Cin

F
G
P

inst

baru

A1
B1

INPUT
VCC
INPUT
VCC

S1
S0
S2
A
B
Cin

F
G
P

CLA
G0
C0
P0
G1
P1
G2
P2
G3
P3

inst1

S0

INPUT
VCC

S1

INPUT
VCC

S2

INPUT
VCC
INPUT
VCC
INPUT
VCC

baru

A2
B2

S1
S0
S2
A
B
Cin

C1
C2
C3
G
P

OUTPUT

OUTPUT

OUTPUT

F2

OUTPUT

F3

inst4

F
G
P

inst2

baru

A3
B3

INPUT
VCC
INPUT
VCC

S1
S0
S2
A
B
Cin

F
G
P

inst3

4-bit slice in symbol

4bit
Cin
A0
B0
A1
B1
S0
S1
S2
A2
B2
A3
B3
inst

F0
F1
G
P
F2
F3

16-bit body diagram

NOT

inst22

4bit

A0

B0
A1

B1
S0

S1
S2

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

INPUT
VCC
INPUT
VCC
INPUT
VCC

A2
B2
A3

B3

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

Cin
A0
B0
A1
B1
S0
S1
S2
A2
B2
A3
B3

F0
F1
G
P
F2
F3

OUTPUT

F0

OUTPUT

F1

OUTPUT

F2

OUTPUT

F3

F0
F1
G
P
F2
F3

OUTPUT

F4

OUTPUT

F5

OUTPUT

F6

OUTPUT

F7

inst5

4bit

A4

B4
A5

B5

A6

B6
A7

B7

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

Cin
A0
B0
A1
B1
S0
S1
S2
A2
B2
A3
B3

CLA
G0
C0
P0
G1
P1
G2
P2
G3
P3

inst6

4bit

A8

B8
A9
B9

A10

B10
A11

B11

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

Cin
A0
B0
A1
B1
S0
S1
S2
A2
B2
A3
B3

inst

F0
F1
G
P
F2
F3

OUTPUT

F8

OUTPUT

F9

OUTPUT

F10

OUTPUT

F11

F0
F1
G
P
F2
F3

OUTPUT

F12

OUTPUT

F13

OUTPUT

F14

OUTPUT

F15

inst7

4bit

A12
B12
A13
B13

A14

B14
A15

B15

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC

Cin
A0
B0
A1
B1
S0
S1
S2
A2
B2
A3
B3
inst8

C1
C2
C3
G
P

From waveform :
We insert the random input value for A and B to check whether the output is same or not with the function.
This is our observation. For selector S2, S1 and S0 we group as S. For input A15 until A0 we group them as A, input B15 until
B0 we group as B. While, for output F15 until F0 we group them as F.
For arithmetic function, we have to read it in 2s complement and change to decimal to recheck the output.

When our selector S = 000, the function will follow X-OR gate.
Input A = 0110 0010 1001 0011
XOR

Input B = 1010 1111 0011 1011

inst

Output F = 1100 1101 1010 1000

When our selector S = 001, the function will follow OR gate.

Input A = 0110 0001 0010 1010
OR2

Input B = 0100 1111 0010 1001

inst

Output F = 0110 1111 0010 1011

When our selector S = 010, the function will follow AND gate.
Input A = 0110 0010 1011 1000

AND2

Input B = 1000 1111 0001 0101

inst

Output F = 0000 0010 0001 0000

When our selector 011, the function will follow NOR gate.
Input A = 1110 1110 1010 0011
NOR2

Input B = 0001 1011 1011 1011

inst

Output F = 0000 0000 0100 0100

When our selector 100, the output will follow function F = increment A
Input A = 1110 1110 1011 0000
Input B = 1101 0101 0001 1110
Output F = 1110 1110 1011 0001

For this arithmetic function, we convert input A to 2s compliment and B always 0.

Input A = -4432
Hence, output F = -4432 + 1 = -4431

=> 1110 1110 1011 0001

When our selector S = 101, the output will follow function F = increment B
Input A = 0100 0111 1001 1100
Input B = 0100 1100 1100 0110
Output F = 0100 1100 1100 0111
For this arithmetic function, A always 0.
Input B = +19654
Hence, output F = 19654 + 1 = 19655

=> 0100 1100 1100 0111

When output selector S = 110, the output will follow function F = A minus B minus 1
Input A = 1100 0110 0010 1001
Input B = 0001 0110 1111 1010
Output F = 1010 1111 0010 1110
For this arithmetic function, we convert input A output F to 2s compliment.
Input A = -14807
Input B = 5882
Hence, output F = -14807 5882 1 = -20690

=> 1010 1111 0010 1110

When our selector S = 111, the output will follow function F = A plus B
Input A = 0010 1101 1000 1111
Input B = 1110 1011 0011 1010
Output F = 0001 1000 1100 1001
For this arithmetic function, we convert input B to 2s compliment.
Input A = 11663
Input B = -5318
Hence, output F = 11663 + (-5318) = 6345

=> 0001 1000 1100 1001

Discussion and conclusion:

Our 16-bit ALU design was succeed. From the above observation we got the same value as the function that we
select. To design 16-bit ALU, we started with 1 bit slice that contain logic gate, 4 to 1 MUX, 2 to 1 MUX and adder. After
that, we combine four 1-bit slice with CLA to design 4-bit slice. Lastly, we combine four 4-bit slice with CLA to design
our 16-bit ALU.
After we done it, we already understand the function of ALU and CLA. In addition, we can differentiate the logic
gate and arithmetic function.