Glossary

A
Accept operation. Operation on a mailbox that is similar to the pend operation, except
that if no clataare available, the task retums immediately from the call with a condition
code rather than susPending.
Access time. The interval between when data are requestedfrom the memory cell and
when they are actually available.
Accumulator. An anonymous register used in certain computer instructions.
Activity packet. A special token passed between the processors in a dataflow
architecture. Each token contains an opcode, operand count, operands,and a list of
destination addressesfor the result of the computation.
Actual parameter. The named variable passedto a procedure or subroutine.
Address bus. The collection of wires neededto accessindividual memory addresses'
Alpha testing. A type ofvalidation consisting ofinternal distribution and exerciseofthe
software.
ALU. See arithmetic logic unit'
Anatog-to-digital conversion. The processof convertingcontinuous(analog; signals
into discrete (digital) ones.
Anonymous variable. A hidden variable createdby the compiler to facilitate call-by-
value parameterpassing.
Application programs" Programs users write to solve specific problems.
Arithmetic logic unit. The CPU intemal device that performs arithmetic and logical
operations.
Assemblers. Software that translatesassemblylanguage to machine code.
Assembly language. The set of symbolic equivalents to the macroinstruction set.

327
328 I Glossary

Associative memory. Memory organizedso that it can be searchedaccordingto its

contents.
Asynchronous event. An event that is not synchronous.
Atomic instruction. An instructionthat cannotbe intenupted.

B
Background. Non-interruptdriven processesin foreground/background systems.
BAM. See binary angularmeasurement.
Banker's algorithm. A techniquesometimesused to preventdeadlocksituations.
Bathtub curve. A graphdescribingthe phenomenonthat in hardwarecomponentsmost
errorsoccur either very early or very late in the life of the component.Some believe
that it is applicableto software.
Belady's Anomaly. The observationthat in the FIFO pagereplacementrule, increasing
the number of pagesin memory may not reducethe number of page faults.
Beta testing. A type of systemtestwherepreliminaryversionsof validatedsoftwareare
distributedto friendly customerswho test the softwareunder actual use.
Binary angular measurement. An n-bit scalednumber where the least significantbit
is 2"-' .180.
Binary semaphore. A semaphorethat can take on one of two values.
Binary tree. A collectionof n nodes,one of which is a specialone calledthe root. The
remaining n - 1 nodesform at most two subtrees.
Black box testing. A testingmethodologywhereonly the inputs and outputsof the unit
are considered.How the outputsare generatedinside the unit is ignored.
Blocked. The condition experiencedby tasksthat are waiting for the occurrenceof an
event.
Broadcast communication. In statecharts,a techniquethat allows for transitionsto
occur in more than one orthogonalsystemsimultaneously.
Buffer. A temporary data storage area used to interface between, for example, a fa^st
device and a slower processservicingthat device.
Burn-in testing. Testingthat seeksto flush out thosefailuresthat appearearly in the life
of the part and thus improve the reliability of the delivered product.
Burst period. The time over which data are being passedinto a buffer.
Bus arbitration. The processof ensuringthat only one device at a time can place data
on the bus.
Bus contention. Condition in which two or more devicesattemptto gain control of the
- --
main memory bus simultaneously.
Bus cycle. Memory fetch.
Bus grant. A signal provided by the DMA controller to a device indicating that it has
exclusiverights to the bus.
Bus time-out. A condition whereby a device making a DMA requestdoes not receive
a bus grant before some specifiedtime.
Busy wait. In polled loop systems,the processof testing the flag without success.
I Glossary
329

C
Call-by-address. See call-by-reference.
Call-by-reference. The processin which the addressof the parameteris passedby the
calling routine to the called procedureso that it can be alteredthere.
Call-by-value. Parameterpassingmethodin which the value of the actualparamererin
the subroutineor function call is copied into the procedure'sformal parameter.
Calling trees. See structurechart.
CASE. Computer-adedsoftwareengineering.
Catastrophic error. An error that rendersthe svstemuseless.
CCR See condition code register.
Cellular automata. A computationalparadigm for an efficient descriptionof SIMD
massivelyparallel systems.
Chain reaction. In statecharts,a group of sequentialevents where the nth event is
triggeredby the (n - l)th event.
'Code
Checkpoints. that outputs intermediateresults to allow an external Drocessto
monitor the efficacy of the processin questron-
Checksum. A simple binary addition of all program code memory locationsused ro
verify the contents.
Circular queu€. See ring buffer.
CISC. Seecomplexinstructionset computer.
Class definitions. Object declarationsalong with the methodsassociatedwith thern.
Clear box testing. See white box testing.
Code inspection. See group walkthrough.
Collision. Condition in which a device already has control of the bus and another
obtainsaccess.Also, simultaneoususe of a critical resource.
C-ompaction. The processof compressingfragmentedmemory so that it is no lon-eer
fragmented.Also called coalescing.
Compiler. Softwarerhat translareshigh-orderlanguageprogramsinto assembll,code
Complex instruction set computers. Architecturescharacterizedbv a larse. micrr.-
coded instruetionset with numerousaddressingmodes.
Composition. An operationappliedto a reliability matrix that determinesthe marin-iuir
reliability betweenprocessors.
Compute-bound. Computationsin which the number of operationsis laree in ;,r:---
parisonto the number of I/O instructions.
Condition code register. Intemal CPU register used to implemenr a .Lrr.,i::1.-:.;.
transfer.
Conditional transfer. A changeof the program counterbasedon the resuk .ri : !3>:
Content.addressablememory. See associatrvememory.
context. The minimum informationthat is neededin order to sa'e a curienrlr .\e.-urrns
task so that it can be resumed.
Context switching. The processof saving and restorine suft-rcientinformation for a
real-time task so that it can be resumedafter beins intem-rpred.
330 I Glossary

Continguous firleallocation. The processof forcing all allocatedfile sectorsto follow

one anotheron the disk.
iontinuous random variable. A random variablewith a continuoussamplespace.
Control flow diagram. A real-timeextensionto dataflowdiagramsthat showsthe flow
of control signalsthrough the system.
Control specifications. In dataflow diagrams,a finite state automatonin diagrammatic
and tabularrepresentation.
Control unit. CPU internal device that synchronizesthe fetch-executecycle.
Cooperative multitasking system. A scheme in which two or more processesare
divided into statesor phases,determinedby a finite stateautomaton.Calls to a central
dispatcher are made after each phase is complete.
Coprocessor. A secondspecializedCPU used to extendthe macroinstructionset.
Coroutine system. See cooperativemultitaskingsystem.
Correlated data. See time-relativedata.
Counting semaphore. A semaphorethat can take on two or more values.
CPU. Centralprocessingunit.
CRC. See cyclic redundancYcode.
Critical region. Code that interactswith a serially reusableresource.
CU. See control unit.
Cycle stealing. A situationin which DMA accessprecludesthe CPU from accessingthe
bus.
Cyclic redundancy code. A method for checking ROM memory that is superior to
checksum.See Chapter 11.
Cycling. The processwhereby all tasks are being appropriately scheduled(although no
actualprocessingis occurring).
cyciomatic complexity. A measureof a system reliability devised by McCabe.

D
Daemon. A device serverthat doesnot run explicitly but rather lies dormant waiting for
some condition(s) to occur.
Dangerous allocation. Any memory allocation that can preplude system determi-
nrsm.
Data bus. Bus used to carry data between the various componentsin the system.
Dataflow architectures. A multiprocessing system that uses a large number of speciai
processors,and computation is performed by passing activiti packs between them.
Dataflow diagrams. A structured analysis tool for modeling software systems.
Dead code. See unreachablecode.
Deadlock. A catastrophicsituation that can arise when tasksare cornpetingfor the sarne
set of two or more serially reusableresources.
Deadly embrace. See deadlock.
Death spiral. Stack overflow causedby repeatedspurious interrupts.
Decode. The processof isolating the opcodeTieldof a macroinstructionand determin-:ne
the addressin micromemory of the programming correspondingto it'
I Glossary 33r

Defect. The preferred term for an error in requirement,design, or code. See also fault,
failure.
Demand page system. Techniquewhere program segmentsare permittedto be loaded
in noncontiguousmemory as they are requestedin fixed-sizechunks.
Density. In computermemory, the number of bits per unit area.
De-referencing. The processin which the actual locationsof the parametersthat are
passedusing call-by-valueare determined'
Derivative of f at x. Representsthe slope of the function/ at point x.
Deterministic system. A systemwhere for each possiblestate.and each Setof inputs,
a unique set of outputsand next stateof the systemcan be determined.
Digital-to-analog conversion. The processof convertingdiscrete(digital) signalsinto
continuous(analog)ones.
Direct memory access. A scheme in which accessto the computer's memory is
affordedto other devicesin the systemwithout the intervcntionof the CPU'
Direct mode instruction. Instructionin which the operandis the data containedat the
addressspecifiedin the addressfield of the instruction.
Discrete random variable. A random variabledrawn from a discretesamplespace.
Discrete signals. Logic lines used to control devices.
Dispatcher. The part of the kernel that performs the necessarybookkeeping to start 3
task.
Distributed real.time systems. A collection of interconnectedself-containedpro-
cessofs.
DMA. See direct memory access.
DMA controller. Device that performsbus arbitration.
Dormant state. ln the task-controlblock model, a statethat is best describedas a TCB
belonging to a task that is unavailableto the operatingsystem.
Double-buffering. A techniqueusing two buffers where one is tllled while the data ir
the other is being used.
DRAM. Dynamic random accessmemory.
Drive line. In core memory,a wire usedto induce a magneticfield in a toroid-shrpe;
magnet. The orientation of the field representseither a 1 or a 0'
Dynamic memory. Memory that usesa capacitorto storelogic 1s and 0s. and thet ::-.:
be refreshedperiodicallyto restorethe chargelost due to capacitivedischarse
Dynamic priority system. A system in which the priorities of tasks ca: ;:i:::
Contrast with fixed priority system'

E
Effort. One of Halstead'smetrics (seeChapter 11)'
---e
Embedded system. Software used to conffol speci.alizedharClare .l';;:.:: ::
computer system.
I --: '-i:l
EncapSulation. A condition that ariseswhen a classof objecis;n.j ilre rrFEri'.-
can be performedon are isolatedin both accessand implementation'
332 I Glossary

Event. Any occurrencethat resultsin a changein the stateof a system.

Event determinism. When the next statesand outputsof the systemare known for each
set of inputs that trigger events.
Event flag. Synchronizationmechanismprovided by certain languages.
Exception. Error or other specialcondition that arisesduring program execution.
Exception handler. Code used to processexceptlons.
Execute. Processof sequencingthrougli the stepsin micromemorycorrespondingto a
particularmacroinstruction.
Executing state. In the task-controlblock model, a task that is currently running.
Exccutive. See kernel.
Extennal fragmentation. When main memory becomescheckeredwith unused but
availablepartitions,as in Figure 8.-5.

F
Failed system. A systemthai cannotsatisfyone or more of the requirementslistedin the
formal systemspecification.
Failure. A fault that causesthe softwaresystemto fail to meet one of its requirements.
See also defect.
A function describingthe probability that a systemfails at time r.
Failure function.
Fault. The appearanceof a defect during the operation of a software system;
synonymouswith error or bug. See also failure.
Fault tolerance. The ability of the systemto continue to function in the presenceof
hardwareor softwarefailures.
Fetch. The processof retrieving a macroinstructionfrom main memory and placing it
in the instructionregister.
Fetch-executecycle. The processof continuouslyfetchingand executingmacroinstruc-
tions from main memory.
File fragmentation. Analogous to memory fragmentationbut occurring within files,
with the sameassociatedproblems.
Finite state automaton. A mathematicaltechniqueusedto representsystemswith finite
input and output spaces.Also known as a finite statemachine.
Firing. In Petri netsor in certainmultiprocessorarchitectures,when a processblock or
processperformsits prescribedfunction.
Firm real-time system. A systemwith hard deadlineswhere some low of
missing a deadlinecan be tolerated.
Fixed priority system. A system in which the task priorities cannot be changed.
Contrast with dynamic priority system.
Fixed-rate system. A systemin which intemrptsoccui only at fixed rates.
Flip-flop. A bistablelogic device.
Flow chart. Graphical algorithm representation.
Flush. In pipelined architectures, the act of emptying the pipeline when branching
occurs.
I Glossary 333

Foreground. A collectionof interrupt driven or real-timeprocesses.

Formal parameter. The dummy variable used in the description of a procedure or
subroutine.
FSA. Seefinite stateautomaton.
FSM. See finite state automaton.
Function points. A widely used metric set in nonembeddedenvironments; they form
the basis of many commercial software analysispackages.Function points measurethe
number of interfacesbetweenmodulesand subsystemsin programsor systems.
Functional requirements. Those system features that can be directly tested br
executing the program.

G
Garbage. Memory that hasbeenallocatedbut is no longerbeing usedby a task (that is.
the task has "lost track of it").
General register. CPU intemal memory that is addressablein the address field of
certainmacroinstructtons.
General semaphore. See counting semaphore.
General polynomial. The modulo-2 divisor of the messagepolynomial in CRC.
Granularity. See scale factor.
Group walkthrough. A kind of white box testingin which a numberof personsinspect
the code line-by-line with the unit author.

H 1
-Hamming code. A coding technique used to detect and correct errors in computer
memory.
Hard error. Physical damageto memory cell.
Hard real-time system. Systemswherefailure to meet responsetime constraintsleads
to system failure.
Hybrid system. A system in which interrupts occur both at fixed frequencies and
sporadically.
Hypercube processor. A processor configuration that is similar to the linear arrar'
processorexcept that each processorelement communicatesdata along a number of
other higher dimensional pathways.

I
ICE. See in-circuit emulation.
Immediate mode instruction. An instructionin which the operandis an intege:
Implied mode instruction. An instruction involving one or more specitk nnern\a{
locations or registers that are implicitly defined in the operation pert-urrri trt
instruction.
Incidence matrix. A realiability matrix in which the enries are eitlrer I or 0.
334 I Glossary

In-circuit emulation. A devicethat usesspecialhardwarein conjunctionwith software

to emulatethe targetCPU for debuggingpurposes.
Indirect mode instruction. Instructionwhere the operandfield is a memory location
containing the addressof the addressof the operand.
Induction variable. A variablein a loop that is incrementedor decrementedby some
constant.
Information hiding. The processof isolating highly changeablesectionsof code.
Inheritance. In object-oriented programming, inheritance allows the programmer to
define new objects in terms of other objects that inherit their characteristics.
In-line patch. A patch that fits into the memory spaceallocatedto the code to be
changed.
Input space. The set of all possibleinput combinationsto a system.
Instruction register. CPU intemal register that holds the instruction pointed to by the
contents of the program counter.
Integration. The processof uniting modules from different sourcesto form the overall
system.
Internal fragmentation. Condition that occurs in fixed-partition schemeswhen, for
example, a processrequires I kilobyte of memory, while the only 2-kilobyte partitions
are available.
Interrupt. A hardware signal that initiates an event.
Interrupt handler. Specialcode usedto respondto intemrpts.Also called an interrupt
service routine.
Interrupt-handler location. Memory location containing the starting address of an
interrupt-handlerroutine. The program counter is automatically loaded with its address
when an interrupt occurs.
Interrupt latency. The delay between when an intemrpt occurs and when the CPU
begins reacting to it.
Interrupt register. Register containing a bit map of all pending (latched) interrupts.
Interrupt return location. Memory location where the contentsof the program counter
is saved when an intemrpt is processedby the CPU.
Interrupt vector. Register that contains the identity of the highest-priority intemrpt
request.
Intrinsic function. A macro where the actual function call is replaced by in-line
code.

J
Jackson Chart. A form of structure chart that provides for conditional branchins.

K
Kalrnan filter. A mathematical construct used to combine measurementsof the same
quantity from different sources.
Kernel. The smallestportion of the operating system that provides for task scheduling,
dispatching, and intertask communication.
 335
I Glossary

that providespreemptlonpolnts
Kernel preemption. A methodusedin real-timeUNIX
in cails to kemel functionsto allow them to be intemrpted'
usedto protect a critical region'
Key. In a mailbox, the data that are passedas a flag

L
Leaf. Any node in a tree with no subtrees'
pagereplacementalgorithm'
Least recently used rule. The best nonpredictive
a diagramat a finer level of
Leveling. [n dataflow diagrams.the processof redrawing
detail.
multiple instructionsof the same
Linear array processor. A processororganizedso that
type can be executedin Parallel'
Linker.Softwarethatpreparesrelocatableobjectcodeforexecutton'
averagenumberof customersin
Little,s law. Rule trom queuingtheory statingthat the
aqueuingSystem,N"',isequaltotheaverageanivalrateofthecustomerstoth
ta"'
system,ru,, times the averagetime spentin that system'
in the program'
Live variable. A variablethat can be used subsequently
Livelock. Another term for process starvatron'
the machine'
Load module. Code that can be readily loaded into
if you examine a list of recently executed
Locality-of-ret'erence. The notion that
you will see that most of the instructions are
progiu* instructions on a logic analyzer,
iocalized to within a small number of instructtons'
ineffective'
Lock-up. When a systementersin which it is rendered
Look-uptable.Anintegerarithmetictechniquethatusestablesandrelieson
functions quickly'
mathematicaldefinition of the derivative to compute
computationsoutsidea loop that
Loop invariant optimization. The processof placing
do not need to be performed within the loop'
Looselycoupledsystem.Asystemthatcanrunonotherhardwarewiththerewri
certainmodul:s
LRU. See leastrecentyusedrule'

M
computer operations'Also called
Machine code. Binary instructions that affect specific
machine language.
Macrocode. See macroinstruction'
Macroinstruction. Binary program code stored in the main memory of the computer'
Also called macrocode.
'i
of a memory locatlon in'J Ar-
Mailbox, An intertask communication device consi,sting
it'
operations-post and pend-that can be performed on
by the CPU'
Main memory. Memory that is directly addressable
of repeating processes in c1'ciicor pencrltc i\ ilsl'l'ls
Major cycle. The largestsequence
MAR. See memory addressregister'
enabling or di'abling sFecric
Mask register. A register that contains a bit map either
intemrPts.
 I Glossary
336

Master processor. The on-line processorin a master/slaveconfiguration'

MDR. SeememorYdata register.
of the memory
Memory address register (or MAR). Registerthat holds the address
location to be acted on.
written to or that
Memory data register (or MDR). Registerthat holds the data to be
is read fiom the memory location held in the MAR'

Memory-loading. The percentageof usablememory that is being used'

parts of a
Memory locking. In a real-timesystem,the processof locking all or certain
involved in paging, and thus make the
processlnro memory to reducefhe <lverhead
executiontimes more predictable.
array processor
Mesh processor. A processorconfigurationthat is similar to the linear
that eachprocessor element also communicatesdata north and south'
"^a"pt
Messageexchange' See mailbox.
Messagepolynomial. Used in CRC (seeChapter 11)'
on objects.
Methods. In object-orientedsystems,functionsthat can be performed
MFT. Multiprogrammingwith a fixed number of tasks'
particular macro-
Microcode. A sequenceof binary instructionscorrespondingto a
instruction.Also called microinstructions'
Microcontroller. A computersystemthat is programmablevia microcode.
Microinstructions. See microcode.
Micro-kerne|.Anano-kemelthatalsoprovidesfortaskscheduling.
correspondingto
Micromemory. cPU intemal memory that holds the binary codes
macroinstructions.
Microprogram. Sequenceof microcodestoredin micromemory'
Minor cycle. A sequenceof repeatingprocessesin cyclic or periodic systems'
with the
Mixed listing. A printout that combinesthe high-orderlanguageinstruction
equivalentassemblylanguage code'
frequencies and
Mixed system. A system in which interrupts occur both at fixed
sporadically"
with high-
Multimedia computing. Computing that involves computer systems
resolution graphics, CD-ROM drives, mice, high-performancesound cards, and
multitasking operating systemsthat support these devices'
Multip|exer.Adeviceusedtoroutemultiplelinesontofewerlines.
than one
Multiprocessing operating system. An operating system in which more
to provide for simultaneity; contrast with multitasking operating
processoris available
sysrcm.
function-
Multitasking operating system. An operating systemthat provides sufficient
single processor so that the illusion of
ality to aiow multiple programs to run on a
simultaneity is created; contrast with multiprocessing operating system.
Mutex. A common name for a semaphorevariable'
MUX. See multiPlexer'
MVT. Muftiprogramming with a variable number of tasks'
I Glossary 337

N
Nano-kernel. Code that provides simple thread-of-execution(same as "flow-of-
control") management;essentiallyprovides only one of the three servicesprovided by
a kernel-that is, it providesfor task dispatching.
Nonfunctional requirements. System requirementsthat cannot be tested easily by
program executron.
Nonvolatile menory. Memory whose contentsare preservedupon removing povl'er.
Non-von Neumann architecture. An architecturethat doesnot use the storedprogram,
serial fetch-executecycle.
No-op. A macroinstruction that does not changethe state of the computer.
NP-complete problem, A decisionproblem that is a seeminglyintractableproblem for
which the only known solutions are exponentialfunctions of the problem size; compare
with NP-hard.
NP-hard. A decision problem that is similar to an NP-completeproblem (exceptthat for
the NP-hard problem not even an exponential time solution can be found).
nth Order reliability matrix. The composition of a reliability matrix with itself (n - l)
trmes.
N-version programming. A techniqueusedto reducethe likelihood of systemlock-up
by using redundantprocessors,each running software that has been coded to the same
specificationsby different teams.
Nucleus. See kernel.

o
Object code. A specific collection of machine instructions.
Object-oriented language. A languagethat provides constructsthat encouragea high
degree of information hiding and data abstraction.
Opcode. Starting addressof the microcode program stored in micromemory.
Operating system. A unique collection of systemsprograms.
Organic system. A system that is not embedded.
Orthogonal process. In statecharts,the combined functionalit.v of t set of orrhogonal
processes.
Orthogonal product. In statecharts. a processthat depictsconcrurentprocesses that r'Jn
in isolation.
Ostrich algorithm. A techniquethat advisesthat the problem of deadlockbe ignored.
This solution is viable only in noncritical s\stems.
Output space. The set of all possibleoutput combilations ior a s)'stem'
Overlay. Dependentcode and data sections used in overlaf i,ng.
Overlaying. A technique that allows a srngle program to be larger than the allowable
user space.
Oversized patch. A patch that requires more memor)- than is curendy occupied by the
code to be replaced.
338 I Glossary

P
Page. Fixed-sizechunk used in demand-pagedsystems.
Page fault. An exceptionthat occurs when a memory referenceis made to a location
within a page not loaded in marn memory.
Page-frame. Seepage.
Page stealing. When a page is to be loaded into main memory, and no free pagesare
found, then a page frame must be written out or swappedto disk to make room.
Page table. A collectionof pointersto pagesusedto allow noncontiguousallocationof
page frames in demandpaging.
Parnas partitioning. See information hiding.
Partial order relation. In processscheduling,an indicator that any processcan call
itself (reflexivity); if processA calls process B, then the reverse is not possible
(antisymmetry),and if processA calls processB and processB calls processC, then
processA can call processC (transitivity).
Patching. The processof correctingerrors in the code directly on the targetmachine.
PC. See program counter.
PDL. See program design language.
Peepholeoptimization. An optimizationtechniquewhere a small window of assembly
langageor machinecode is comparedagainstknown pattemsthat yield optimization
opportunltles.
Pend operation. Operationof removing datafrom a mailbox. If data are not available,
the processperforming the pend suspectsitself until the data becomeavailable.
Petri net. A mathematical/pictorialsystemdescriptiontechnique.
Phase-driven code. See state-drivencode.
Ping-pongbuffering. Seedouble-buffering.
Pipeline. An intertaskcommunicationmechanismprovided in UNIX.
Pipelining. A techniqueused to speedprocessorexecutionthat relies on the fact that
fetching the instruction is only one part of the fetch-execute cycle, and that it can
overlap with different parts of the fetch-executecycle for other instructions.
Polled loop system. A real-timesystemin which a single and repetitivetest instruction
is used to test a flag that indicates that some event has occurred.
Polymorphism. In object-oriented programming, polymorphism allows the pro-
grarnmerto createa single function that operateson different objects dependingon the
type of object involved.
Post operation. Operationthat placesdata in a mailbox.
Power bus. The collectionof wires usedto distributeDowerto the variouscomponents
of the computersystem.
Pragma. In certainprogramminglanguages,a pseudo-opthat allows assemblycode to
be placed in-line with the high-order language code.
Preempt. A condition that occurs when a higher-priority task interrupts a lower-priority
task.
Preemptive priority system. A systemthat usespreemptionschemesinsteadof round-
robin or first-come/first-servescheduling.

.."-:--:<]
I Glossary 339

Primary memory. See main memory.

Priority ceiling protocol. A method used in interruptdriven systemsto avoid priority
inversion;dictatesthat a task blocking a higher priority task inheritsthe higherpriority
for the duration of that task.
Priority inversion. A condition that occurs becausea noncritical task with a high
execution rate will have a higher priority than a critical task with a low execution
rate.
Processblocks. Subsysterrsused to calculatethe overall systemreliability.
Processingelements. The individual processorsin a multiprocessingsystemsuch as a
systolic or wavefiont architecture.
Program counter. The CPU internal register that holds the address of the next
instructionto be executed.
Program design language. A type of abstracthigh-order languageused in sYstem
specification.
Propagation delay. The contributionto interruptlatencydue to limitation in switching
speedsof digital devicesand in the transit time of electronsacrosswires.
Prototype. A mock-up of a softwaresystemoften used during the designphase.
Pseudocode. A type of program design language.

R
Raise. Mechanismused to initiate a softwareinterrupt in certain languagessuch asC.
RAM scrubbing. A technique used in memory configurations that include error
detectionand correctionchips.The technique,which reducesthe chanceof multiple bit
errorsoccuring,is neededbecausein someconfigurationsmemory effors are corrected
on the bus and not in mernoryitself. The correctedmemory datathen needto be written
back to rnemory.
Random variable. A function mapping elements of the sample space into a real
number.
Rate-monotonic system. A fixed-rate,preemptive,prioritized real-time systemshere
the priorities are assignedso that the higher the executionfrequency,the higher the
priority.
Reactive system. A systemthat has some ongoing interactionwith its enrironment.
Read/write line. Logic line that is set to logic 0 during memory-u'rite and to logr. I
during memory read.
Ready state. In the task-controlblock model, the stateof those thsksthat are r:::i :.-
run, but not running.
Real-time system. A system that must satisf;- explicit tbcundea' :eirrcrit ll=.1
constraintsor it will fail.
Recovery block. Sectionof code that terminate.in che.-\pr.int. lf the lire:r:. -
processingcan resumeat the beginning of a recoren bir-t-k.
Recursion. A methoduherebya procedurecan be self-relerentiiri.ihat ls. l[ !-allin\\-hi-
(call) itself.
340 I Glossary

Reduced instruction set cornputer. Architecture usually characterizedby a small

instruction set with limited addressing modes and hard-wired (as opposed to
microcoded)instructlons.
Reduction in strength. Optimization techniquethat usesthe fastestmacroinstruction
possibleto accomplisha given calculation.
Re-entrant procedure. A procedurethat can be usedby severalconcurrentlyrunning
tasksin a multitaskingsystem.
Register direct mode instruction. Instruction in which the operand field is a
reglster.
Register indirect mode instruction. Instructionin which the operandaddressis kept in
a registernamed in the operandfield of the instruction.
Regressiontesting. A test methodologyused to validate updatedsoftu,areagainstan
old set of test casesthat have alreadybeen passed.
Reliability matrix. In a multiprocessingsystem,a matrix that denotesthe reliability of
the connectionsbetweenprocessors.
Responsetime. The time between the presentationof a set of inputs to a software
systemand the appearanceof all the associatedoutputs.
ReversePolish notation. The result of building a binary parsetree with operandsat the
leavesand operationsat the roots, and then traversingit in post-orderfashion.
Ring buffer. A first-in/first-outlist in which simultaneousinput and output to the list is
achievedby keepinghead and tail pointers.Data are loaded at the tail and read from
the head.
RISC. See reducedinstructionset computer.
Root. In overlaying memory management,the portion of memory containing the
overlay managerand code common to all overlay segments,such as math libraries.
Round-robin system. A systemin which severalprocessesare executedsequentiallyto
completion,often in conjunctionwith a cyclic executive.
Round-robin system with time-slicing. A system in which each executabletask is
assigneda fixed time quantumcalled a time slice in which to execute.A clock is used
to initate an interrupt at a rate correspondingto the time slice.

S
Sample space. The set of outcomesto some experiment.
Sampling rate. The rate at which an analog signal is converted to digital form.
Scale factor. A technique used to simulate floating point operations by assigning an
implicit noninteger value to the least significant bit of an integer.
sccs. Source code control system for managementof system code; typical for UNIX
operatingsystems.
Schedualability analysis. The compile time prediction of execution time per-
formance.
Scheduler. The part of the kernel that determineswhich task will run.
Scratch pad memory. CPU intemal memory used for intermediate results.
 311
I Glossary

Screen signature. The CRC of a screenmemory'

Secondarymemory.Memorythatischaracterizedbylong-termstoragedevicesSucha
tapes,disks, and cards'
S e l f - m o d i f y i n g c o d e ' C o d e t h a t c a n a c t u a l l y c h a n g e i t s e lmay
f ; f o rdiffer
e x a mby
p lonly
e ' b yone
taking
of certain initructions
advantageof tn" tu",iiat the opcodes
bit.
type used for protectrng critical regions'
Semaphore. A special variable
on a semaphor'
two operations that can be performed
Semaphore primitives' The
namelY,wait and signal'
coupled system'
Semidetachedsystem' See loosely
S e n s e l i n e . l n c o r e m e m o r y a w i r e t h a t i s u s e d t o . . r e is
a d ' ' t h e m e m o r y . D ein
p ethe
n d sense
ingonth
in the core, a pulse or is not generated
orientation of the magnetrcfield
line.
one task at a time and
resourcethat can only be usedby
Serialty reusable resource. A
that must be used to comPletion'
Server.Aprocessusedtomanagemultiplerequeststoaseriallyreusableresource
SEU. Seesingleevent upset' as C'
provided by certainlanguages'such
Signal. Exception-handlingmechanism
Signaloperation.op",uti-ononasemaphorethatessentiallyreleasesthereso
semaPhore'
ProtectedbY the
Single.eventupset.Alterationofmemorycontentsduetochargedparticlesprese
event'
Jpu"", ot in the presenceof a nuclear
S|aveprocessor.Theoff-line,processorinamaster/slaveconfiguration.
of the contents of memory'
Soft eiror. Repairable alteration
Softreal-timesystem.Asysteminwhichperformancersdegradedbynotdestroye
failure to meet responsetime constrarnts'
Software. A collection of macroinstructlons'
Softwarereliability.Theprobabilitythatasoftwaresystemwillnotfailbeforesom
time t.
software'
involving redundant hardware or
Spatiat fault tolerance' Methods
Speculativeexecution.Inmultiprocessingsystem s , a s i t u a t i o n t h a t i n v obirrrr'
l r ' e s e:>
ni
executingcode in the next process
processoroptimislcailv and predictively
longasthereisnodepend"ncyinthatprocessblockoncodethatcouidberu:il-:.
other Processors'
the wait semaphoreoperatlon'
Spin lock. Another name for
with all interruptsocculrlng sporadicarir'
Sporadic system. A system
by an interrupt that occursapen'rir'i'i
Sporadic task. A task driven
Spuriousinterrupts.Extraneousandunwantedintemlptsih":,:,:'.']::..]..
loading.
memory'
SRAM. Static random-access
structure'
Stack. A first-inAast-out data
Stackmachines.ComputerarchitectureinuhichLtelnst.';---::i3r=;en:ir3.J
stack' and an accurtuial"t
intemal memory store called a
342 I Glossary

Starvation. A condition that occurs when a task is not being serviced frequently
enough.
State-driven code. Programcode basedon a finite stateautomaton.
Static memory. Memory that does not rely on capacitivechargeto storebinary data.
Statistically based testing. Techniquethat usesan underlyingprobability distribution
function for each systeminput to generaterandom test cases.
Status register. A registerinvolved in interuptprocessingthat containsthe value of the
lowest interrupt that will presentlybe honored.
Stresstesting. A type of testingwherein the systemis subjectedto a large disturbance
in the inputs(for example,a largeburstof interupts), foilowed by smallerdisturbances
spreadout over a longer period of time.
Structure chart. Graphicaldesign tool usedto partition systemfunctionality.
Suspendedstate. In the task-controlblock model, those tasks that are waiting on a
particularresource,and thus are not ready.Also called the blocked state.
Swapping. The simplest schemethat allows the operating system to aliocate main
memory to two processessimultaneously.
Switch bounce. The physical phenomenonthat an eiectricai signal cannot instanfa-
neouslychangefrom its logical false condition.
Synchronous data. See time-relativedata.
Synchronous event. Event that occursat predictabletimes in the flow-of-control.
Syndrome bits. The extra bits neededto implementa Hamming code.
System. An entity that when presentedwith a set of inputs produces
outputs.
System programs. Softwareused to managethe resourcesof the computer.
System unification. A process consisting of linking together the testing software
modulesin an orderly fashron.
Systotic processors. Multiprocessingarchitecturethat consistsof a large number of
uniform processorsconnectedin an array topology.

T
Task-control block. A collection of data associatedwith a task including
processcode (or a pointer to it), and other infonnation.
TCB. See task control block.
Telepresence. A form of virtual reality in which a human operatorcan remotely control
robots or other devicesas if the operatorwere physically present.
Temporal determinism. A conditionthat occurswhen the responsetime for eachset of
outputsis known in a deterministicsystem.
Temporal fault tolerance. Techniquesthat allow for toleratingmisseddeadlines.
Test-and-setinstruction. A macroinstructionthat can atomically test and then set a
panicular memory addressto some value.
Test probe. A checkpointused only during testing'
Test suite. A collection of test cases.
I Glossary 343

Thrashing. Very high paging activity.

Throughput. A measureof the number of macroinstructionsper secondthat can be
processedbasedon some predeterminedinstructionmix.
Time-loading. The percentageof "useful" processingthe computer is doing. Also
known as the utilization factor.
Time overloaded. A systemthat is l00oloor more time-loaded.
Time-relative data. A iollection of data that must be time correlated,
Time-slice. A fixed time quantum used to limit execution time in round-robin
systems.
Transceivers. A transmitheceivehybrid device.
Tiansputer. A fully self-sufficient, multiple instruction set, von Neumann processor,
designedto be connectedto other transputers.
Trap. Internal interrupt causedby the execution of a certain instruction.
Tri-state. A high-impedancestate that, in effect, disconnectsa device from the bus.

U
Unit. A softwaremodule.
Unreachable code. Code that can never be reachedin the normal flow-of-control.
User space. Memory not required by the operating system.
Utilization facator. See time-loadine.

v
Vector processor. See linear iuray processor.
Version control software. A systemthat managesthe accessto the various components
of the system from the software library.
Volatile memory. Memory in which the contents will be lost if power is removed.
von Neumann bottleneck. A situation in which the serial fetch and execution of
instructions limits overall execution speed.

w
Wait and hold condition. The situation in which a task acquires a resourceand then
does not relinquish it until it can acquire another resource.
Wait operation. Operation on a semaphorethat essentiallylocks the resourceprotected
by the semaphore,or prevents the requestingtask from proceeding if the resourceis
already locked.
Wait state. Clock cycle used to synchronizemacroinsEuctionexecution with the access
time of memory.
Watchdog timer. A device that must be reset periodically or a discrete signal is
issued.
 I Glossary

Wavefront processor. A multiprocessing architecture that consists of an array of

identical processors, each with its own local memory and connected in a nearest-
neighbor topology.
White box testing. Logic-driven testing-designedto exercise all paths in the module.
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 lndex

Calling trees, 113-i4

Binary ree, definition, 28
A CASE (comPuter-aidedsoftware
Bit failures, 277
-3 engineering),110
0-address architecture, 25 I Black box testing,264-5
1-addressarchitecture, 3 1-3 Central processing unit (CPU), 2,
Blocked tasks, 181
2-addressarchitecture, 33-5 BRANCH instructions, 38
20-r
3-addressarchitecture, 35 oPeration, 4-7
Broadcastcommunication,133' 135
O-addressmachine, instruction set' 26 structure,4
Buffer size calculation, 245-8
l-address machine, instruction set, 32 tesrifig, 27 l-2
maximum, 248
2-addressmachine' instruction set' 34 throughput, 13
M[\4/1 queue' 251
3-addressmachine, instruction set' 36 Chain reaction, i35
variable, 246-8
0-addressmachine, Programmlng' CheckPoints, 269-70
Buffering data,170-2
28-3r Checksum, 272
Buffering sYstem' 245
Absract data tYPing' 68-71 CICS (Customer Information
B u g s ,2 5 5 - 6
Control SYStem),148
Accumulator, 22 Built-in-softwaretest (BIST), 271
Circular queue (ring buffer), 171
Activity Packets,292 Built-in{est software(BITS)' 271'
Ada, 17,60, 61, 63, 65, 66, 11' CISC (comPlex instruction sdt
2'16
80-1, 150, 182,324 comPuters) architecture' 4 1-3
Burn-in testing,267
Ada-95, 8r-2, 324' 325 Class definitions' 70
Burst petiod, 245,248
Cleanroom testing, 268
Ada++, 70 Bursting of events, 146
Address bus, 2 cMS-2, l7
Bursts of data,245-6
Addressingmodes,21-5 Code generation, 83-4
Bus,2
ALGOL-60, 63, 66 Code insPections,266
arbitration, 50
ALGOL-W 63 COHESION environment, 95
contention, 50
Alpha testing, 267 Collision,50' 175
cycles,21-2
Analog+o-digital (A/D) circuitry, 53 COM variables, 63
grant signal' 50
ANSI-C, 78, 181 COMMON variables, 63
interface unit (BIU), 318
Aiplication Programs, 7 Compaction' 200
time-out signal, 51
Adthmetic logic unit (ALU)' 4 Compare instructions,35-8
transfer mechanisms, 2-3
Arithmetic oPerations,27 Compiler optimization techmques'
Byzantine Generals' Problem' 286
224-i2
Assemblers, 8
AssemblYlanguages,21,82-3' lI2' combination effects' 233-4
324
c common subexPresston
elimination, 225
Asynchronous events, 12 C language,l'1, 60, 61, 65, 66"13'
Automatic teller machine, 118-20 constant folding, 226
75-8,83, 324,326
constant ProPagation' 229
disadvantages,78
crossjumP eliminadon' Ii:-l
B excePtion handling, 77-8
dead-storeeliminanon' ll9
special variable tYPes,75-6
Background, 156 dead-vanable ellmlnarex'- l-tr'
C++ language,70,78, 324' 326
Background Processing, 157-8 fl ow-of-codlFoi r'OtrruDi:-ir- -li
Caches,227
Banker's algorithm, 185-6 intrinsic runcc:'is- lit
Call-by-address,61-2
B A S I C , 1 7 , 6 0 , 6 3 , 6 5 , ' 1 3 , ' 7 4 '1 9 7 lmP Lr':uc-.-r :--::-rroY- ll-
Call-bY-name, 63
Bathtub curve, 257 ItF: L\:r-.$l: l-:
Call-bY-reference,6 1-2 "ft-f'Ii^'tl-
Beta testing, 267 .rtr: -;:::f-::g- ]i -
Call-bY-value' 61-2
BinarY angular measurement .:":6 -:--:r-;g- i-{--
(BAM), t?1-? Call-bY-value-result-63

-t<-s
356
Compiler optimization techniques
\cont.)
reduction in strength, 225
removal of dead or unreachable
code,22'7-8
short-circuiting Boolean code, 230
speculative execulion, 234
use of arithmetic identities, 225
use of registers and caches,22'7
Compilers,8, 83-4
Complex systems,315-16
multimedia, 323
Computer architecturc, 2
Computer architectules,
multiprocessingsystems,
282-3
Computer hardware, 19-58
history, 17
prototypes/simulators,307
Computer hardware/software
integration,301-13
Condition code registers (CCRs), 37
Conditional branching, 114
Conditional transfer, 37
Context, 150
Context-saving rule, 151
Context swirching, 150-l
Contiguous file allocation, 204
Continuousprobability distribution.
242
Continuous random variable, 242
Continuous real-valued function,
222-3
Control flow diagram, 124
Control specifications, 124
contrbl unit (cU), 4
Cooperative multitasking systems,
148-50
Coprocessors,40-l
Core memory, 44
Coroutines,148-50, 157
responsetime, 208
Counting semaphores,178-9
Critical regions, 175
Cross jump elimination, 231-2
CSML,60
Customers, 248
Cycle stealing, 46
Cyclic executive system, 149
Cycl ic redundancycode (CRC), 272-4
Cycling, 307
eychmatic c-or[plexiry, 260
D Double buffering, 170
Daemons, 175
Data bus, 2
Data flow architectures,292-4
Data flow diagrams, 120-4,133,
286,294
conventions,121
DeMarco's rules for, i21
for navigation system, 122
for nuclear plant, 123
Hatley and Pribhai's extensions,
1 a A
Data flow processors,system
specification, 293-4
Data Item Descriptions (DIDs),
99-100
Data strobe (DST), 2-3
Data transfer timing diagram, 3
Databases
applications, 3 17-19
construction,3l7-18
design,317
Deadlock, 183-5
avoidance, 185-6
conditions necessaryfor, 183-4
detection of, 185-7
recovery 186-7
Death spiral, 277
DEBUG, 228
Debuggers, 307
Defects,255-6
Dernand paging, 201-3
DeMarco's rules for data flow
diagrams,121
Descrete random variable, 243-4
Design, 109-40
Detailed design document, 9l
Determinism,l2-13
Digital-to-analog (D/A) circuitry, 53
Direct memory access(DMA),
50-1,218,27',7
acknowledge signal (DMACK),
50
controller, 50-l
memory, 235
request signal (DMARQ, 50
transfer timing diagram, 51
Direct mode instructions, 22
Disable priority interrupt (DPI),
38-9
Discrete random variable, 241
Discrite signal, 3
Dispatcher, 142,149
Distributed systems, 283-91
reliability in, 286-91
DOD-STD-2I674 (ME-STD-
2167A),99-rc4
Double indirect mode addressing,
24-5
Index
DRAGOON,70
Dynamicallocation,65
Dynamic-prioritysystems,154
E
Electropically erasable
programmable read-only
memory (EEPROM),47-8
Embedded data processor (EDP),
318
Embedded distribution systems, 283
Embedded systems, 10
Enable priority interrupt (EPI),
38-9
Enumerated types, 69
Erlang's loss formula, 253-4
ESTEREL, 60
Euclid, 326
Even parity checker, ll7
Event determinism, 12
Event flags, 181-3
Event signals,181-3
Events, 12, 144
bursting of, 146
Exception handling, 68
C language, 77-8
Executive, 143
Exponential distribution, 242, 243
Extemal fragmentation memory,
199
F
Failed system, definition, 9
Failure function, 257
Failures, 255-6
FALSE state, 3
Fault tolerance, 269
Faults, 255-6
Fetch-execute cycle, 5
Fiber Distributed Data Interface
(FDDr),
318
File fragmentation,204
Finite stateautomata(FSA), 117,
t33-4,146-:7
Finitq statemachines(FSMs),117
First-in/first-out(FIFO),202
Fixed-prioritysystems,153-4
Fixed-ratesystems,150
Flash memory,48
Flip-flop, zt4-5
Floatingpoint instructions,39, 214,
215
Flow-of-control optimization,228
Flowcharts,ll2-13, ll4
Foreground,156
 Index 357

Foreground,ibackground systems, Input/output (I/O) L

l 56-60 inteirupt driven, 48, 52
initialization, 158 Languagefeatures,59-85
memory-mapped,49-50, 235
major drawback, 160 comparison of, 74
m e t h o d s2, , 3 , 4 8 - 5 2
real-timeoperation,158-9 see also specific languap,esand
perfcrrmance,239
responsetimes, 160 specific language features
programmed,48-9
Formal program proving, 266-1 Least recently used (LRU) method
Input space,8
FORTRAN, 16, 1'7. 60, 61, 63_6, 202
Inputs, 8
L e v e l i n g ,l 2 l
t 3 - 5 . 1 1 2 ,1 9 7 ,2 1 1 ,3 2 4 Instructioncounting.213-16
Freedomspacestation,318 Linkers, 8
Instructionexecutiontime
Function points, 263 Little's law, 253
s i m u l a t o r s2, 1 7 - l l i
Fusible-linkROMs, 46 Livelock,183
Instructionregister,4
Fusible links, 46-7 LOAD instruction,25, 28, 63
Integration,30l
Load module, 302
Internal fragmentationmemory, 199
Local area networks (LANs), 43,
G Interpolation,geometric
315
interprctation, 222-3
Garbagecollection,204 Locality-of-reference method,
Interpreter, 74
Gaussian(or normal) distribtion, 242 203*4
Irrterrupt, definition, 6
Gaussianprobability function, 243 Locksup,271
Interrupt controllers,54-5
Generalregisters,4 Logic analyzer, 213, 304-5
Interrupt disabling,211
Generator poly nomial, 272 Longmp,77
Interrupt driven I/O, 48, 52
Global variables,63-4 Look-up tables,222-4
Interrupt driven systems,150-6
reuse,238 Loop induction elimination, 227
Interrupt handlers,6, 182, 191, 195
GOTO statemenr, 112, 113 Loop invariant optimization, 226
Interrupt handling,5J, 311
Granularity, 220-1 Loop jamming, 231
timing sequence,55
Graphicaltechniques,design Loop unrolling, 230-l
Intenupt latency, 21O-12
precautions,l38 Loosely coupled system, 10
low priority interrupts high
Group walkthrou ghs, 266 LSB (least significantbir,220
priority,212
Interrupt register 6
M
H Interrupt retum location, 6
Halstead'smetrics, 261-3 Interrupt systems,144-6 McCabe's metric, 260
Hamming code error detection and response1ime, 209 Machine language,20, 83
cotection,274 Intenupt vector, 6 Macrocode, 5
Hard, enor,2'72 Intertaskcommunication,169-88 Macroinstruction execution times,
Harells statecharts,136-7 Intrinsic functions, 226 211
Heisenberg uncertainty pnnciple, ISO Standard9000, 103-4 Macroinstructions, 5
307,310-12 Mailboxes, 173-5
Hybrid systems,150, 156 and semaphores,177
J
implementation,173-4
Jacksonchart, 113 queues,174-5
I
Java language, 326 Major cycles, 155-6
IEEE 830-1993, 104 JOVIAL, 17 Mask registeq 6
rEEE 1003 1-1990, 164-5 Jump instructions,35-8 Mathematicalspecification,11l-12
IEEE standards,106 conditional and unconditional, 37-8 Matrix multiplication, 65
If-then structure, 147 "Jump-to-self instruction, 150 Maximum stack size, 193
Image processing, 319-24 Jump unconditional absolute (JUA), Mealy FSA, 117-18
Immediate mode instructions, 22 38 Memory, 2, 43-8
Implied mode instructions, 22 analysisof requirementsi3-1--
Incidence matrix,287 dangerousallocation- i !-r
In-circuit emulation (ICE), 305-6
K
DMA,235
In-circuit emulator block diagram, 308 'ii i--: .l
Kalman filter, 269 d y n a m i ca l l o c a l r . - r .
Indexed loop construct, 132-3 Kemels extemal frasm3n-'rror-- ^,
Indirect memory instructions, 23 build or buy?, 164 fragmei--:::::. l-'i
Induction v ariable, 22'7 definitions, 142-3 l|]le;nal lnlSneri::]:.. -+.
Inertial measurementunit (IMU), 10 design strategies,141-67 icckine. l0-r
Information hiding, 7l hierarchy. 143 manasement schernes-l-1-
Inheritance, 70 role of. 142 nonvolatile.43
 358 Index

Memory (cont ) Multimeters, 304 P

primary or main, 3 Multiple stack anangements, 193
Package,7 l-2
program arca,236 Multiplexer, 52
P a g ef a u l t , 2 0 1
RAM area, 236 Multiplexer/demul tiplexer (MDM) Page frames, 201
secondary,3 units,318 Page stealing,201
stack area, 236 Multiprocessingsystems,2, 124, Page table, 201
static schemes,205 129, r7 5, 260, 281-99, 3t5 Parallel subsystems,equivalent
rcsiLn|,272 classification of computer reliability, 258
volatile, 43 architectures,282-3 Parameterpassing, 60-73
Memory addressregister (MAR), 4 Multiprogramming, 129 Pamas partitioninE, 92-4, ll0, 265
Memory data register (MDR), 4 Multitasking systems,79, 124, 146, Partial transition table, 120
Memory-loading,201, 312 169, r',]5.260 P a s c a l ,1 7 , 6 0 , 6 I , 6 5 , 6 6 , ' 1 3 ,
rcducing,237-8 Mutex, 177 78-9, 83
variable selection-23r MUX transceivers,52-3 Patching,308, 309-10
Memory-loading f actot, 236-:7 MVT (multiprogramming with a PEARL,326
Memory management, 189-205 variable number of tasks), Peephole optimization, 225
Memory managementmodel, 196 200-1 Petri nets, 124-9
Memory map,234-5 examples,129
Memory-mapped l/o, 49 -50, 235 firing, 125
Messageexchanges,173
N
flowchart analogs,127
Message polynomia| 2'12 Nano-kemel, 143 systolic array, 296-7
Methods, 70 Natural languages,110-11 Phase-driven code, 146-8, l5'7, 208
MFT (multiprogramming with a Nearest neighbor topolo1y, 294 Ping-pong buffering, 170
fixed number of tasks), Network interface unit (NIU), 318 Pipelining, 39-40
198-200 No-op (no-operation), 5 Poissonprocess,244, 252
Microcode, 5 Non-von Nuemann multiprocessing Polled loop systems, 144
Microcontroller, 20 architectures, 21, 291-8 responsetime, 146,208
Microinstructions, 5 NP-completeproblems,218-19 with inrerrupts, 144-6
Micro-kemal, 143 NP-hard problem, 219 Polymorphism, 70
Micromemory,4 N-version programming, 271 POP instruction, 27
Microprogram, 5 POSIX standard,164-5, 318
Mil-Std-15538 bus standard,52-3
Mil-Std-2167A (DOD-STD-21674'),
o Power bus, 2
keemption, 212
99-100 Object-oriented programming, 70 Preemptive priority systems, 153-5
MIMD archiiecture, 283 Occam, 60 Priority ceiling protocol (PCP), 155
Minor cycles, 155-6 Occam-2,325 Priority inversion, 155
MISD architecture, 282 Odd parity checker, 118 Probability density function, 242
Mismatched COMMON overlays, Opcode (operation code), 5 Probability distribution function,
64 Operating system, 8, 143 241-3,248
Missed intemrpts, 276-7 Operational concept document, 89 Probe effect, 311
Mixed listing, 214 Optimization Process, 142
MMll queae,249-52 basic theory,223-32 Processblocks, 258
buffer size calculation, 251 peephole,225 hocessing elements, 294
real-time systems, 252 techryqaes,224-32 Program counter (PC), 4
Modeling techniques, advantages Orbital replaceable units (ORU), Program design languages (PDLs),
and disadvantages,138 318 I l5-16
M o d u l a - 2 ,l ' 7 , 6 3 , 6 5 , 6 6 , 7 1 , Qrganic distributed processing Programmable logic arrays (PLAs),
79-80, 150,183 system,283 46
Modularity, 7l-3 Organic systems, l0 hogrammable read-only memories
MODULE,71,79 Orthogonalstates,284 (PROMs),46-7
Moore finite state automaton, 117 Orthogonality, 134 Programmed I/O,48-9
MSB (most significant bit),22A-1 OS/2 PresentationManager, 148 Programming languages,324-6
MULT1,65 Oscilloscope, 304 Project Whirlwind, 316-17
MULr2, 65 Ostrich algorithm, 186 Propagation delays, 211
Multi Bus tr, 318 Output space, 8 Pseudocode,115-16
Multimedia architecture, 323 0utputs, 8 PUSH instruction, 28
Multimedia systems,321-4 Overlaying, 198 -PUSH operation, 27
 Index
o second-order,289
Queues,mailboxes,i74-5
Queuing models, 241-54
Queuing system, components, 249
Queuing theory,248-52
buffer calculations, 25 1
service and production rates,
250-7
R
Raise operation,181
Random-accessmemory (RAM), 43
corraplion,2T2
dynamic (DRAM),43
scrubbing,157-8, 274-5
static (SRAM), 43
testing,274-6
Randomvariable,241
Rate-monotonic analysis (RMA),
155
Rate-monotonic systems, 154
Reactive systems, 10
Read-only mernory (ROM), 43
conuption,272
testing,272-4
Read/write line, 3
Real-time computing, 16
Real-time languages.See Language
features and under specific
languages
Real-time systems, 1
applications,3l5-26
basic cpncepts,1-18
definition, 9
design issues,14
examples,14-16
full-featured, 160-3
history, 16-17
Mlivl/l queue, 252
significant development events, 16
use of term, 10-11
Recovery blocks, 270
Recursion, 64-5
Re-entrant procedures, 65
Register direct mode instnrctions,
24
Register indirect instructions, 24
Registers, 227
Regression testing, 267
Reliability, 256-63
characterizations,256
in distributed systems, 286-91
Reliability functions, 256-8
Reliability manix;.287-9
hiiher-order, 290-1
maximum,29l
359
Single-eventupset (SEU), 158
third-order, 290 protection mechanisms, 277-8
Resource allocation, 185 Single-processing system,2
Resourcesharing, 175 Slowest cycle computation, 220
Resourcetable, 174 Smalltalk, 70
Responsetime,9,207 Soft enor, 272
calculation,208-10 Software
coroutines,208 concepts,7-8
interrupt systems, 209 d e s i g n ,i 1 0
modelling, 252 Heisenberg uncertainty principle,
phase-drivencode, 208 311
polled loops, 208 history, 17
reducing,219-34 reliability, 256-63
Restoreroutine, 191-2 definition, 256
Retum from interrupt (RI), 38 simulators, 306
RETURN instruction, 38 testing,311-12
Retum location,38 watchdog timers, 56, I57,276,
Reverse Polish notation, 28 2',77
Ring buffers, 171-2 Software Design Descriptions
RISC (reduced instruction set (SDDs), 104
computer) architectures,4 1-3, Software life cycle, 87-107
282,315 concept phase, 89
Round-robin systems, 152 designphase,91-4
Run-time ring buffer, 193 functional requirements, 90
Run-time stack, 190 maintenancephase, 96
nonfunctional requirements,90-l
nontemporal transitions, 96-8
S
Pamas partitioning, 92-4
SABRE, 16 phases,activities and byproducts,
Sample space, 241 88-96
Sampling rate, 53 programming phase, 94-5
Save routine, 191-2 requirements phase, 89-91
Scale factor, 220 rules for requirements and design
Scaled arithmetic, 220-l documents,91
Schedualability analysis, 84 standards,99-107
Scheduler, 142 test phase,95-6
Scheduling, NP-complete, 2 18-l 9 version control software, 94
Scratch pad memory, 4 Spacestation,Freedom,318
Screen signature, 274 SPARC (Special Application of
Second-orderreliability matrix, 289 RISC) series,42
Self-modifying code, 238 Spatial fault tolerance, 269
Semaphores,175-80 Specification, 109-40
and mailboxes, 177 mathematical,111-12
counting, 178-9 Speculative execution, 234
primitives, 176 Spin lock, 177
problems with, 179 Spiral software model, 98
Semiconductor memory. 44-6 sPool-, 175
Semidetachedsystem, 10 Sporadicsystems.150
Senseline, 44 Sporadic tasks, 150
Serially reusable resources, 175 Spurious interrups. 276-l
Series subsystems,equivalent Stack, 38
reliability, 259 architecture. 15
Servers1 , 72,248 area.136
Setjmp, 77 managemen.- 190--
Signal library function call. 182 molel. i51
Signal operation. 176 operations. 21
SIMD architectures,282 overflos.277
 Index
360

Task-controlblock (TCB), 161-3 TRUE state, 2

Standards,software develoPment'
model, 161, 190, l96J Type definition, 69
99-r07
state transitions, 162 Typing, 66-8
Starvation,154, 183
State counters, 149 task management, 163
State-driven code, 146-9 task states,161
Statecharts,133-8, 284 Task resource request table, 173-4 U
depth, 134 Task synchronization, 169-88
Ultraviolet read-onlY memory
orthogonality, 134 Temporal determinism, 13
(uvRoM),47
Statistiqally based testing, 267-8 Temporal fault tolerance, 269
Test-and-setinstruction, 180
UNIT,73
Status register, 6 Universal asynchronousrelaY
sToRE,25,63 Test instructions, 37
terminal (UART), 52
Stress, tesring, 269 Tesr log, 303
Test probe, 269-?0
uNrx, 143,3r8,324
Strong typing,66
User space,198
Structurechans, 113-14 Test tools, 303-7
Utilization factor, definition, 13
StructuredAnalysis, 110, 120 Testing, 263-9
SUBROUTINE, 65, 73 black box, 264-5
Subroutine instructions, 35-8 cleanroom, 268
Subsystems,reliabilities, 259 cPu,27r-2 V
Swapping, 198 goal of,263 Version control software, 94
Switch bounce, 1zl4 memory,272 Virtual reality (VR) systems, 320-l
Synchronous events, 12 planning, 263-9 VLSL292,295
Syndrome,274 RAM, 274-6 Von Neumann bottleneck, 39
System, definition, 8 ROM,272-4 Von Neumann computer
Systembus, 2 software,311-12 architectures,20, j9, 282
System concePts,8-9 statistically based, 267-8
System integration stress,269
backoff method, 308-9 systemJevel, 267
unit level, 264-:7
W
establishing a baseline, 307-8
goals, 302-3 white box, 265-6 Wait and hold condition, 185
methodology, 307-10 Thrashing, 201 Wait operation, 176
System-level testing, 267 Threat-managementsystems, 154 Wamier-Orr notation, 129-33
Systernperformanceanalysis,207-23 Time-loading, 2O7, 312 examples,tr31-2
System programs, 7 and its measuremettt,212-18 Watchdog timer (WDT), 56, 157,
System reliability, 258-63 deterministic Performance,218 276,2"t7
System specification,284-6 instruction counting, 2 13-1 6 Waterfall, 88
data flow processors,293-4 instruction execution time Wavefront processors,297-8
for wavefront Processors,298 simulators,217-18 system specification for, 298
System test suite, 267 logic analYzer,2l3 Weak typing, 66-8
System unifrcation, 302 pictorial representation,2 16-17 Weibull distribu tion, 243
System validation, 303 definition, 13 Weibull probabilitY densitY
Systolic anay reducing,219-34 -. funcrtion, 243
for convolution, 295 Time-overloaded sYstem, 13, 250 Whirlwinil computer, 316-17
in nearest neighbor toPologY' 295 Time-relative buffering, 170-1 White box, testing, 265-6
peti net,296-:1 Time slice, 152 Wide area networks (WANs), 315
Systolic processots, 294-7 Timing code, 305 Working sets, 203-4
. Systolic systems, specification, 297 Timing instructions, 304-5 World Wide Web, 113, 133
Transceiver,52
Transitibn Table, 118
T Transputen, 298
Traps,7, 182
z
fable-driven code, 148
Tri-state condition, 50 Z notation,110
Task, 142