1

MULTIPLEXER AND DEMULTIPLEXER

MULTIPLEXER

combinational circuit that selects binary information from one of the many
input lines and direct it to the output line
Multiplexer means many into one.
Data selector and acts as a switch
parallel to serial converter

selecto

Figure 1.0 General 2n-to-1 MUX

Relationship between selector variable and input :

To determine the number of inputs and selector:

n(no. of inputs) = 2m no. of select lines

m = log2n
Figure 2.0 Mechanism of

Example:
selector
If the number of data lines or inputs is 4, the number of data selector will be:
n=4
m = log24
m = log222
m=2
Advantages of using MUX:
reduce number of wires, therefore number of gates that will be use will
also be reduced
reduces circuit complexity and cost
by using MUX, one can implement adder and subtractor

Multiposition switches are widely used in many electronics circuits. However

circuits that operate at high speed require the multiplexer to be automatically
selected. A mechanical switch cannot perform this task satisfactorily. Therefore,
multiplexer used to perform high speed switching are constructed of electronic
components.

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Multiplexer handle two type of data that is analog and digital. For analog
application, multiplexer are built of relays and transistor switches. For digital
application, they are built from standard logic gates.
The multiplexer used for digital applications, also called digital multiplexer, is
a circuit with many input but only one output. By applying control signals, we can
steer any input to the output. Few types of multiplexer are 2-to-1, 4-to-1, 8-to-1, 16to-1 multiplexer.
Medium Scale Integration MUX

TYPES OF MUX
2-to-1 (1 select line)
4-to-1 (2 select lines)
8-to-1 (3 select lines)
16-to-1 (4 select lines)
32-to-1 (5 select lines)

2:1 Multiplexer
1

Figure 3.0

2:1 MUX schematic symbol and its internal connection

when select (S) is equal to 1, D1 will be selected and the output will be D1,
otherwise D0 when (S) = 0. Table 1.0 and table 2.0 justifies the concept of a 2:1
multiplexer
S
0
0
0
0
1
1
1
1

D1
0
0
1
1
0
0
1
1

D0
Y
0
0
1
1
0
0
1
1
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1
0
0
1
1
1

S1
0
0

S0
0
1

Table 1.0 & Table 2.0

Y
D0
D1

2:1 MUX Truth Table (Complete and condensed)

In table 1.0, D0,D1 and S is the input, we have three(3) inputs including the
selector, therefore, an 8 possible combinations will result in the output Y referring to
the AND implementation of the circuit. Table 2.0 on the other hand shows how D0
and D1 is selected when S will be given a value of 1 or 0.
__

Y = sD1 + sD0
Equation 1.0

2:1 MUX SOP expression

4:1 MULTIPLEXER

Figure 4.0

4:1 MUX schematic symbol and its internal connection

The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output bit. The
four input bits are D0, D1, D2 and D3. Only one of this is transmitted to the output Y.
The output depends on the value of AB which is the control input. The control input
determines which of the input data bit is transmitted to the output. Using the
equation in finding the number of select inputs m = log2n , where n = 4, a 4:1
multiplexer therefore have 2 select inputs s 0 and s1. The following conditions are
applied in a 4:1 MUX in selecting a particular line of data to be output or
transmitted:
IF S1S0=00, then Y= D0
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IF S1S0=01, then Y= D1
IF S1S0=10, then Y= D2
IF S1S0=11, then Y= D3
Translating these conditions in a truth table can be seen in the table below:
S1
0
0
1
1

S0
0
1
0
1

Table 3.0

Y
D0
D1
D2
D3

4:1 MUX Truth Table

Therefore we can construct the SOP expressions that justifies the truth table
of a 4:1 MUX:

Y = S0 S1D0 + S0 S1D1 + S0 S1D2 + S0 S1D3

Equation 2.0

4:1 MUX SOP expression

Obviously, the input selected to be passed to the output depends on the

minterm expressions of the select inputs. In General, for MUXes with n select inputs,
the output Y is given by:

Y = m0D0+ m1D1+ m2D2+ .+ m2n-1D2n1

Equation 3.0

4:1 General Equation for MUXes with an output Y

Thus,

Using the general equation above for an 8:1 MUX, 16:1 MUX and n:1 MUX, we
can arrive to the same procedure in analyzing this MUXes. With the understanding
of the basics of the MUX, we will move in implementing a particular low order of
multiplexer to obtain a higher order of a multiplexer or what we called chaining or
MUX tree.

MUX CHAINING/MUX TREE

Larger multiplexers can be constructed by using smaller multiplexers by
chaining them together. For example, an 8-to-1 multiplexer can be made with two 4to-1 and one 2-to-1 multiplexers. The two 4-to-1 multiplexer outputs are fed into the

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2-to-1 with the selector pins on the 4-to-1's put in parallel giving a total number of
selector inputs to 3, which is equivalent to an 8-to-1.
Implementation of 4:1 MUX using 2:1 MUX
Suppose we will construct a 4:1 MUX that will be used for our circuit but 2:1
MUXes are only available. As an engineer, what we will do in this case?
To create this circuit, we will need three(3) 2:1 MUX, to be able to gasp how will it be
constructed, we will use the following analogy:
We are required to have 4 number of inputs, thus our input n = 4, and we will use a
2:1 MUX, so
4/2 = 2 -------- this is the number of 2:1 MUX S0
2/2 = 1 ------- this is the number of 2:1 MUX S 1
Divide the number of n inputs required to construct the required MUX to the given n
inputs of the given MUX
The circuit will look like this:

Figure 5.0

Using 2:1 MUXes to implement 4:1 MUX

Let x be the output

when s0 = 0 and s1 = 0, x = D0, all 0s are selected in s0
when s0 = 1 and s1 = 0, x = D1, all 1s are selected in s0
when s0 = 0 and s1 = 1, x = D2, all 0s are selected in s0
when s0 = 1 and s1 = 1, x = D3, all 1s are selected in s0
thus, the truth table of this circuit is the same as of a 4:1 MUX
Time-division multiplexing (TDM)
Time-division multiplexing (TDM) is a method of transmitting and receiving
independent signals over a common signal path by means of synchronized switches
at each end of the transmission line so that each signal appears on the line only a
fraction of time in an alternating pattern. This form of signal multiplexing was
developed in telecommunications for telegraphy systems in the late 19th century,
but found its most common application in digital telephony in the second half of the
20th century.
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Implementation of 8:1 MUX using 2:1 MUX
By using 2:1 MUX, we can also create a 8:1 MUX, this time the number of 2:1 MUX is
7 by using the analogy in the previous discussion

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1
Table 4.0

Figure 6.0

8:1 MUX Truth Table

Using 2:1 MUXes to implement 8:1 MUX

The same logic will be applied in this case because we also use 2:1 MUX
Implementation of 8:1 MUX using 4:1 MUX
Using 4:1 MUX to construct an 8:1 MUX is a special case because if we will
use the the previous analogy, it will be not applicable.
We are required to have 8 number of inputs, thus our input n = 8, and we will use a
4:1 MUX, so
8/4 = 2 -------- this is the number of 4:1 MUX in S 0
2/4 = 0.5 ------- N/A
What we will do now is to use the enable input which will be varying to implement
8:1 MUX using 4:1 MUX
The circuit will look like this:

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Y
D0
D1
D2
D3
D4
D5
D6
D7

Figure 7.0

Using 4:1 MUXes to implement 8:1 MUX

Referring
S2
S1
S0
to our
0
0
0
truth table,
0
0
1
if s2 = 0,
0
1
0
then the
nd
0
1
1
2 4x1
1
0
0
MUX (B)
1
0
1
will be
1
1
0
disabled,
1
1
1
since s2 is
complemented in the first 4x1 MUX (A), A will be activated, thus an output of 0. The
output now will depend on the value of S0 and S1. For instance ORing the result of
s0 = 1 and s1 = 0 will give an output Y = D1. From here we can now understand the
result of the other select inputs. B 4x1 MUX will be activated otherwise if s2 = 1.

Application of Multiplexer
1. Communication system Communication system is a set of system that
enable communication like transmission system, relay and tributary station,
and communication network.

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Y
D0
D1
D2
D3
D4
D5
D6
D7

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Figure 8.0

MUX-DEMUX application in Internet

2. Telephone network In telephone network, multiple audio signals are

integrated on a single line for transmission with the help of multiplexers. In
this way, multiple audio signals can be isolated and eventually, the desire
audio signals reach the intended recipients.
3. Computer memory - Multiplexers are used to implement huge amount of
memory into the computer, at the same time reduces the number of copper
lines required to connect the memory to other parts of the computer circuit.
4. Transmission from the computer system of a satellite Multiplexer can be
used for the transmission of data signals from the computer system of a
satellite or spacecraft to the ground system using the GPS (Global Positioning
System) satellites.

Figure 9.0

MUX application in GPS satellites

DEMULTIPLEXER

reverse of a MUX
serial to parallel converter
A demultiplexer is a circuit with one input and many output. By applying
control signal, we can steer any input to the output
forward the data input to one of the outputs depending on the values of the
selection inputs.
sometimes convenient for designing general purpose logic, because if the
demultiplexer's input is always true, the demultiplexer acts as a decoder

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Figure 10.0

A demultiplexer (right to left orientation)

1:2 DEMUX
A 1:2 demux consist of one Data Input and 2 Data outputs, an enable and one
select input. 1:2 demux works the opposite of 2:1 MUX.

Figure 11.0

1:2 DEMUX schematic symbol and mechanism

Figure 11.0

1:2 DEMUX equivalent AND implementation

When S = 0, the input, D, is directed to the output Y0. When S == 1, the input, D, is
directed to the output Y1. Just as before, we think of S as a 1 bit number, which
specifies the output we want to direct the input to.
D
0
1
0
1
Table 5.0

S
0
0
1
1

Y1
0
0
0
1

1:2 DEMUX Truth Table

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To simplify the above truth table, Let us analyse it a little bit. We can clearly
see that the output Y0 follows the data input D if S = 0 and Y1 = 0. Similarly, output
Y1 follows the data input D if S = 1 and Y0 = 0.
S
0
1

Y1
0
D

Table 5.1 Concise 1:2 DEMUX Truth Table

Deriving the output equation from the truth table we get:

Y1 = SD
Y0 = SD

1:4 DEMUX

The 1-to-4 demultiplexer has 1 input bit, 2 control bit, and 4 output bits. An
example of 1-to-4 demultiplexer is IC 74155.
A careful inspection of the Demux circuit shows that it is identical to a 2 to 4
decoder
with enable input. Figure 12.0 shows the circuit of a 2-4 decoder which is
identical to a 1:4 DEMUX

Figure

11.0

1:4 line DEMUX

For the decoder, the inputs are A1and A0, and the enable is input E.
For demux, input E provides the data, while other inputs accept the selection
variables.
Although the two circuits have different applications, their logic diagrams are
exactly the same.
Enable
E
0
1
1
1
1

INPUTS
S1
X
0
0
1
1

S0
X
0
1
0
1

D0
0
1
0
0
0

OUTPUTS
D1
D2
0
0
0
0
1
0
0
1
0
0

D3
0
0
0
0
1

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Table 6.0 1:4 DEMUX Truth Table

The input E is directed to one of the outputs, as specified by the two select lines
S1and
S0.
D0= E if S1S0= 00 D0= S1 S0 E
D1= E if S1S0= 01 D1= S1 S0E
D2= E if S1S0= 10 D2= S1S0 E
D3= E if S1S0= 11 D3= S1S0E

APPLICATION OF A DEMULTIPLEXER

Figure 12.0 Typical application of a demultiplexer

Communication system - The demultiplexer receive the output signals of the

multiplexer and converts them back to the original form of the data at the
receiving end. The multiplexer and demultiplexer work together to carry out
the process of transmission and reception of data in communication system.

Arithmetic Logic Unit - In an ALU circuit, the output of ALU can be stored in
multiple registers or storage units with the help of demultiplexer. The output
of ALU is fed as the data input to the demultiplexer. Each output of
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demultiplexer is connected to multiple register which can be stored in the
registers.
REFERENCES:

http://www.allaboutcircuits.com/vol_4/chpt_9/7.html
http://faculty.kfupm.edu.sa/COE/abouh/Lesson3_5.pdf
http://www.philadelphia.edu.jo/academics/qhamarsheh/uploads/LectureEncod
ers.pdf
youtube.com/NESOacademy multiplexer and demultiplexer
youtube.com/ColumbiaCommunityCollege
/MUXDEMUX

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