Chapter No.

03
1.explain the functions of the ale and io/m signals of the 8085 microprocessor.
2.explain the need of demultiplex the bus ad7 - ad0.
3.figure 3.21 shows the 74ls138 (3to8) decoder with the three input signals. Io/m ,rd and wr from
the 8085 microprocessor . Specify and name the valid output signals.
4.explain why four output signals are invalid or meaningless in figure 3.21.
5.identify appropriate control signals are invalid or meaningless in figure 3.21.
6.in figure 3.4 if the 8085 places the address 20h on a15-a8 and 05hon ad7-ad0 and the ale is high,
specify the output of the latch 74ls373 .
7. At t2 the databyte 4fh is placed on ad7-ad0. Specify the output of the latch in figure 3.4. Explain
your answer.
8. Specify the crystal frequency require for the microprocessor to operate at 1.1 mhz.
9.list the sequence of events which occur when the 8085b mpu reads from memory.
10 if the 8085 adds 87h and 79h specify the contends of accumulator and the status of s,z, and cy
flags.
11.if 8085 has fetched the machine code located at the memory location 205fh. Specify the contends
of program counter.
12.if the clock frequency is 5 mhz , how much time is required to execute an instruction of 18 tstates?
13.assume the memory location 2075h and the databyte 75h. Specify the contents of address bus
ad15-ad8 and the multiplexed bus ad7-ad0.when thread mpu asserts the signal.
14.in the opcode fetch cycle what are the control and status signals asserted by 8085
microprocessor . To enable the memory buffer.
15 the instruction mov b,m copies the content of memory location into register b. It is a 1- byte
instruction with two machine cycles and seven t-states . Identify the second machine cycyle and its
control signal.
16.the instruction in lda 2050h copies the content of memory location 2050h to accumulator.it is a3
byte instruction with four machine cycls and 13 t states .identify fourth machine cycle and its control
signal.
17.in question no.16 identify the contends of the demultiplexed address bu a15- a0 and the data bus
in the fourth machine cycle when the control signal is asserted .

19. In figure 3.15 connect the output line o6 of the decoder to the ce of the memory chip instead of
o0 and identify the memory map.
20. In figure connect a15 to the active high enable signal e3 of the decoder and groun e1. Identify the
memory map of the chip.
21."identify the actual gate you have to use to generate the signal memr in figure 3.15
22.modify the schemantic diagram of 3.15 to eliminate the negative nand gate and obtain the same
memory address range without adding other components.
23.in figure 3.17 exchange a15 and a13 and identify the memory map.
24. In figure 3.17 if we use all the output lines of the decoder to select eight memory chips of the
same size as that of 6116 , what is the total range of memory map.
26. In figure 3.19 specify the memory address range if output line o1 of the decoder 8205 is
connected to the CE signal . Specify the range of foldback memory.
27. In figure 3.19 specify the memory, address range if output line o7 0f the decoder 8205 is
connected to the ce signal of a 2k memory chip.
28.by examining the range of foldback memory specify the relationship between the range of
foldback memorynd the number of dont care lines
29. In figure 3.23 specify the memory addresses for rom 1, rom 2 and r/wm1.
30.in figure 3.23 eliminate the second decoder and connect cs4 to ce0 of the r/wm1 and identify its
memory map and foldback space.
31.in figure 3.24 identify the address range of memory chip.
32.in figure 3.24 connect y1 to ce of the memory chip in place of y0 and identify the address range of
memory chip.
33.in figure 3.24 replace the 27128 memory chip with 2767 memory chip . Identify the primary
address range and mirror address range of the memory chip for given decoding circuit.
34.in question 33 the address line a13 was at a dont care logic state.replace the address line a15-by
the address line a13 , leave a15 as dont care and identify the mirror address range.
35.refer to the memory schematic of the primer . Identify the address range of sram(u3) if the input
y1 of the decoder 74hc39 is asserted.
36. In primer schematic the address line a14 is connected to the memory chip as well as to the input
a of the 2-to-4 decoder . Find the total address range of the memory chip.explain how this decoding
technique helps the designer to use either 16k or 32k memory chip.
37. In figure 3.20 identify the memr signals of the opcode fetch machine cycles.

38. In the figure identify the machine cycle and the hexcode read by the processor when it asserts
the last memr signal.