Description
Open-Feedback Protection
Applications
Related Resources
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February 2013
Part Number
FAN9611MX
Package
16-Lead, Small Outline Integrated Circuit (SOIC)
Packing Method
Packing
Quantity
2,500
Package Outlines
Ordering Information
Suffix
M
JL(1)
JA(2)
35C/W
50 120C/W(3)
Notes:
1. Typical JL is specified from semiconductor junction to lead.
2. Typical JA is dependent on the PCB design and operating conditions, such as air flow. The range of values
covers a variety of operating conditions utilizing natural convection with no heatsink on the package.
3. This typical range is an estimate; actual values depend on the application.
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V IN
L2a
D2
V OUT
V LINE
L2b
R ZCD2
C IN
RIN1
L1a
D1
R ZCD1
L1b
AC IN
EMI Filter
RIN2
C 5VB
ZCD1
CS1 16
ZCD2
CS2 15
5VB
VDD 14
MOT
DRV1 13
AGND
DRV2 12
SS
PGND 11
COMP
FB
R MOT
R INHYST
C SS
R FB1
V BIAS
R FB2
Q1
RG1
Q2
RG2
R OV1
R COMP
VIN 10
C COMP,LF
C COMP,HF
RCS1
OVP 9
C VDD1
C VDD2
C INF
Block Diagram
RCS2
R OV2
C OUT
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Pin Configuration
Pin Definitions
Pin #
Name
Description
ZCD1
Zero Current Detector for Phase 1 of the interleaved boost power stage.
ZCD2
Zero Current Detector for Phase 2 of the interleaved boost power stage.
5VB
5V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC.
MOT
AGND
SS
COMP
FB
OVP
Output Voltage monitor for the independent, second-level, latched OVP protection.
10
VIN
11
PGND
12
DRV2
Gate Drive Output for Phase 2 of the interleaved boost power stage.
13
DRV1
Gate Drive Output for Phase 1 of the interleaved boost power stage.
14
VDD
15
CS2
Current Sense Input for Phase 2 of the interleaved boost power stage.
16
CS1
Current Sense Input for Phase 1 of the interleaved boost power stage.
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4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
-0.3
20.0
VBIAS
-0.3
5.5
-0.3
VBIAS + 0.3
-0.3
VDD + 0.8
-0.3
VDD + 0.3
2.5
0.05
TL
+260
TJ
Junction Temperature
-40
+150
TSTG
Storage Temperature
-65
+150
IOH, IOL
Symbol
Parameter
Min.
Typ.
Max.
Unit
12
18
VDD
VINS
ISNK
1.5
2.0
ISRC
0.8
1.0
(4)
5%
-40
10%
+125
Note:
4. While the recommended maximum inductor mismatch is 10% for optimal current sharing and ripple-current
cancellation, there is no absolute maximum limit. If the mismatch is greater than 10%, current sharing is
proportionately worse, requiring over-design of the power supply. However, the accurate 180 out-of-phase
synchronization is still maintained, providing current cancellation, although its effectiveness is reduced.
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Unless otherwise noted, VDD = 12 V, TJ = -40C to +125C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
80
110
3.7
5.2
mA
mA
Supply
ISTARTUP
IDD
IDD_DYM
(5)
VON
VDD Increasing
9.5
10.0
10.5
VOFF
VDD Decreasing
7.0
7.5
8.0
VHYS
UVLO Hysteresis
VON VOFF
2.5
TA = 25C; ILOAD = 1 mA
5.0
4.8
5.2
5.0
V
mA
Error Amplifier
TA = 25C
2.95
2.91
3.075
VFB = 1 V to 3 V;
|VSS VFB| 0.1V
-0.2
0.2
IOUT_SRC
-13.7
-8
-4
IOUT_SINK
12
VOH
4.5
4.7
V5VB
VOL
0.0
0.1
0.2
gM
Transconductance
50
78
115
mho
120
195
270
mV
VEA
Voltage Reference
IBIAS
3.00
3.05
Electrical Characteristics
PWM
VRAMP,OFST PWM Ramp Offset
tON,MIN
Minimum On-Time
TA = 25C
VFB > VSS
Maximum On-Time
VMOT
tON,MAX
R = 125 k
1.16
1.25
1.30
Maximum On-Time
3.4
5.0
6.6
12.5
16.5
20.0
kHz
400
525
630
kHz
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Unless otherwise noted, VDD = 12 V, TJ = -40C to +125C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.19
0.21
0.23
0.2
85
100
ns
Current Sense
VCS
ICS
CS Input Current
VCSX = 0 V to 1 V
CS to Output Delay
CS Stepped from 0 V to 5 V
tCS_DELAY
-0.2
VZCD is Falling
-0.1
0.1
VZCD_H
IZCD = 0.5 mA
0.8
1.0
1.2
VZCD_L
IZCD = 0.5 mA
-0.7
-0.5
-0.3
mA
10
mA
IZCD_SRC
IZCD_SNK
tZCD_DLY
(5)
Turn-On Delay
ZCDx to OUTx
180
ns
2.0
Output
ISINK
ISOURCE
1.0
tRISE
Rise Time
10
25
ns
tFALL
Fall Time
20
ns
VO_UVLO
IRVS
(5)
(5)
500
mA
-7
-5
-3
-0.40
-0.25
-0.10
0.76
0.925
1.10
0.2
IVINSNK
-0.2
1.4
2.5
A
V
3.1
3.7
4.3
VFF_RATIO
(5)
3.6
4.0
4.3
VFF_UL / VIN_BO
Phase Management
VPH,DROP
0.66
0.73
0.80
VPH,ADD
0.86
0.93
1.00
3.15
3.25
3.35
TA = 25C
DRV1=DRV2=0 V
FB Decreasing
0.24
DRV1=DRV2=0 V
3.36
3.50
3.65
Note:
5. Not tested in production.
2008 Fairchild Semiconductor Corporation
FAN9611 Rev. 1.1.7
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Theory of Operation
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2. Interleaving
4. Input-Voltage Feedforward
Basic voltage-mode control, as described in the
previous section, provides satisfactory regulation
performance
in most cases. One important
characteristic of the technique is that input voltage
variation to the converter requires a corrective action
from the error amplifier to maintain the output at the
desired voltage. When the error amplifier has adequate
bandwidth, as in most DC-DC applications, it is able to
maintain regulation within a tolerable output voltage
range during input voltage changes.
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9
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10
8. Power Limit
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11
Functional Description
be used as an indication that the chip is running.
Potentially, this behavior can be utilized to control the
inrush current limiting circuit.
Internal
Circuits
PWM
signal
.
0.3/0.0V
RZCD
ARM
(ready)
1(2)
ZCD
INHIBIT
ZCD Valley
Detector
To ZCD
winding
ZCD
signal
(true differentiator)
Positive Negative
Clamp Clamp
V
N AUX
1
O
0 .5 mA 2 N BOOST
2.4
1
2
1.25 VINSNS , PK
(2)
This method is especially dangerous in power-factorcorrector applications because the error amplifiers
bandwidth is typically limited to a very low crossover
frequency. The slow response of the amplifier can
cause considerable overshoot at the output.
(1)
PGND is the reference potential (0 V) for the highcurrent gate-drive circuit. Two bypass capacitors should
be connected between the VDD pin and the PGND pin.
One is the VDD energy storage capacitor, which provides
bias power during startup until the bootstrap power
supply comes up. The other capacitor shall be a goodquality ceramic bypass capacitor, as close as possible
to PGND and VDD pins to filter the high peak currents
of the gate driver circuits. The value of the ceramic
bypass capacitor is a strong function of the gate charge
requirement of the power MOSFETs and its
recommended value is between 1 F and 4.7 F to
ensure proper operation.
5. Soft-Start (SS)
Soft-start is programmed with a capacitor between the
SS pin and AGND. This is the non-inverting input of the
transconductance (gM) error amplifier.
At startup, the soft-start capacitor is quickly pre-charged
to a voltage approximately 0.5 V below the voltage on
the feedback pin (FB) to minimize startup delay. Then a
5 A current source takes over and charges the softstart capacitor slowly, ramping up the voltage reference
of the error amplifier. By ramping up the reference
slowly, the voltage regulation loop can stay closed,
actively controlling the output voltage during startup.
While the SS capacitor is charging, the output of the
error amplifier is monitored. In case the error voltage
(COMP) ever exceeds 3.5 V, indicating that the voltage
loop is close to saturation, the 5 A soft-start current is
reduced. Therefore, the soft start is automatically
extended to reduce the current needed to charge the
output capacitor, reducing the output power during
startup. This mechanism is integrated to prevent the
voltage loop from saturation. The charge current of the
soft-start capacitor can be reduced from the initial 5 A
to as low as 0.5 A minimum.
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V DD
(3)
1A
To take advantage of the higher sink current capability
of the drivers, the gate resistor can be bypassed by a
small diode to facilitate faster turn-off of the power
MOSFETs. Traditional fast turn-off circuit using a PNP
transistor instead of a simple bypass diode can be
considered as well.
R GATE =
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16
= 27k 5 pF = 130ns
or
P =
1
= 1.2MHz
2 27 k 5 pF
(4)
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17
Frequency Clamp
Application Information
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b.
c.
d.
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The return path for the gate drive current and VDD
capacitor should be connected to the PGND pin.
General
Keep high-current output and power ground paths
separate from analog input signals and signal
ground paths.
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20
Description
Name
VLINE.ON
VLINE.OFF
fLINE,MIN
Nominal DC Output
VOUT,RIPPLE
VOUT,LATCH
POUT
tHOLD
RG1, RG2
DG1, DG2
CVDD1
2.2
CVDD2
47
RCS1, RCS2
Value
VOUT
RINHYST
RIN2
VOUT,MIN
fSW,MIN
Maximum DC Bias
VDDMAX
0.95
PMAX,CH
COUT
L
tON,MAX
N
10
IL,PK
VIN
POUT_NO_FF = PMAX
3.7
IO,MAX
RZCD1,
RZCD2
C5VB
RMOT
Soft-Start Capacitor
CSS
Compensation Capacitor
Compensation Resistor
Compensation Capacitor
Feedback Divider
(5)
where VIN is the voltage at the VIN pin and PMAX is the
desired maximum output power of the converter which
will be maintained constant while the input voltage
feedforward circuit is operational.
0.15
CCOMP,LF
RCOMP
CCOMP,HF
RFB1
Feedback Divider
RFB2
ROV1
ROV2
RIN1
PMAX, CH = 1.2
POUT
2
(6)
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COUT(RIPPLE)
COUT(HOLD) =
POUT
=
4 fLINE,MIN VOUT VOUT,RIPPLE
R ZCD1 = R ZCD2 =
(7)
2 POUT t HOLD
2
2
VOUT OUT,RIPPLE VOUT,MIN
(8)
L LINE,MAX =
(9)
(10)
2
VLINE,MAX
VOUT 2 VLINE,MAX
t ON,MAX =
2
VLINE,
OFF
RFB2 =
2 VLINE,OFF
L
t ON,MAX
(11)
2 PMAX, CH
VOUT
0.12mA VOUT
(12)
(17)
(16)
3V VOUT
3V
=
PFB
IFB
(15)
2
VLINE,
OFF VOUT 2 VLINE, OFF
(14)
L LINE,OFF =
0.5 VOUT
N 0.5mA
(18)
(13)
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C SS =
(19)
R OV2 =
gM IOUT,MAX
4.1V COUT (2 f0 )
RFB2
RFB1 + RFB2
VOUT, LATCH
R OV1 =
1 R OV2
3.5V
1
2 f0 CCOMP,LF
CCOMP,HF =
1
2 fHFP RCOMP
(21)
LINE,MAX
(26)
2 VLINE,MIN PINSNS
2 VLINE,MIN
RIN1 =
1 RIN2
0.925V
(27)
(22)
(23)
RINHYST
2 VLINE,ON RIN2
0.925V
RIN1 + RIN2
=
2A
(28)
0.925 V V
RCOMP =
(25)
(20)
C COMP,HF < 4 C SS
(24)
POVP
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VDD MAX
1.0 A
(29)
0.18V
IL,PK
(30)
1 4 2 V
LINE,OFF
2
R CS1
PRCS1 = 1.5 IL,PK
6
9 VOUT
RG
DG
RCS
(31)
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25
Typical characteristics are provided at TA = 25C and VDD = 12 V unless otherwise noted.
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26
Typical characteristics are provided at TA = 25C and VDD = 12 V unless otherwise noted.
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Gate Drive 1
Gate Drive 1
Gate Drive 2
Gate Drive 2
Inductor Current 1
Inductor Current 1
Inductor Current 2
Inductor Current 2
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28
Typical characteristics are provided at TA = 25C and VDD = 12 V unless otherwise noted.
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Typical characteristics are provided at TA = 25C and VDD = 12 V unless otherwise noted.
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Typical characteristics are provided at TA = 25C and VDD = 12 V unless otherwise noted.
IL1
IL1
IL2
IL2
IL1 + IL2
IL1 + IL2
VGATE
VGATE
VOUT
VOUT
Line Current
Line
Current
Line
Vol
VOUT
110VAC
220VAC
COMP
Line
Current
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Input Voltage
400 W
400 V (1 A)
100
100
95
95
Efficiency (%)
Efficiency (%)
Evaluation Board
85
80
80
10
20
30
40
50
60
70
80
90
10
100
30
40
50
60
70
80
90
100
20
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Related Products
Part
Number
FAN6961
Description
Green Mode PFC
PFC Control
Number
of Pins
Comments
Industry Standard Pin-Out with
Green Mode Functions
FAN7528
FAN7529
Low THD
FAN7530
FAN7930
FAN9611
16
FAN9612
16
Table 1.
Related Resources
AN-6086: Design Consideration for Interleaved Boundary Conduction Mode (BCM) PFC Using FAN9611/12
AN-9717: Fairchild Evaluation Board User Guide FEB388: 400W Evaluation Board using FAN9611/12
AN-8021: Building Variable Output Voltage Boost PFC Converters Using FAN9611/12
Fairchild 300-W Low Profile Evaluation Board: FEBFAN9611_S01U300A
References
1.
2.
L. Huber, B. Irving, C. Adragna and M. Jovanovich, Implementation of Open-Loop Control for Interleaved
DCM/BCM Boundary Boost PFC Converters, Proceedings of APEC 08, pp. 1010-1016.
C. Bridge and L. Balogh, Understanding Interleaved Boundary Conduction Mode PFC Converters,
Fairchild Power Seminars, 2008-2009.
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33
10.00
9.80
8.89
16
4.00
3.80
6.00
PIN ONE
INDICATOR
1.75
5.6
0.51
0.35
1.27
(0.30)
0.25
1.27
C B A
0.65
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
Physical Dimensions
0.25
0.19
0.10 C
0.50
0.25 X 45
(R0.10)
GAGE PLANE
(R0.10)
0.36
8
0
SEATING PLANE
0.90
0.50
(1.04)
DETAIL A
SCALE: 2:1
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