Introduction
M a n y power circuit topologies have been investigated in an
attempt to achieve soft switching in a high power inverter. Soft
switching operation of the power devices can nearly eliminate
switching losses and therefore allow operation at significantly
higher switching frequencies. However, the realization of soft
switching high power circuits (above 100 kW) has been hampered
because significantincreases in device count, device voltage ratings,
and/or current ratings is usually necessary. Additional conduction
losses in the devices and passive components, primarily the
resonant inductors, can further offset the advantage of a soft
switching circuit at high power levels.
One of the most successful circuits investigated to date is the
Resonant dc Link (RDCL) and the Active Clamped Resonant dc
Link (ACRDCL) inverters which impose respectively a 2 - 2.5,and
a 1.4-1.8per unit voltage stress [l-41on all devices. The ACRDCL
requires one additional (clamp) switch. However, both converters
have a major disadvantage in that all inverter switches are required
to change state synchronously with the resonating dc bus This
discrete pulse modulation (DPM) umtrol precludes achieving PWM
control of each phase, resulting in sub-harmonicsand more crudely
formed sinewaves. The highest resonant frequency that can be
attained at high power levels is severely limited by the intrinsic
properties of the power devices and the quality of the passive
components. On the other hand, it is crucial in high power drives
with high dc bus voltages to be able to produce narrow voltage
pulses (smaller than the resonant period) whenever low output
voltages are modulated and to transition into square wave operation
whenever high output voltages are required. Although the
possibility of semi-PWM in three phase ACRDCL inverters has
been investigated[5] it is expected that turning off inverter switches
during the resonant cycle will lead to higher device stresses and
additional control complexity.
Most circuit topologies which simultaneously enable soft switching
and PWM control have imposed a penalty with respect to device
I2Cdc
--4
VD(
a.
VD(
b.
d.
e.
' attempts to
The clump commutation phase begins when V
overshoot the positive dc rail, forward biasing D1 and thereby
connecting 'V to the positive dc rail. At this time S l is gated-
INVERTER
RECTIFIER
CF2
IO21
1011
3phaseload
1034
f.
2Cdc
I
C.
d.
f.
a.
+
l
7-
T
I
b.
g*
Figure 7. Commutation from Diode
a.
The commutation at low load currents from a conducting switch is
illustrated in Fig. 8a. The commutation sequence (see Fig. 8) is
similar to that described above except there are no r m p phases:
b.
C.
/ Iboost
d.
e.
Figure 8. Commutation from Switch - Low Current.
is gated off. At thispoint D2 is now conducting all of Il.
1232
b.
(3)
C.
VF
S1
Cr
SimulationResults
D2
a.
1233
finn n.
W
---.-I
c)
n 300.0-
f
L
0.000~
-300.0-
a.
400.01
h
1)
5 225.0-
-300.0.
0.0 loo
5.0
1.0
t kc)
1.5
b.
Figure 10. ARCP Commutation at Low Current
LF1 (pH)
CF1 (pF)
LF2 UH)
CF2 (pF)
Vpeak
Input THD(%)
600.0t
5
400.0-
200.0-
0 000
3.888
3.891
3.894
HSW
320
220
320
220
750
0.153
0.255
9.18
8.28
na
1.44
5.47
6.92
4.49
11.4
93.2
ACRDCL
320
220
320
220
1200
0.371
0.513
9.18
8.22
77.1
1.48
0.823
2.30
6.30
8.61
94.6
ARCP
320
220
320
220
750
0.124
0.292
9.42
8.22
150.0
1.66
0.362
2.02
4.68
6.71
95.8
3.897 1 0 7 ~
a.
1234
0.0199
0.0472
31.9
33.2
150.0
2.34
1.27
3.62
5.61
9.23
94.4
Conclusion
The ARCP power circuit is clearly the preferred topology for high
performance. high power convertersdue to its unique characteristics
of PWM control and soft switching without additional voltage or
current stresses in the primary devices and low losses in the
additional passive Components. Summarizing one can state that the
ARCP advantages are:
equivalent spectral performance to hard-switching converter
reduced device stresses compared with the hard switched and
and the ACRDCL converter (controlled di/dt and dvldt)
capable of high switching frequencies with low switching
losses
high efficiency
small auxiliary devices
The ARCP has as major disadvantage in that auxiliary devices and
associated gating circuitry are required; this can represent a
considerable cost penalty for low power converters. However, for
high power applications, particularly when high switching
frequencies are desired, the disadvantagescited are outweighed by
the substantial performance advantages gained.
References
D.M. Divan, "Resonant DC Link Converter - A New Concept in Static
Power Conversion," JEEE-JAS ConferenceProceedings 1986, pp. 267-280.
2. D.Divan, G.Skibinski, "Zero Switching Loss Invertas for High Power
Applications", IEEE-IAS Conference Record, 1987, pp. 627-634.
3. R.W. De Doncka, G. Venkataramanan, D. Divan,"Design Methodologies of
Soft Switching Inverted', IEEE-IAS ConferenceRecords, 1987,pp. 626639.
A. Mertens, D.M. Divan, "A High Frequency Resonant dc Link Inverter
4.
Using IGBTs", IPEC, Tokyo, 1990, pp. 152-160.
5. R.W. De Doncka, G.Venkataramanan, "A New Single phase AC to DC
Zero Voltage Soft Switching Converter", IEEE-PESC '90 Conference
Records, 1990, pp. 2W212.
6. O.D. Patterson, D. Divan,"A Pseudo Resonant Full Bridge DC/DC
Convert"', PESC 87 Cod. Records, pp.424-430.
J.A Ferreua, A. van Ross, J.D. Van Wyk, "A Generic Soft Switching
7.
Converter Topology with a Parallel Nonlinear Network for High Power
Application", IEEE-PESC90 Conference Records, 1990, pp 298-304.
8. A. Cheriti, K.AI-Haddad,e.a.,"A Rugged Soft Commutated PWM Inverter
for Ac Drives", IEEE-PESC90 Conference Recads, 1990,pp.656662.
9. R.W. De Doncker, R.L. Steigerwald, D.M. Divan,"Soft Switching in High
Power Converters", Seminar IEEE-APEC, Fifth Annual Conference 1990,
Seminar Wakbook, Seminar 8, pp. S8-53 - S8-76.
10. G. Bingen, "Utilisation de Transistors a Fort Courant et Tension Elevee,"
European Power Electronics and Applications Conferenceproceedings 1985,
pp. 1.15-1.20.
11. W. McMurray,"Resonant Snubbers With Auxiliary Switches." IEEE-IAS
Rocecdigs 1989, pp. 829-834.
C0nf"W
1.