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CHETTINAD COLLEGE OF ENGINEERING & TECHNOLOGY

DEPARTMENT OF ECE
CS6303 COMPUTER ARCHITECTURE (6th semester)
16 MARKS QUESTION BANK

UNIT I OVERVIEW & INSTRUCTIONS

1. Explain Eight ideas invented for computer design (8marks)
1. Design for Moores Law
2. Use Abstraction to Simplify Design
3. Make the Common Case Fast
4. Performance via Parallelism
5. Performance via Pipelining
6. Performance via Prediction
7. Hierarchy of Memories
8. Dependability via Redundancy
2. Explain Components of a computer system or hardware / software of computer system
(16marks)
Diagram for Components of a computer system
Functional unit, Memory unit(primary and secondary memory),CPU,Input/Output
devices Types of software,OS
Input devices-keyboard , mouse etc.,
Output devices- LCD,LED,types of printer
3. Discuss Technology or generations of computer in brief(16marks)
First ,second, third, fourth and fifth geneartion computer
4. Discuss Performance of CPU & CPU performance equation or 4 types of problem in text
book (Theory and problems) (16marks)
5. Write note on Power wall equation of CPU (8marks)
6. Write note on Uniprocessors to multiprocessors (8marks)
7. Instructions operations and operands representing instructions Logical operations
control operations (16 marks)
(or) Explain Logical operations & control operations with examples (16 marks)

PREPARED BY: S.SAKTHI, AP/IT

or
Explain immediate, register, Base/Displacement, PC relative, Pseudo direct addressing
(Theory and problems )(16marks)
9. Suppose we have two implementations of the same instruction set architecture. Computer
A has a clock cycle time of 250 ps and a CPI of 2.0 for some program, and computer B has
a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is
faster for this program and by how much? (8marks)
10. A compiler designer is trying to decide between two code sequences for a particular
computer. The hardware designers have supplied the following facts: (8marks)
class BC
CPI

Code Sequence
1
2

CPI for each instruction class

A
B
C
1
2
3
Instruction counts for each instruction class
A
B
C
2
1
2
4
1
1

PREPARED BY: S.SAKTHI, AP/IT

For a particular high-level language statement, the compiler writer is considering two code
sequences that require the following instruction counts:
a) Which code sequence executes the most instructions?
b) Which will be faster?
c) What is the CPI for each sequence? (Dec 2014)
11. A program runs in 12 seconds on computer A, which has a 3 GHz clock. We have to design
a computer B such that it can run the same program within 9 seconds. Determine the clock
rate for computer B. Assume that due to increase in clock rate, CPU design of computer B
is affected ant it requires 1.2 times as many clock cycles as computer A for execution this
program. (8marks)
12. Assume a two address format specified as source, destination. Examine the following
sequence of instructions and explain the addressing modes used and the operation done in
every instruction. (Dec 2014) (10 marks)
1)Move (R5)+, R0
3)Move R0, (R5)
4)Move 16(R5),R3
13. Register R1 and R2 of a computer contain the decimal values 1200 and 2400 respectively.
What is the effective address of the memory operand in each of the following instructions?
1)Load 20(R1), R5 2) Add (R2), R5 3)Move #3000, R5 4)sub (R1)+, R5.
14. Consider three different processors p1,p2,p3 executing same instruction set.P1 has a
3Ghz clock rate and a CPI of 1.5 . P2 has a 2.5 Ghz clock rate and a CPI of 1.0 .P3 has a
4.0 Ghz clock rate and has a CPI of 2.2. (10 marks)
(i) Which processors has the highest performance expressed in instruction per second?
CPU time=Instruction count* CPI / Clock rate
CPU time P1=Instruction count* CPI / Clock rate =n*1.5/3*109 =n*0.5 *10-9 sec
CPU time P2=Instruction count* CPI / Clock rate = n*0.4*10 -9 sec
CPU time P3=Instruction count* CPI / Clock rate = n*0.55 * 10-9 sec
Therefore p2 produces highest performance than other processors.
(ii) If the processor each execute a program in 10 seconds,find the number of cycles and
the number of instructions.
Number of clock cycles:
CPU time for p1,p2,p3=10 sec
CPU time= CPU clock cycles / clock rate
CPU clock cycles = CPU time * clock rate
CPU clock cycles P1 = 10 sec * 3 * 109 Hz =30*109 cycles
CPU clock cycles P2 = 10 sec * 2.5 * 109 Hz =25*109 cycles
CPU clock cycles P3 = 10 sec * 4 * 109 Hz = 40*109 cycles
Number of instructions count:
CPU clock cycles = Instruction count* CPI
Instruction count = CPU clock cycles / CPI
Instruction count P1=CPU clock cycles / CPI = 30*10 9 cycles / 1.5 =20 *109 instructions
Instruction count P2 = CPU clock cycles / CPI = 25*10 9 cycles / 1.0 =25 *109 instructions
Instruction count P3= CPU clock cycles / CPI = 40*109 cycles / 2.2 =18.18 *109 instructions

UNIT II ARITHMETIC OPERATIONS

1. Write notes on ALU - Addition and subtraction (Theory or problem) (8/16 marks)
(1s complement, 2s complement, addition and Subtraction problem, half and full adder,
3. Explain half and full adder in detail. (8marks)
4. Explain Multiplication algorithm in detail.(Theory or problem) (16marks)
(Recode multiplier & bit pair recoding multiplication problems, Booths multiplication
problems)
5. Explain Division algorithm in detail (Theory or problem) (16marks)
(Restoring and Non restoring division problems)

6. Explain Floating Point operations (floating point addition, floating point subtraction,
floating point multiplication and floating point division-steps, flowchart with example
problems) in detail. (Theory or problem) (16marks)
(Single and double precision problems)
7. Represent 1259.12510 in Single and double precision format.
8. Represent -307.187510 in Single and double precision format
9. Explain floating point addition and subtraction in detail. (16marks)
or

PREPARED BY: S.SAKTHI, AP/IT

Perform floating point addition using the numbers 0.510 and 0.437510 use the floating

PREPARED BY: S.SAKTHI, AP/IT

Perform floating point multiplication using the numbers 0.510 and 0.437510 use the

10. Write notes on Subword parallelism. (4 marks)

11. Explain floating point number representation and the IEEE 754 format. (16)

UNIT III PROCESSOR AND CONTROL UNIT

1. Explain Basic MIPS implementation (16marks)
2. Explain Building datapath in detail. (16marks)
or Data path segment for ALU instructions, Data path segment for load and store word
instructions & Data path segment for branch instruction
3. Explain Control Implementation scheme of MIPS or R type, Load, Branch on equal and
Jump instructions (16marks)
4. Explain Pipelining and types of Pipeline hazards or data, structural and control / instruction
hazards (16marks)
5. Write notes on Pipelining or Pipeline hazards. (16 marks)
6. Explain Pipelined datapath and control unit in detail
or
Explain implementation of MIPS instruction pipeline and pipeline control in detail
(16marks)
7. Explain various ways to handling Data hazards (8 marks) (text book + xerox)
8. Explain various ways to Handling Control hazards (8 marks) (text book + xerox)
9. Write notes on branch prediction techniques. (8 marks)
10. Explain Exceptions and its ways to handle exception in MIPS. (16marks) (text book +
xerox)

PREPARED BY: S.SAKTHI, AP/IT

UNIT IV PARALLELISM
1. Explain Instruction-level-parallelism or Static & Dynamic multi-issue processors or
different ways of implementing a multi-issue processors (8/16marks) (text book + xerox)
2. Explain the dynamic multi-issue processors or limitations of ILP.(8marks) (text book +
xerox)
3. Explain dynamic pipeline scheduling.( xerox)
4. Explain Parallel processing challenges with problems (8marks) (text book + xerox)
5. Explain Flynn's classification (SISD, SIMP, MISD, MIMD, SPMD(single program multiple data
stream),MPMD, VECTOR and SCALAR systems) (8/16marks) (text book + xerox)
Single program, multiple data streams (SPMD)
Multiple autonomous processors simultaneously executing the same program (but at independent
points, rather than in the lockstep that SIMD imposes) on different data. Also termed single process, multiple
data - the use of this terminology for SPMD is technically incorrect, as SPMD is a parallel execution model
and assumes multiple cooperating processes executing a program. SPMD is the most common style of
parallel programming. The SPMD model and the term was proposed by Frederica Darema. Gregory F. Pfister
was a manager of the RP3 project, and Darema was part of the RP3 team.
Multiple programs, multiple data streams (MPMD)
Multiple autonomous processors simultaneously operating at least 2 independent programs.
Typically such systems pick one node to be the "host" ("the explicit host/node programming model") or
"manager" (the "Manager/Worker" strategy), which runs one program that farms out data to all the other
nodes which all run a second program. Those other nodes then return their results directly to the manager. An
example of this would be the Sony PlayStation 3 game console, with its SPU/PPU processor .

6. Explain Hardware multithreading and its types (text book + xerox)

Or Fine/Interleaved, Coarse/Blocked and Simultaneous Multithreading(SMT). Or various
ways methods of Hardware multithreading (8/16marks)
7. Explain Multicore processors (text book + xerox)
Or Shared multicore processors (SMP) and Distributed / cluster-message passing multicore
processors (8/16marks)

UNIT V MEMORY AND I/O SYSTEMS

1. Explain Memory hierarchy (8 marks)
2. Explain Memory technologies (16 marks)
3. Explain Cache basics & Measuring and improving cache performance
Or Discuss Cache memory in brief. (16 marks) (Theory and problems)
4. Explain Page replacement algorithms(Theory and problems) (8 marks)
5. Explain Virtual memory (16 marks)
6. Explain TLBs (8 marks)
7. Explain Input/output system(16 marks)
8. Explain Programmed I/O(16 marks)
9. Explain DMA in detail (16 marks)
10. Explain bus arbitration in detail. (8 marks)
11. Write notes on interrupt. (8 marks)
12. Explain I/O processors. (8/16 marks)

Explain Multiplication algorithm in detail.(Theory or problem) (16marks)

Multiplication algorithm: