Srr320405 Vlsi Design

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Code No: RR320405 Set No. 1

III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
VLSI DESIGN
( Common to Electronics & Communication Engineering and Electronics &
Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Define threshold voltage of a MOS device and explain its significance.
(b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8]
2. With neat sketches explain how Diodes and Resistors are fabricated in Bipolar
process. [16]
3. Design a stick diagram for n-MOS Ex-OR gate. [16]
4. Design a layout diagram for CMOS inverter. [16]
5. Derive an equation for the propagation delay from input to output of the pass
transistor chain shown in Figure 5. [16]
Figure 5
6. Using PLA Implement JK Flip flop circuit.
7. With respect to synthesis process explain the following terms.
(a) Flattening
(b) Factoring.
(c) Mapping.
8. Explain about the following packaging design considerations.

[16]
[6+5+5]
(a) Electrical considerations.

(b) Mechanical design consideration. [8+8]
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VLSI DESIGN
Telematics)
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1. (a) With neat sketches explain the drain characteristics of an n-channel enhance-
ment MOSFET.
(b) n-MOS Transistor is operated in the Active region with the following parame-
ters VGS = 3.9V ; Vtn = 1V ; W/L = 100; µnCox = 90 µA/V 2
Find its drain current and drain source resistance. [8+8]
2. With neat sketches explain how Diodes and Resistors are fabricated in Bipolar
process. [16]
3. Design a stick diagram for the NMOS logic shown below Y = (A + B + C) [16]
4. Design a layout diagram for two input nMOS NAND gate. [16]
5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-

channel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance
Rsp = 2.5 × 104 Ω per square. [16]
www.andhracolleges.com Figure 5
6. (a) What are the advantages and disadvantages of the reconfiguration.
(b) Mention different advantages of Anti fuse Technology. [8+8]
7. Clearly explain each step of high level design flow of an ASIC. [16]
8. (a) Clearly explain the diffusion process in IC fabrication.

(b) Clearly explain various diffusion effects in silicon with emphasis on VLSI ap-
plication. [8+8]
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VLSI DESIGN
Telematics)
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1. (a) Derive an equation for IDS of an n-channel Enhancement MOSFET operating

in Saturation region.
(b) An nMOS transistor is operating in saturation region with the following pa-
rameters. VGS = 5V ; Vtn = 1.2V ; W/L = 110; µnCox = 110 µA/V 2 .
Find Transconductance of the device. [8+8]
2. (a) With neat sketches explain CMOS fabrication using n-well process.
(b) Explain how capacitors are fabricated in CMOS process. [10+6]
3. Design a stick diagram for the CMOS logic shown below Y = (A + B + C) [16]
4. Explain with suitable examples how design the layout of a gate to maximize per-
formance and minimize area. [16]
5. Derive an equation for the propagation delay from input to output of the pass
transistor chain shown in Figure 5. [16]
www.andhracolleges.com Figure 5
(b) Mention different advantages of Anti fuse Technology.
7. Clearly explain each step of high level design flow of an ASIC.
8. With neat sketches explain the oxidation process in the IC fabrication process.
[8+8]
[16]
[16]
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VLSI DESIGN
Telematics)
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1. (a) Define threshold voltage of a MOS device and explain its significance.
(b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8]
2. (a) With neat sketches explain how resistors and capacitors are fabricated in p-
well process.
(b) With neat sketches explain how resistors and capacitors are fabricated in n-
well process. [8+8]
3. What is a stick diagram and explain about different symbols used for components
in stick diagram. [16]
4. Design a layout diagram for CMOS inverter. [16]
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 104 Ω per square. [16]
Figure 5
(b) Mention different advantages of Anti fuse Technology. [8+8]
7. Explain the following process in the ASIC design flow.
(a) Functional gate level verification.

(b) Static timing analysis. [8+8]
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8. (a) Mention the properties of the twin oxide.
(b) Clearly explain about ION implantation step in IC fabrication. [6+10]
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Code No: RR320405 Set No. 1

3. Design a stick diagram for n-MOS Ex-OR gate. [16]

4. Design a layout diagram for CMOS inverter. [16]

7. With respect to synthesis process explain the following terms.

8. Explain about the following packaging design considerations.

(a) Electrical considerations.

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Code No: RR320405 Set No. 2

5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-

8. (a) Clearly explain the diffusion process in IC fabrication.

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Code No: RR320405 Set No. 2

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Code No: RR320405 Set No. 3

1. (a) Derive an equation for IDS of an n-channel Enhancement MOSFET operating

7. Clearly explain each step of high level design flow of an ASIC.

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Code No: RR320405 Set No. 4

4. Design a layout diagram for CMOS inverter. [16]

7. Explain the following process in the ASIC design flow.

(a) Functional gate level verification.

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Code No: RR320405 Set No. 4

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