Projects: ES6126: Algorithms to Architectures

Last Date of Submission: 14 April 2016.

General Guideline for Report Preparation
The report is required to consist of the dependence graph (DG) and the mapping
of the DG to processor space flow-graph (PSFG) wherever necessary. Otherwise it
may contain the flow-graph(s) used for the architecture(s). It should contain a
short description of the architecture(s), HDL code(s), and screen shot(s) of test
bench report(s), along with the results asked to produce in the respective
assignments. You should provide a short conclusion which need not be more
than 5 sentences.

Description of the Project Assignments

1. Design a pipelined array architecture based on seamless-delay model consisting
of 10 processing elements to compute a matrix vector product Y of a matrix X of
size 5 x 10 with a 10-point vector b. Write the HDL code for the design and
synthesize that for FPGA implementation. By running a suitable test bench show
that the design is functionally correct. Find the LUT count and maximum
operating frequency of the design. Estimate the dynamic power consumption at
frequencies f, f/2, f/3, f/4, and f/5, where f is the maximum operating frequency
of your array architecture. Take all the inputs to be integer of 8-bit width.
2. Design an array architecture consisting of 30 processing nodes to implement a
30-tap FIR filter. You can use one multiplier and one adder in each processing
node. Write the HDL code for the direct form design of this FIR filter and
synthesize that for FPGA implementation. By running a suitable test bench show
that the design is functionally correct. Find the LUT count and maximum
operating frequency of the design. Estimate the dynamic power consumption at
frequencies f, f/2, f/3, f/4, and f/5, where f is the maximum operating frequency
of your array architecture. Use fractional values of filter coefficients of your
choice in the range [-1 1]. Consider the input signal to be random fractions in the
range [-1 1]. Assume the coefficients as well as the input signals to be of 8-bit
width. Perform the scaling of input, coefficients, and output wherever you feel
necessary.
3. Design a pipelined array architecture to perform bubble sorting, where a set of
30 integers are fed sequentially as input to the architecture during each clock
period. Write the HDL code for the array architecture and synthesize them for
FPGA implementation. By running a suitable test bench show that the designs
are functionally correct. Find the LUT count and maximum operating frequency of
the designs. Estimate the dynamic power consumption at frequencies f, f/2, f/3,

f/4, and f/5, where f is the maximum operating frequency of the array
architectures.
4.

You are required to design 2-parallel and 3-parallel direct form structures for 4tap FIR filter. Write the HDL code for the designs and synthesize them for FPGA
implementation. By running suitable test benches show that the designs are
functionally correct. Find the LUT count and maximum usable frequency and
throughput in each of these two cases and compare those. Use fractional values
of filter coefficients of your choice in the range [-1 1]. Consider the input signal
to be random fractions in the range [-1 1]. Assume the coefficients as well as the
input signals to be of 8-bit width. Perform the scaling of input, coefficients, and
output wherever you feel necessary.

5.

You are required to design an 8-tap FIR filter in its direct form structure using 8
multipliers and an adder-tree consisting of 7 adders without any pipelining. Next,
you need to explore all possible pipelining options within the adder-tree and in
between adder-tree and the multiplication stage. You are allowed to use as many
registers as you need for pipelining. Synthesize and test your design without
pipelining and the designs with all possible pipelining options. From the synthesis
result, find the maximum operating frequency along with the LUT requirement
and register count in each of the designs. Use fractional values of filter
coefficients of your choice in the range [-1 1]. Consider the input signal to be
random fractions in the range [-1 1]. Assume the coefficients as well as the input
signals to be of 8-bit width. Perform the scaling of input, coefficients, and output
wherever you feel necessary.

6. Design a structure for the implementation of 16-point radix-2 decimation-infrequency (DIF) fast Fourier transform (FFT) using only 8 butterfly units, where
different stages for FFT computation are time multiplexed. Write the HDL code
for the design and synthesize that for FPGA implementation. By running suitable
test bench show that the design is functionally correct. From the synthesis result,
find the maximum operating frequency along with the LUT requirement and
register count in each of the designs. Consider the input signal to be random
fractions in the range [-1 1]. Assume the multiplying coefficients as well as the
input signals to be of 8-bit width. Perform the scaling of input, coefficients, and
output wherever you feel necessary.
7.

Explore algorithm and architecture optimization of Advanced Encryption

Standard (AES) encryption algorithm for a block length of 128 bits and 256 bits
key length. Write HDL code of your design and synthesize your design. Estimate
the area, performance, and power consumption of your design and compare that
with one of the popular/state of the art implementation. Try to reduce the energy
consumption of your design through algorithm and architecture optimization
over the state of the art low power designs. You can find some reference designs
at http://competitions.cr.yp.to/caesar-submissions.html.

8. RSA (named after the surnames of Ron Rivest, Adi Shamir, and Leonard
Adleman) is one of most widely used public-key cryptosystems. Explore
algorithm and architecture optimization of RSA encryption and decryption for
256 bits key length. Write HDL code of your design and synthesize your design.
Estimate the area, performance, and power consumption of your design and
compare that with one of the popular/state of the art implementation. Try to
reduce the energy consumption of your design through algorithm and
architecture optimization over the state of the art low power designs.
9. Design architectures to implement a direct form 32-tap FIR filter using Wallace
tree multiplier and pipeline adder tree using seamless-delay model and discretedelay model. Write the HDL code of both the designs of this FIR filter and
synthesize them for FPGA implementation. By running suitable test benches
show that the designs are functionally corrects. Compare the LUT counts and
maximum operating frequencies of both the designs. Use fractional values of
filter coefficients of your choice in the range [-1 1]. Consider the input signal to
be random fractions in the range [-1 1]. Assume the coefficients as well as the
input signals to be of 8-bit width. Perform the scaling of input, coefficients, and
output wherever you feel necessary.